HP Visualize J200, Reference Manual

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3-10 Memory System
J Class Technical Reference
MSI
60 MHz Clk
Bank 0
DRAM Data Bus (0)
MUX Data Bus
T0 T1 T2 T3 T4 T5 T6 T7
Access Latency
Precharge
DRAM Data(32 bytes)
DRAM Data(32 bytes)
T0
T1
T8 T9 T10
T1
T0 T1
T0
Access Latency
Precharge
DRAM Data(32 bytes)
DRAM Data(32 bytes)
Figure 3–6. The Stalled Pipeline – 192 MB/s (Fast Page Mode DRAM)
Performance Considerations
Figures 3–5 and 3–6 show the boundaries of memory system performance with respect to cycle time or
bandwidth. In reality, the cycle time will lie somewhere in between these two points. Additionally, these
factors contribute to “busy” system latency, which is the latency observed when the memory system is
working to satisfy the bandwidth demand.
Resource Contention
Figure 3–6 shows the behavior of the memory system when multiple transactions contend for usage of the
same memory bank. In this example, the bandwidth is limited to the cycle time of a single bank of
memory (a behavior exhibited by most memory systems.) In J Class systems, this behavior stalls the
pipeline, resulting in a lose of parallelism. As parallelism is lost, performance is likely to degrade. The
two primary factors affecting the memory system’s ability to execute transactions in parallel are memory
bank contention and DRAM Data bus contention.
Memory Bank Contention
Memory bank contention results from two memory transactions contending for usage of the same
memory bank. Under this circumstance, the losing transaction, or second one in, is delayed until the prior
transaction completes. Because transactions are constrained to complete in exact order in the design, all
subsequent transactions are effectively delayed as a result of prior transaction contention.
Memory Bus Contention
Memory bus contention exhibits much the same behavior as memory bank contention, except that it
results from two memory banks attempting to use the same DRAM Data Bus time “slot.” The term “slot”
refers to a 5 clock (4 clocks for EDO DRAM) period of time that a bank must reserve on the DRAM Data
bus in order to return data to DRAM Data Path MUX. As with bank contention, this condition also causes
a delay in returning data.
Estimating Memory Performance
The memory system contains one or more banks of DRAM in which each bank is 32 data bytes wide. The
rate at which a single bank can be cycled is called the “bank cycle time” and is limited by DRAM
technology and the timing specs for driving address and control information to the DRAMs. Currently,
the implemented bank cycle time is 166.7ns for reads (150ns for reads from EDO type DRAMs) and
200.0ns for writes.