HP Model 715/100 - Workstation, Handbook

Page: 79 / 150

Troubleshooting 4–25
HPMC Caused by a Multi-Bit Memory Parity Error
An HPMC interruption is forced when a multi-bit memory parity error is detected
during a “DMA read” operation of fetching an I/D cache line (32 bytes).
Table 4–7 shows an example of the HPMC error information retrieved from Stable
Storage by the PIM_INFO command during the Boot Administration environment.
Table 4–7. Multi-Bit Memory Parity Error
Check Type
CPU State
Cache Check
TLB Check
Bus Check
Assists Check
Assists State
System Responder Address
System Requester Address
System Controller Status
0x20000000
0x9e000004
0x00000000
0x00000000
0x00210004
0x00000000
0x00000000
0x00nnnnnn
0x00000000
0x00000nnn
Value Word
Interpreting the Table
The values in the Bus Check and System Responder Address words indicate that a
multi-bit memory parity error was detected by logic in the memory module. Ignore
the value in the System Controller Status word.
The System Responder contains the SPA of the faulty SIMM pair. To determine the
pair, you need to know the following:
The SIMM pair sizes and their locations (for example, 16 MB SIMMs in Pair 1
and 8 MB Simms in Pair 0)
The total memory size in HEX