HP Model 715/100 - Workstation, Handbook

Page: 83 / 150

Troubleshooting 4–29
HPMC Caused by a Data Cache Parity Error
An HPMC interruption is forced when a data parity error is detected during a Load
instruction to the memory address space or during a data cache flush operation.
Table 4–9 shows an example of the HPMC error information retrieved from Stable
Storage by the PIM_INFO command during the Boot Administration environment.
Table 4–9. Processor Module Error (Data Cache Parity)
Check Type
CPU State
Cache Check
TLB Check
Bus Check
Assists Check
Assists State
System Responder Address
System Requester Address
System Controller Status
0x80000000
0x9e000004
0x40000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000nnn
Value Word
The value in the CPU State word indicates that register values and addresses stored
in Stable Storage at the time of the HPMC were saved.
The value on the Cache Check word identifies that logic in the processor module
detected a (data) cache parity error. Ignore the value in the System Controller Status
word.
For Model 715/75, replace the PCX-T module. For any other Model 715, replace the
Motherboard.