Honeywell bendis king KLN 94, Maintenance Manual

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BENDIX/KING KLN 94
Rev 0, Sept/2000 15599M00.JA Page 4-39
U5043-C and U5043-D are connected to the external lighting bus signals LIGHTING_28V_LO and
LIGHTING_14V. The inverting summing amplifier U5043-D uses R5201, R5122, and R5107 to
scale the voltage. U5043-C filters and inverts the DC voltage level so the Host microprocessor
can use this voltage to control the intensity of the button and nomenclature backlighting LEDs.
4.3.4.2.28 DC Roll Steering Control.
The Host microprocessor controls digital pot U5045-A at a voltage level b5Vdc and
ground. This level is scaled, level shifted, and filtered by U5037-B, C5161, C5171, R5114, R5115,
R5113, and R5116. Series resistors R5126 and R5125 eliminate unwanted oscillation and in-
crease RF immunity. Capacitor C5179 reduces noise.
4.3.4.2.29 Contrast Control
When DISPLAY_RST is low, the Host microprocessor controls digital pot U5045-D at a voltage
level b5Vdc and ground. R5123 and C5173 filter the signal. It is then buffered and driv-
en to the display module as CONTRAST adjust by voltage follower U5036-A.
4.3.4.2.30 Hardware Reset Circuit
When the KLN 94 is powered up, the MAIN_RESET signal lines will only be released when the
+5V supply is stable. After U5002 senses a 5V, the MAIN_SRAM_CS_INn is passed
through to MAIN_SRAM_CSn signal along with ap5V to VCC_BAT. The battery voltage
at pin 1 of U5002 will be present at pins 2 and 12 only when +5V at pin 3 is below 4.75 Vdc. The
PFO output of U5002 will indicate to the Host microprocessor the status of the battery. Q5034
inverts the MAIN_RESET signal along with making an open collector signal which allows other de-
vices to drive the MAIN_HW_RESETn signal line.
4.3.4.2.31 Battery Measurement
The voltage of the internal battery at E3 is routed through the voltage follower U5036-B, to be mea-
sured by the ADC module of the Host microprocessor U5031.
4.3.4.2.32 Button LED Drive Lo Switch
The active low drive signal for the front panel button backlighting is controlled by transistors
Q5002-A and Q5002-B depending on whether the unit is in the normal operational mode or is
turned off.
In the normal operational mode, reset clamp transistor Q5009 is open. This permits the Host mi-
croprocessor’s PWM drive signal, BUTTON_LED_PWM, to be buffered by drive transistors
Q5001 and Q5006. Resistors R5142, R5134, R5137, and R5005 dampen high current noise tran-
sients. The buffered PWM signal drives the gate of Q5002-A, which causes the button backlight-
ing LEDs to turn on during that portion of the PWM cycle when Q5002-A is active. Note that since
+5V is active, clamp transistor Q5010 is kept on via R5143, thus preventing Q5002-B to interfere
with the PWM-based control of Q5002-A.
When the unit is turned off, the aircraft bus voltage applied via the PROT_AC_PWR line drive the
gate of Q5002-B via resistor divider R5008 and R5144. Since the +5V supply is off, clamp tran-
sistor Q5010 shall be kept off, permitting Q5002-B to stay on. This causes the button backlighting
LEDs to be on.
The timing circuit consisting of R5143, CR5002, and C5005 prevents unwanted bursts of light dur-
ing transitions of the unit between the normal operation and off states.
4.3.4.2.33 Display Backlighting LED Drive Lo Switch
The active low drive signal for the LED backlight within the LCD display is controlled by transistors
Q5004-A and 5004-B which are paralleled for lower on resistance.