Honeywell bendis king KLN 94, Maintenance Manual

Page: 29 / 172

BENDIX/KING KLN 94
Page 4-30 15599M00.JA Rev 0, Sept/2000
4.3.4.2.7 Graphics Microprocessor
The Graphics microprocessor handles two main functions within the KLN 94. The first function is
the interface to the LCD display. The majority of the data shown on the display is generated from
the Host Microprocessor and passed to the Graphics microprocessor via the Dual Port SRAM
(U5008). The Graphics microprocessor formats this data and presents it to the Graphics Control-
ler chip within the LCD display module.
The second function is the interface to/from the Compact Flash Memory Card. This card holds all
of the NAV Database, as well as, the Terrain Database. When required, the NAV Database is
passed to the Host microprocessor for updating via the Dual Port Ram (U5008). The Terrain Da-
tabase stays local to the Compact Flash Memory Card and is accessed as needed by the Graph-
ics microprocessor when displaying the "Moving Map" screen.
The Graphics microprocessor (U5030) is an Intel 80386EX. The system clock is 32MHz and can
be monitored on U5030 pin 112. A 64MHz crystal clock (Y5001) is the reference clock.
The Graphics microprocessor can be placed into the reset state by either of two conditions. The
Graphics microprocessor receives a reset, high true, from the signal line GRAPHICS_RESET into
pin 119. This signal is an output of U5029 pin 14. Two conditions can cause this reset.
1) The reset controller chip (U5002) detects that VCC has fallen below or has not risen to an ac-
ceptable limit. It then asserts the MAIN_RESETn signal that is decoded in U5029 and asserts
GRAPHICS_RESET.
2) Duart (U5042), which is controlled by the Host microprocessor, can force an assertion of the
DISPLAY_RST signal (pin 14) which is decoded in U5029 and asserts GRAPHICS_RESET.
Upon the release of Graphics Reset, the Graphics microprocessor starts addressing code space
data from the programmed flash part (U5017) starting with all address lines high as the first ad-
dress. The memory map of the Graphics Microprocessor is depicted in the following table.
TABLE 4-5 Graphics Microprocessor Address Map
All R/W accesses of the Graphics microprocessor are terminated by the GRAPHICS_READYn
signal. Ready signals are generated external to the Graphics microprocessor by U5038 when ac-
cessing local Ram, Flash, and Compact Flash Database memory devices and by U5041 when ad-
dressing with MEMCSn to the LCD display module. GRAPHICS_READYn is generated internally
in the 386EX when accessing IOCSn of the LCD.
The Graphics microprocessor can monitor up to 5 interrupts of which only 4 are used. The follow-
ing table is the descriptions of the interrupts monitored.
uP Chip Select Designation Size Space Data Size, bits Wait State Ready Source
CS0# SRAM_CS1n 1024K 0000000-00FFFFF 16 2 External
CS5# SRAM_CS2n 1024K 0100000-01FFFFF 16 2 External
CS1# MEMCSn 128K 0800000-081FFFF 16 Ready
Controlled
External
CS2# IOCSn 2K 0840000-08407FF 8 1 Internal
CS3# DPRAM_CSn 2K 0850000-08507FF 8 9 Max External
CS4# CF_CSn 2K 0860000-08607FF 16 10 Max External
UCS# CODE_CSn 1024K 3F00000-3FFFFFF 16 3 External