Honeywell bendis king KLN 94, Maintenance Manual

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BENDIX/KING KLN 94
Page 4-34 15599M00.JA Rev 0, Sept/2000
4.3.4.2.12.3 Main EPLD Functionality
The Main logic is spread across three EPLDs identified as MAIN1 (U5029), MAIN2 (U5041), and
MAIN3 (U5023) on the schematic. Refer to other sections of this document for discussion of spe-
cific functions assigned to the MAIN EPLDs. The following paragraphs give an overview of the
functions.
4.3.4.2.12.4 Main 1 EPLD Controller
The MAIN1 EPLD controller holds a variety of functions supporting the Host microprocessor.
4.3.4.2.12.4.1 Decoding for the DUART Chip.
Duart Chip enable/Discrete Chip select 3 by decoding the MAIN_DUART_CSn signal from the mi-
croprocessor along with MAIN_ADDRESS_BUS4. When both signals are low DUART_CEn is as-
serted low and when only MAIN_DUART_CSn is low DISCRETE_CS3n is asserted low.
4.3.4.2.12.4.2 Decoding for the NAV Database Chip.
Database Decoder logic decodes the MAIN_DBXOVER_CS and MAIN_DB_CSn chip selects
along with MAIN_WRn signal from the microprocessor. If either MAIN_DB_CSn or
MAIN_DBXOVER_CSn is asserted low then DBASE_LOCAL_CSn is asserted low. In this condi-
tion, with MAIN_WRn high, a read access is done to the local Database chip. If MAIN_WRn is
low, data is written to the local Database chip.
4.3.4.2.12.4.3 Lower and upper chip enable decoding of the Flash memory.
This is accomplished by asserting MAIN_ROM_CSn or MAIN_XROM_CSn. With the assertion of
either of these signals low will assert MAIN_8M_BOOT_CSn. When MAIN_XROM_CSn is high
and MAIN_ROM_CSn is low, the MAIN_8M_ADDRESS_A19 signal line for the flash is asserted
low. This is the lower Flash addressing mode.
4.3.4.2.12.4.4 Decoding for the Static RAM Chip.
Both MAIN_SRAM1_CSn and MAIN_SRAM2_CSn are decoded to assert MAIN_SRAM_CS_INn
low. This addressing space is shared with the Database and PERIPH chip selects as well. If ei-
ther of the Database or the PERIPH chip selects are asserted the MAIN_SRAM_CS_INn signal is
held high regardless of the status of MAIN_SRAM1_CSn or MAIN_SRAM2_CSn.
4.3.4.2.12.4.5 Enabling of the HW_PGM_EN and / or WPn signals.
Decode logic handles the HW_PGM_EN and WPn signals to enable the write capabilities for the
Flash chips. If either the BDM or the JTAG connectors are connected and RESETn is not asserted
low, then WPn and HW_PGM_EN will be high. When both the CURSOR and the ENTER keys
are depressed simultaneously on the front panel when power is applied to the unit, only
HW_PGM_EN will be asserted high and WPn will remain low. This is intended for unit application
code programming only. WPn must be driven high when programming the Boot portion of the
Flash memory devices.
4.3.4.2.12.4.6 Creation of the DISCRETE_CS1n and DISCRETE_CS2n signals.
A 3-to-8 decoder monitors the MAIN_ADDRESS_BUS lines 1 through 3, as well as,
MAIN_DISCRETE_CSn from the microprocessor to generate the DISCRETE_CS1n and
DISCRETE_CS2n signals. The DISCRETE_CS1n signal will be asserted low when all three
MAIN_ADDRESS_BUS signals are low and MAIN_DISCRETE_CSn is low.