Rev. 1.71
88
April 11, 2017
Rev. 1.71
89
April 11, 2017
HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM
HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM
PTMnRPH Register
Bit
7
6
5
4
3
2
1
0
Name
—
—
—
—
—
—
D9
D8
R/W
—
—
—
—
—
—
R/W
R/W
POR
—
—
—
—
—
—
0
0
Bit 7~2
Unimplemented, read as "0"
Bit 1~0
PTMnRPH
: PTM CCRP High Byte Register bit 1 ~ bit 0
PTM 10-bit CCRP bit 9 ~ bit 8
Periodic Type TM Operating Modes
The Periodic Type TM can operate in one of five operating modes, Compare Match Output Mode,
PWM Output Mode, Single Pulse Output Mode, Capture Input Mode or Timer/Counter Mode. The
operating mode is selected using the PTnM1 and PTnM0 bits in the PTMnC1 register.
Compare Match Output Mode
To select this mode, bits PTnM1 and PTnM0 in the PTMnC1 register, should be all cleared to
00 respectively. In this mode once the counter is enabled and running it can be cleared by three
methods. These are a counter overflow, a compare match from Comparator A and a compare match
from Comparator P. When the PTnCCLR bit is low, there are two ways in which the counter can be
cleared. One is when a compare match occurs from Comparator P, the other is when the CCRP bits
are all zero which allows the counter to overflow. Here both the PTMAnF and PTMPnF interrupt
request flags for Comparator Aand Comparator P respectively, will both be generated.
If the PTnCCLR bit in the PTMnC1 register is high then the counter will be cleared when a compare
match occurs from Comparator A. However, here only the PTMA
n
F interrupt request flag will
be generated even if the value of the CCRP bits is less than that of the CCRA registers. Therefore
when PTnCCLR is high no PTMPnF interrupt request flag will be generated. In the Compare
Match Output Mode, the CCRA can not be set to “0”. If the CCRA bits are all zero, the counter will
overflow when its reaches its maximum 10-bit, 3FF Hex, value, however here the PTMA
n
F interrupt
request flag will not be generated.
As the name of the mode suggests, after a comparison is made, the TM output pin, will change state.
The TM output pin condition however only changes state when a PTMAnF interrupt request flag is
generated after a compare match occurs from Comparator A. The PTMPnF interrupt request flag,
generated from a compare match from Comparator P, will have no effect on the TM output pin.
The way in which the TM output pin changes state are determined by the condition of the PTnIO1
and PTnIO0 bits in the PTMnC1 register. The TM output pin can be selected using the PTnIO1
and PTnIO0 bits to go high, to go low or to toggle from its present condition when a compare
match occurs from Comparator A. The initial condition of the TM output pin, which is setup after
the PTnON bit changes from low to high, is setup using the PTnOC bit. Note that if the PTnIO1,
PTnIO0 bits are zero then no pin change will take place.