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Holtek HT66F002, Manual

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Holtek HT66F002 Manual Download Page 80

Rev. 1.71

80

April 11, 2017

Rev. 1.71

81

April 11, 2017

HT66F002/HT66F0025/HT66F003/HT66F004

Cost-Effective A/D Flash MCU with EEPROM

HT66F002/HT66F0025/HT66F003/HT66F004

Cost-Effective A/D Flash MCU with EEPROM

Single Pulse Mode

To select this mode, bits ST0M1 and ST0M0 in the STM0C1 register should be set to 10 
respectively and also the ST0IO1 and ST0IO0 bits should be set to 11 respectively. The Single Pulse 
Output Mode, as the name suggests, will generate a single shot pulse on the STM output pin. 
The trigger for the pulse output leading edge is a low to high transition of the ST0ON bit, which 
can be implemented using the application program. However in the Single Pulse Mode, the ST0ON 
bit can also be made to automatically change from low to high using the external STCK0 pin, 
which will in turn initiate the Single Pulse output. When the ST0ON bit transitions to a high level, 
the counter will start running and the pulse leading edge will be generated. The ST0ON bit should 
remain high when the pulse is in its active state. The generated pulse trailing edge will be generated 
when the ST0ON bit is cleared to zero, which can be implemented using the application program or 
when a compare match occurs from Comparator A.

S/W Command 

SET

“

ST0ON

”

or

STCK0 Pin 

Transition

Trailing Edge

S/W Command 

CLR

“

ST0ON

”

or

CCRA Compare 

Match

STP0/STP0B Output Pin

Pulse Width = CCRA Value

Leading Edge

ST0ON bit

0 

→

 1

ST0ON bit

1 

→

 0

Single Pulse Generation 

Summary of Contents for HT66F002

Page 1: ...Cost Effective A D Flash MCU with EEPROM HT66F002 HT66F0025 HT66F003 HT66F004 Revision V1 71 Date April 11 2017...

Page 2: ...HT66F004 18 Power on Reset Electrical Characteristics 18 System Architecture 19 Clocking and Pipelining 19 Program Counter 20 Stack 21 Arithmetic and Logic Unit ALU 21 Flash Program Memory 22 Structur...

Page 3: ...ystem Clocks 38 System Operation Modes 39 Control Register 40 Operating Mode Switching 42 NORMAL Mode to SLOW Mode Switching 43 SLOW Mode to NORMAL Mode Switching 44 Entering the SLEEP0 Mode 44 Enteri...

Page 4: ...se Mode 80 Capture Input Mode 82 Periodic Type TM PTM 83 Periodic TM Operation 83 Periodic Type TM Register Description 84 Periodic Type TM Operating Modes 88 Compare Match Output Mode 88 Timer Counte...

Page 5: ...lication Circuits 121 Instruction Set 122 Introduction 122 Instruction Timing 122 Moving and Transferring Data 122 Arithmetic Operations 122 Logical and Rotate Operation 123 Branches and Control Trans...

Page 6: ...instruction Peripheral Features Flash Program Memory 1K 14 2K 15 RAM Data Memory 64 8 96 8 True EEPROM Memory 32 8 Watchdog Timer function Up to 18 bidirectional I O lines Software controlled 4 SCOM...

Page 7: ...ostile electrical environments A full choice of HIRC and LIRC oscillator functions are provided including a fully integrated system oscillator which requires no external components for its implementat...

Page 8: ...for HT66F004 Pin Assignment HT66F002 10 MSOP A 10 9 8 7 6 1 2 3 4 5 VDD AVDD PA6 STP0I STCK0 PA5 INT STP0B AN3 PA7 INT STCK0 RES ICPCK PA4 VSS AVSS PA0 STP0 STP0I AN0 ICPDA PA1 STP0B AN1 VREF PA2 INT...

Page 9: ...N5 VREFO PA7 PTP1 AN6 PB0 INT0 AN0 PB1 INT1 AN1 HT66F003 HT66V003 16 NSOP A VSS AVSS PA0 STP0I AN0 OCDSDA ICPDA PA1 AN1 VREF PA2 INT STCK0 AN2 OCDSCK ICPCK PA3 INT STCK0 AN3 VDD AVDD PA6 PTCK1 STP0I S...

Page 10: ...ICPDA ST CMOS ICP Data Line PA1 STP0B AN1 VREF PA1 PAWU PAPU PASR ST CMOS General purpose I O Register enabled pull up and wake up STP0B PASR CMOS TM0 STM inverting output AN1 PASR AN ADC input chann...

Page 11: ...STP0I PASR IFS0 ST TM0 STM input AN0 PASR AN ADC input channel 0 OCDSDA ST CMOS On Chip Debug System Data Line OCDS EV only ICPDA ST CMOS ICP Data Line PA1 AN1 VREF PA1 PAWU PAPU PASR ST CMOS General...

Page 12: ...TP1I VREFO PB0 PBPU PBSR ST CMOS General purpose I O Register enabled pull up PTP1I PBSR IFS0 ST TM1 PTM input VREFO PBSR AN ADC reference voltage output PB1 PTCK1 STP0B PB1 PBPU PBSR ST CMOS General...

Page 13: ...O Register enabled pull up and wake up PTCK1 PASR ST PTM1 clock input AN3 PASR AN ADC input channel 3 PA5 AN4 VREF PA5 PAWU PAPU PASR ST CMOS General purpose I O Register enabled pull up and wake up A...

Page 14: ...eral purpose I O Register enabled pull up RES RSTC ST External reset input VDD VDD PWR Digital positive power supply AVDD AVDD PWR Analog positive power supply VSS VSS PWR Digital negative power suppl...

Page 15: ...No load fSYS fH 64 ADC off WDT enable LVR enable 0 5 0 8 mA 5V 0 8 1 1 mA IIDLE0 IDLE0 Mode Standby Current LIRC on 3V No load ADC off WDT enable LVR disable 1 3 3 0 A 5V 5 0 10 A IIDLE1 IDLE1 Mode St...

Page 16: ...Hz tTIMER xTCKn xTPnI Input Pulse Width 0 3 s tRES External Reset Low Pulse Width 10 s tINT Interrupt Pulse Width 0 3 s tEERD EEPROM Read Time 2 4 tSYS tEEWR EEPROM Write Time 2 5 ms tSST System Start...

Page 17: ...2 0 mA 5V No load tADCK 0 5 s 1 5 3 0 mA tADCK A D Converter Clock Period 2 7 5 5V 0 5 10 s tADC A D Conversion Time Include Sample and Hold Time 2 7 5 5V 12 bit ADC 16 20 tADCK tADS A D Converter Sa...

Page 18: ...ctrical Characteristics HT66F004 Symbol Parameter Test Conditions Min Typ Max Unit VDD Conditions IBIAS VDD 2 Bias Current for LCD 5V ISEL 1 0 00 17 5 25 0 32 5 A ISEL 1 0 01 35 50 65 A ISEL 1 0 10 70...

Page 19: ...e simple addressing methods of these registers along with additional architectural features ensure that a minimum of external components is required to provide a functional I O and A D control system...

Page 20: ...uctions requiring jumps to non consecutive addresses such as a jump instruction a subroutine call interrupt or reset etc the microcontroller manages program control by loading the required address int...

Page 21: ...struction can still be executed which will result in a stack overflow Precautions should be taken to avoid such cases which might cause unpredictable program branching If the stack is overflow the fir...

Page 22: ...k up Table Initialisation Vector 15 bits Interrupt Vectors Look up Table 7FFH 01CH HT66F003 HT66F004 018H Initialisation Vector 14 bits Interrupt Vectors Look up Table HT66F0025 7FFH Program Memory St...

Page 23: ...re should be taken to ensure its protection if both the main routine and Interrupt Service Routine use table read instructions If using the table read instructions the Interrupt Service Routines may c...

Page 24: ...it programming of the device are beyond the scope of this document and will be supplied in supplementary literature HT66F002 HT66F0025 Writer_VDD ICPDA ICPCK Writer_VSS To other Circuit VDD PA0 PA7 VS...

Page 25: ...in Bank 1 Switching between the different Data Memory banks is achieved by setting the Bank Pointer to the correct value The start address of the Data Memory for all devices is the address 00H Genera...

Page 26: ...EEA 12H 19H 18H 1BH 1AH 1DH 1CH 1FH 1EH 13H 14H 15H 16H 17H INTEG Unused STM0AL PAPU PAWU 20H 21H 22H 29H 28H 2BH 2AH 2DH 2CH 2EH 3FH 23H 24H 25H 26H 27H BP STM0DL STM0C1 STM0DH PA PAC STM0C0 INTC0 U...

Page 27: ...17H INTEG Unused STM0AL PAPU PAWU 20H 21H 22H 29H 28H 2BH 2AH 2DH 2CH 2EH 23H 24H 25H 26H 27H BP STM0DL STM0C1 STM0DH PA PAC STM0C0 INTC0 Unused read as 00 EED Unused Unused STM0AH Unused Unused MFI0...

Page 28: ...PA PAC INTC0 Unused read as 00 EED Unused Unused PTM0AL Unused Unused MFI0 Unused WDTC TBC SMOD1 PASR RSTC SADC1 SADC0 SADC2 SADOL SADOH Bank0 Bank1 Bank0 Bank1 PTM1AH PTM1DH PTM1DL PTM1AL PTM1C1 PTM...

Page 29: ...operation Memory Pointers MP0 MP1 Two Memory Pointers known as MP0 and MP1 are provided These Memory Pointers are physically implemented in the Data Memory and can be manipulated in the same way as no...

Page 30: ...the Data Memory resulting in higher programming and timing overheads Data transfer operations usually involve the temporary storage function of the Accumulator for example when transferring data betwe...

Page 31: ...he status of the latest operations C is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation otherwise C is cleared C i...

Page 32: ...e place during a subtraction operation C is also affected by a rotate through carry instruction EEPROM Data Memory These devices contain an area of internal EEPROM Data Memory EEPROM which stands for...

Page 33: ...g the MP1 Memory Pointer and Indirect Addressing Register IAR1 Because the EEC control register is located at address 40H in Bank 1 the MP1 Memory Pointer must first be set to the value 40H and the Ba...

Page 34: ...ROM read operations Bit 0 RD EEPROM Read Control 0 Read cycle has finished 1 Activate a read cycle This is the Data EEPROM Read Control Bit and when set high by the application program will activate a...

Page 35: ...automatically cleared to zero by the microcontroller informing the user that the data has been written to the EEPROM The application program can therefore poll the WR bit to determine when the write c...

Page 36: ...the devices should not enter the IDLE or SLEEP mode until the EEPROM read or write operation is totally complete Otherwise the EEPROM read or write operation will fail Programming Examples Reading da...

Page 37: ...of higher power requirements while the opposite is of course true for the lower frequency oscillator With the capability of dynamically switching between fast and slow system clock these devices have...

Page 38: ...Time Base Interrupts Operating Modes and System Clocks Present day applications require that their microcontrollers have high performance but often still demand that they consume as little power as po...

Page 39: ...ller the NORMAL Mode and SLOW Mode The remaining four modes the SLEEP0 SLEEP1 IDLE0 and IDLE1 modes are used when the microcontroller CPU is switched off to conserve power Operating Mode Description C...

Page 40: ...from driving the CPU but some peripheral functions will remain operational such as the Watchdog Timer and TMs In the IDLE0 Mode the system oscillator will be stopped IDLE1 Mode The IDLE1 Mode is ente...

Page 41: ...ntrol bit and determines what happens when the HALT instruction is executed If this bit is high when a HALT instruction is executed the device will enter the IDLE Mode In the IDLE1 Mode the CPU will s...

Page 42: ...in portable applications In simple terms Mode Switching between the NORMAL Mode and SLOW Mode is executed using the HLCLK bit and CKS2 CKS0 bits in the SMOD register while Mode Switching from the NORM...

Page 43: ...setting the HLCLK bit to 0 and setting the CKS2 CKS0 bits to 000 or 001 in the SMOD register This will then use the low speed system oscillator which will consume less power Users may decide to do th...

Page 44: ...ing the SLEEP0 Mode There is only one way for the devices to enter the SLEEP0 Mode and that is to execute the HALT instruction in the application program with the IDLEN bit in SMOD register equal to 0...

Page 45: ...ON bit in SMOD1 register equal to 0 When this instruction is executed under the conditions described above the following will occur The system clock will be stopped and the application program will st...

Page 46: ...ternal falling edge on Port A A system interrupt A WDT overflow If the system is woken up by an external reset the device will experience a full system reset however If these devices are woken up by a...

Page 47: ...sabled using the WDTC register Watchdog Timer Control Register A single register WDTC controls the required timeout period as well as the enable disable operation The WRF software reset flag will be i...

Page 48: ...unknown location or enters an endless loop the clear WDT instructions will not be executed in the correct manner in which case the Watchdog Timer will overflow and reset the device With regard to the...

Page 49: ...ned state and ready to execute the first program instruction After this power on reset certain important internal registers will be set to defined states before the program commences One of these regi...

Page 50: ...g proper reset operation For this reason it is recommended that an external RC network is connected to the RES pin whose additional time delay will ensure that the RES pin remains low for an extended...

Page 51: ...ion 01010101 Configured as PC2 pin or other function 10101010 Configured as RES pin Other Values Inhibit to use All reset will reset this register as POR value except WDT time out Hardware warm reset...

Page 52: ...ribe elsewhere Watchdog Time out Reset during Normal Operation The Watchdog time out Reset during normal operation is the same as an LVR reset except that the Watchdog time out flag TO will be set to...

Page 53: ...t u u LVR reset during NORMAL or SLOW Mode operation 1 u WDT time out reset during NORMAL or SLOW Mode operation 1 1 WDT time out reset during IDLE or SLEEP Mode operation Note u stands for unchanged...

Page 54: ...0 0 0 0 0 11 0 0 0 0 0 11 0 0 0 0 0 11 0 0 0 0 0 11 u u u u u u u INTEG 0 0 0 0 0 0 0 0 u u INTC0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u INTC1 0 0 0 0 0 0 0 0 0 0 0 0 0...

Page 55: ...0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u PTM0DL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u PTM0DH 0 0 0 0 0 0 0 0 u u PTM0AL 0 0 0 0 0...

Page 56: ...tput operations For input operation these ports are non latching which means the inputs must be ready at the T2 rising edge of instruction MOV A m where m denotes the port address For output operation...

Page 57: ...resistors all I O pins when configured as an input have the capability of being connected to an internal pull high resistor These pull high resistors are selected using register PAPU PCPU and are impl...

Page 58: ...O Port A bit 7 bit 0 Wake Up Control 0 Disable 1 Enable I O Port Control Registers Each I O port has its own control register known as PAC PCC to control the input output configuration With these cont...

Page 59: ...Control 0 Output 1 Input Pin shared Functions The flexibility of the microcontroller range is greatly enhanced by the use of pins that have more than one function Limited numbers of pins can force se...

Page 60: ...on a wide range of different functions can be incorporated into even relatively small package sizes PASR Register HT66F002 HT66F0025 Bit 7 6 5 4 3 2 1 0 Name PAS7 PAS6 PAS5 PAS4 PAS3 PAS2 PAS1 PAS0 R...

Page 61: ...4 Pin Shared Control Bit 0 PA3 INT STCK0 1 AN3 Bit 3 PAS3 Pin Shared Control Bit 0 PA2 INT STCK0 1 AN2 Bit 2 1 PAS2 PAS1 Pin Shared Control Bits 0X PA1 10 VREF 11 AN1 Bit 0 PAS0 Pin Shared Control Bit...

Page 62: ...hared Control Bits 0 PB1 PTCK1 1 STP0B Bit 0 PBS0 Pin Shared Control Bit 0 PB0 PTP1I 1 VREFO PBSR Register HT66F004 Bit 7 6 5 4 3 2 1 0 Name PBS6 PBS5 PBS4 PBS3 PBS2 PBS1 PBS0 R W R W R W R W R W R W...

Page 63: ...efault 01 INT on PA2 10 INT on PA3 11 INT on PA7 IFS0 Register HT66F003 Bit 7 6 5 4 3 2 1 0 Name PTCK1PS1 PTCK1PS0 STCK0PS STP0IPS PTP1IPS INTPS1 INTPS0 R W R W R W R W R W R W R W R W POR 0 0 0 0 0 0...

Page 64: ...e internal structures of some generic I O pin types As the exact logical construction of the I O pin will differ from these drawings they are supplied as a guide only to assist with the functional und...

Page 65: ...e port control registers are then programmed to setup some pins as outputs these output pins will have an initial high output value unless the associated port data registers are first programmed Selec...

Page 66: ...tures and differences between the two types of TMs are summarised in the accompanying table Function STM PTM Timer Counter I P Capture Compare Match Output PWM Channels 1 1 Single Pulse Output 1 1 PWM...

Page 67: ...ch have two output pins with the label xTPn and xTPnB When the TM is in the Compare Match Output Mode these pins can be controlled by the TM to switch to a high or low level or to toggle when a compar...

Page 68: ...ures Accessing the CCRA or CCRP low byte register without following these access procedures will result in unpredictable values 8 bit Buffer PTMnDH PTMnDL PTMnRPH PTMnRPL PTMnAH PTMnAL PTM Counter Reg...

Page 69: ...tors with the names Comparator A and Comparator P These comparators will compare the value in the counter with CCRP and CCRA registers The CCRP is 3 bit wide whose value is compared with the highest 3...

Page 70: ...er The counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again bit 6 4 ST0CK2 ST0CK0 Select STM Coun...

Page 71: ...Bit 7 6 5 4 3 2 1 0 Name ST0M1 ST0M0 ST0IO1 ST0IO0 ST0OC ST0POL ST0DPX ST0CCLR R W R W R W R W R W R W R W R W R W POR 0 0 0 0 0 0 0 0 bit 7 6 ST0M1 ST0M0 Select STM0 Operating Mode 00 Compare Match...

Page 72: ...ration depends upon whether STM is being used in the Compare Match Output Mode or in the PWM output Mode Single Pulse Output Mode It has no effect if the STM is in the Timer Counter Mode In the Compar...

Page 73: ...1 0 Name D9 D8 R W R R POR 0 0 bit 7 2 Unimplemented read as 0 bit 1 0 STM0 Counter High Byte Register bit 1 bit 0 STM0 10 bit Counter bit 9 bit 8 STM0AL Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4...

Page 74: ...r here only the STMA0F interrupt request flag will be generated even if the value of the CCRP bits is less than that of the CCRA registers Therefore when ST0CCLR is high no STMP0F interrupt request fl...

Page 75: ...le Output Select Now ST0IO 1 0 10 Active High Output Select Output not affected by STMA0F flag Remains High until reset by ST0ON bit ST0CCLR 0 ST0M 1 0 00 ST0PAU Resume Stop Time CCRP 0 CCRP 0 ST0POL...

Page 76: ...STMA0F flag Remains High until reset by ST0ON bit ST0CCLR 1 ST0M 1 0 00 ST0PAU Resume Stop Time CCRA 0 ST0POL Output Pin Reset to initial value Output inverts when ST0POL is high Output controlled by...

Page 77: ...CCRA and CCRP registers are used to generate the PWM waveform one register is used to clear the internal counter and thus control the PWM waveform frequency while the other one is used to control the...

Page 78: ...Counter Stop If ST0ON bit low Counter reset when ST0ON returns high PWM resumes operation Output controlled by Other pin shared function Time ST0DPX 0 ST0M 1 0 10 ST0POL Output Inverts When ST0POL 1 S...

Page 79: ...CRA Counter Stop If ST0ON bit low Counter reset when ST0ON returns high PWM resumes operation Output controlled by Other pin shared function Time ST0DPX 1 ST0M 1 0 10 ST0POL Output Inverts When ST0POL...

Page 80: ...lse Mode the ST0ON bit can also be made to automatically change from low to high using the external STCK0 pin which will in turn initiate the Single Pulse output When the ST0ON bit transitions to a hi...

Page 81: ...ger Software Clear Software Trigger Software Trigger Single Pulse Mode Note 1 Counter stopped by CCRA match 2 CCRP is not used 3 The pulse is triggered by setting the ST0ON bit high 4 In the Single Pu...

Page 82: ...CCRP value can be used to control the maximum counter value When a CCRP compare match occurs from Comparator P a STM interrupt will also be generated Counting the number of overflow interrupt signals...

Page 83: ...external clock source There are two internal comparators with the names Comparator A and Comparator P These comparators will compare the value in the counter with the CCRA and CCRP registers The only...

Page 84: ...List n 0 or 1 PTMnC0 Register Bit 7 6 5 4 3 2 1 0 Name PTnPAU PTnCK2 PTnCK1 PTnCK0 PTnON R W R W R W R W R W R W POR 0 0 0 0 0 Bit 7 PTnPAU PTM Counter Pause Control 0 run 1 pause The counter can be...

Page 85: ...C PTnPOL PTnCKS PTnCCLR R W R W R W R W R W R W R W R W R W POR 0 0 0 0 0 0 0 0 Bit 7 6 PTnM1 PTnM0 Select PTM Operation Mode 00 Compare Match Output Mode 01 Capture Input Mode 10 PWM Mode or Single P...

Page 86: ...initial high PWM Mode Single Pulse Output Mode 0 Active low 1 Active high This is the output control bit for the TM output pin Its operation depends upon whether TM is being used in the Compare Match...

Page 87: ...er bit 1 bit 0 PTM 10 bit Counter bit 9 bit 8 PTMnAL Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R W R W R W R W R W R W R W R W R W POR 0 0 0 0 0 0 0 0 Bit 7 0 PTMnAL PTM CCRA Low Byte...

Page 88: ...the PTMnC1 register is high then the counter will be cleared when a compare match occurs from Comparator A However here only the PTMAnF interrupt request flag will be generated even if the value of th...

Page 89: ...Level Low if PTnOC 0 Output Toggle with PTMAnF flag Note PTnIO 1 0 10 Active High Output select Here PTnIO 1 0 11 Toggle Output select Output not affected by PTMAnF flag Remains High until reset by PT...

Page 90: ...0 10 Active High Output select Here PTnIO 1 0 11 Toggle Output select Output not affected by TnAF flag Remains High until reset by PTnON bit Output Pin Reset to Initial value Output controlled by othe...

Page 91: ...both the period and duty cycle of the PWM waveform can be controlled the choice of generated waveform is extremely flexible In the PWM mode the PTnCCLR bit has no effect as the PWM period Both of the...

Page 92: ...PTnON bit low Counter Reset when PTnON returns high PTnDPX 0 PTnM 1 0 10 PWM Duty Cycle set by CCRA PWM resumes operation Output controlled by other pin shared function Output Inverts When PTnPOL 1 P...

Page 93: ...art running and the pulse leading edge will be generated The PTnON bit should remain high when the pulse is in its active state The generated pulse trailing edge will be generated when the PTnON bit i...

Page 94: ...lse Width set by CCRA Output Inverts when PTnPOL 1 No CCRP Interrupts generated PTM O P Pin PTnOC 0 PTCKn pin Software Trigger Cleared by CCRA match PTCKn pin Trigger Auto set by PTCKn pin Software Tr...

Page 95: ...rrupt generated Irrespective of what events occur on the PTPnI or PTCKn pin the counter will continue to free run until the PTnON bit changes from high to low When a CCRP compare match occurs the coun...

Page 96: ...X Counter Stop PTnIO 1 0 Value XX YY XX YY Active edge Active edge Active edge 00 Rising edge 01 Falling edge 10 Both edges 11 Disable Capture Capture Input Mode n 0 or 1 Note 1 PTnM 1 0 01 and active...

Page 97: ...se signals directly into a 12 bit digital value The external or internal analog signal to be converted is determined by the SAINS and SACS bit fields Note that when the internal analog signal is to be...

Page 98: ...DC0 START ADBZ ENADC ADRFS SACS2 SACS1 SACS0 SADC1 SAINS2 SAINS1 SAINS0 SACKS2 SACKS1 SACKS0 SADC2 ENOPA VBGEN SAVRS3 SAVRS2 SAVRS1 SAVRS0 A D Converter Register List HT66F004 A D Converter Data Regis...

Page 99: ...rdware will only choose the internal signal as an ADC input In addition if the programs select external reference voltage VREF and the internal reference voltage VBG as ADC reference voltage then the...

Page 100: ...t channel comes from AN1 010 ADC input channel comes from AN2 011 ADC input channel comes from AN3 100 ADC input channel comes from AN4 101 ADC input channel comes from AN5 110 ADC input channel comes...

Page 101: ...voltage then the hardware will only choose the internal reference voltage VBG as an ADC reference voltage input A D Operation The START bit is used to start and reset the A D converter When the microc...

Page 102: ...ould be properly configured to disable other pin functions When VREF or VBG is selected by ADC input or ADC reference voltage the OPA needs to be enabled by setting ENOPA 1 Reference SAVRS 3 0 Descrip...

Page 103: ...D conversion rate A D clock period 16 However there is a usage limitation on the next A D conversion after the current conversion is complete When the current A D conversion is complete the converted...

Page 104: ...S 3 0 Note 1 If select VREF as reference voltage PAS3 PAS2 1 0 for HT66F002 HT66F004 2 If select VREF as reference voltage PAS2 PAS1 1 0 for HT66F003 Step 6 Select ADC output data format by ADRFS Step...

Page 105: ...sumption A D Transfer Function As the devices contain a 12 bit A D converter its full scale converted digitised value is equal to FFFH Since the full scale analog input value is equal to the VDD or VR...

Page 106: ...sable ADC interrupt mov a 0BH mov SADC1 a select fSYS 8 as A D clock and switch off the bandgap reference voltage set ENADC mov a 03h setup PASR to configure pin AN0 mov PASR a mov a 20h mov SADC0 a e...

Page 107: ...it to initiate conversion set START reset A D clr START start A D clr ADF clear ADC interrupt request flag set ADE enable ADC interrupt set EMI enable global interrupt ADC interrupt service routine AD...

Page 108: ...own in the accompanying table The number of registers depends upon the device chosen but fall into three categories The first is the INTC0 INTC1 registers which setup the primary interrupts the second...

Page 109: ...STMP0F STMA0E STMP0E HT66F003 Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 INTEG INT0S1 INT0S0 INTC0 TB1F TB0F INTF TB1E TB0E INTE EMI INTC1 MF1F ADF DEF MF0F MF1E ADE DEE MF0E MFI0 STMA0F STMP0F STMA...

Page 110: ...terrupt 10 Falling Edge Interrupt 11 Dual Edge Interrupt INTC0 Register HT66F002 HT66F0025 T66F003 Bit 7 6 5 4 3 2 1 0 Name TB1F TB0F INTF TB1E TB0E INTE EMI R W R W R W R W R W R W R W R W POR 0 0 0...

Page 111: ...Time Base 0 Interrupt Control 0 Disable 1 Enable Bit 1 INT0E INT0 Interrupt Control 0 Disable 1 Enable Bit 0 EMI Global Interrupt Control 0 Disable 1 Enable INTC1 Register HT66F002 HT66F0025 Bit 7 6 5...

Page 112: ...r Interrupt Control 0 Disable 1 Enable Bit 1 DEE Data EEPROM Interrupt Control 0 Disable 1 Enable Bit 0 MF0E Multi function 0 Interrupt Control 0 Disable 1 Enable INTC1 Register HT66F004 Bit 7 6 5 4 3...

Page 113: ...le MFI0 Register HT66F004 Bit 7 6 5 4 3 2 1 0 Name PTMA1F PTMP1F PTMA0F PTMP0F PTMA1E PTMP1E PTMA0E PTMP0E R W R W R W R W R W R W R W R W R W POR 0 0 0 0 0 0 0 0 Bit 7 PTMA1F TM1 Comparator A match i...

Page 114: ...o will disable all interrupts When an interrupt is generated the Program Counter which stores the address of the next instruction to be executed will be transferred onto the stack The Program Counter...

Page 115: ...Interrupt Name Request Flags Enable Bits Master Enable Vector EMI auto disabled in ISR Priority High Low M Funct 1 MF1F MF1E Interrupts contained within Multi Function Interrupts xxE Enable Bits xxF R...

Page 116: ...tion interrupts Unlike the other independent interrupts these interrupts have no independent source but rather are formed from other existing interrupt sources namely the TM Interrupts A Multi functio...

Page 117: ...her interrupts The purpose of the Time Base Interrupt is to provide an interrupt signal at fixed time periods Their clock sources originate from the internal clock source fTB This fTB input clock pass...

Page 118: ...cleared they have to be cleared by the application program Interrupt Wake up Function Each of the interrupt functions has the capability of waking up the microcontroller when in the SLEEP or IDLE Mod...

Page 119: ...llow further interrupts The RET instruction however only executes a return to the main program leaving the EMI bit in its present zero state and therefore disabling the execution of further interrupts...

Page 120: ...W R W R W R W R W R W R W R W POR 0 0 0 0 0 0 0 Bit 7 Unimplemented read as 0 Bit 6 5 ISEL1 ISEL0 Select resistor for R type LCD bias current VDD 5V 00 2 100k 1 2 Bias IBIAS 25 A 01 2 50 k 1 2 Bias IB...

Page 121: ...3 PA0 PA7 Reset Circuit HT66F002 HT66F0025 VDD VDD RES 10k 100k 0 01 F 1N4148 VSS 0 1 F 1 F 300 0 1 F AN0 AN3 PA0 PA7 Reset Circuit HT66F003 VDD VDD RES 10k 100k 0 01 F 1N4148 VSS 0 1 F 1 F 300 0 1 F...

Page 122: ...o take one more cycle to implement As instructions which change the contents of the PCL will imply a direct jump to that new address one more cycle will be required Examples of such instructions would...

Page 123: ...ful set of branch instructions are the conditional branches Here a decision is first made regarding the condition of a certain data memory or individual bits Depending upon the conditions the program...

Page 124: ...n Data Memory 1Note Z C AC OV DAA m Decimal adjust ACC for Addition with result in Data Memory 1Note C Logic Operation AND A m Logical AND Data Memory to ACC 1 Z OR A m Logical OR Data Memory to ACC 1...

Page 125: ...turn from subroutine and load immediate data to ACC 2 None RETI Return from interrupt 2 None Table Read TABRD m Read table specific page to TBLH and Data Memory 2Note None TABRDC m Read table current...

Page 126: ...of the Accumulator and the specified immediate data are added The result is stored in the Accumulator Operation ACC ACC x Affected flag s OV Z AC C ADDM A m Add ACC to Data Memory Description The con...

Page 127: ...scription The TO PDF flags and the WDT are all cleared Operation WDT cleared TO 0 PDF 0 Affected flag s TO PDF CLR WDT1 Pre clear Watchdog Timer Description The TO PDF flags and the WDT are all cleare...

Page 128: ...be affected by this instruction which indicates that if the original BCD sum is greater than 100 it allows multiple precision decimal addition Operation m ACC 00H or m ACC 06H or m ACC 60H or m ACC 6...

Page 129: ...emory Operation m ACC Affected flag s None NOP No operation Description No operation is performed Execution continues with the next instruction Operation No operation Affected flag s None OR A m Logic...

Page 130: ...RLA m Rotate Data Memory left with result in ACC Description The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0 The rotated result is stored in the Accum...

Page 131: ...cted flag s C SBC A m Subtract Data Memory from ACC with Carry Description The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator The result...

Page 132: ...sult is not 0 the program proceeds with the following instruction Operation m m 1 Skip if m 0 Affected flag s None SIZA m Skip if increment Data Memory is zero with result in ACC Description The conte...

Page 133: ...ed Data Memory are interchanged The result is stored in the Accumulator The contents of the Data Memory remain unchanged Operation ACC 3 ACC 0 m 7 m 4 ACC 7 ACC 4 m 3 m 0 Affected flag s None SZ m Ski...

Page 134: ...e to TBLH and Data Memory Description The low byte of the program code last page addressed by the table pointer TBLP is moved to the specified Data Memory and the high byte moved to TBLH Operation m p...

Page 135: ...ated at regular intervals users are reminded to consult the Holtek website for the latest version of the Package Carton Information Additional supplementary information with regard to packaging is lis...

Page 136: ...0mil Outline Dimensions Symbol Dimensions in inch Min Nom Max A 0 236 BSC B 0 154 BSC C 0 012 0 020 C 0 193 BSC D 0 069 E 0 050 BSC F 0 004 0 010 G 0 016 0 050 H 0 004 0 010 0 8 Symbol Dimensions in m...

Page 137: ...0mil Outline Dimensions Symbol Dimensions in inch Min Nom Max A 0 236 BSC B 0 154 BSC C 0 012 0 018 C 0 193 BSC D 0 069 E 0 039 BSC F 0 004 0 010 G 0 016 0 050 H 0 004 0 010 0 8 Symbol Dimensions in m...

Page 138: ...ch Min Nom Max A 0 043 A1 0 000 0 006 A2 0 030 0 033 0 037 B 0 007 0 013 C 0 003 0 009 D 0 118 BSC E 0 193 BSC E1 0 118 BSC e 0 020 BSC L 0 016 0 024 0 031 L1 0 037 BSC y 0 004 0 8 Symbol Dimensions i...

Page 139: ...150mil Outline Dimensions Symbol Dimensions in inch Min Nom Max A 0 236 BSC B 0 154 BSC C 0 012 0 020 C 0 390 BSC D 0 069 E 0 050 BSC F 0 004 0 010 G 0 016 0 050 H 0 004 0 010 0 8 Symbol Dimensions i...

Page 140: ...ages See Fig 1 Symbol Dimensions in inch Min Nom Max A 0 980 1 030 1 060 B 0 240 0 250 0 280 C 0 115 0 130 0 195 D 0 115 0 130 0 150 E 0 014 0 018 0 022 F 0 045 0 060 0 070 G 0 1BSC H 0 300 0 310 0 32...

Page 141: ...Nom Max A 0 945 0 965 0 985 B 0 275 0 285 0 295 C 0 120 0 135 0 150 D 0 110 0 130 0 150 E 0 014 0 018 0 022 F 0 045 0 050 0 060 G 0 1BSC H 0 300 0 310 0 325 I 0 430 Symbol Dimensions in mm Min Nom Ma...

Page 142: ...il Outline Dimensions Symbol Dimensions in inch Min Nom Max A 0 406 BSC B 0 406 BSC C 0 012 0 020 C 0 504 BSC D 0 104 E 0 050 BSC F 0 004 0 012 G 0 016 0 050 H 0 008 0 013 0 8 Symbol Dimensions in mm...

Page 143: ...50mil Outline Dimensions Symbol Dimensions in inch Min Nom Max A 0 236 BSC B 0 155 BSC C 0 008 0 012 C 0 341 BSC D 0 069 E 0 025 BSC F 0 004 0 0098 G 0 016 0 05 H 0 004 0 01 0 8 Symbol Dimensions in m...

Page 144: ...ed herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification nor recommends the use of...

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