Rev. 1.71
54
April 11, 2017
Rev. 1.71
55
April 11, 2017
HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM
HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM
The different kinds of resets all affect the internal registers of the microcontroller in different ways.
To ensure reliable continuation of normal program execution after a reset occurs, it is important to
know what condition the microcontroller is in after a particular reset occurs. The following table
describes how each type of reset affects each of the microcontroller internal registers. Note that where
more than one package type exists the table will reflect the situation for the larger package type.
Register
HT66F002
HT66F0025
HT66F003
HT66F004
Reset
(Power On)
WDT Time-out
(Normal
Operation)
RES Reset
(Normal
Operation)
RES Reset
(HALT)
WDT Time-out
(HALT)*
Program
Counter
●
●
●
●
0 0 0 H
0 0 0 H
0 0 0 H
0 0 0 H
0 0 0 H
MP0
●
●
●
●
1 x x x x x x x
1 x x x x x x x
1 x x x x x x x
1 x x x x x x x
1 u u u u u u u
MP1
●
●
●
●
1 x x x x x x x
1 x x x x x x x
1 x x x x x x x
1 x x x x x x x
1 u u u u u u u
BP
●
●
●
●
- - - - - - - 0
- - - - - - - 0
- - - - - - - 0
- - - - - - - 0
- - - - - - - u
ACC
●
●
●
●
x x x x x x x x
u u u u u u u u
u u u u u u u u
u u u u u u u u
u u u u u u u u
PCL
●
●
●
●
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
TBLP
●
●
●
●
x x x x x x x x
u u u u u u u u
u u u u u u u u
u u u u u u u u
u u u u u u u u
TBLH
●
●
●
●
- - x x x x x x
- - u u u u u u
- - u u u u u u
- - u u u u u u
- - u u u u u u
STATUS
●
●
●
●
- - 0 0 x x x x
- - 1 u u u u u
- - u u u u u u
- - 0 1 u u u u
- - 1 1 u u u u
SMOD
●
●
●
●
0 0 0 - 0 0 11
0 0 0 - 0 0 11
0 0 0 - 0 0 11
0 0 0 - 0 0 11
u u u - u u u u
INTEG
●
●
●
●
- - - - - - 0 0
- - - - - - 0 0
- - - - - - 0 0
- - - - - - 0 0
- - - - - - u u
INTC0
●
●
●
●
- 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0
- u u u u u u u
INTC1
●
●
- 0 0 0 - 0 0 0
- 0 0 0 - 0 0 0
- 0 0 0 - 0 0 0
- 0 0 0 - 0 0 0
- u u u - u u u
●
●
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
u u u u u u u u
MFI0
●
●
●
- - 0 0 - - 0 0
- - 0 0 - - 0 0
- - 0 0 - - 0 0
- - 0 0 - - 0 0
- - u u - - u u
●
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
u u u u u u u u
MFI1
●
- - 0 0 - - 0 0
- - 0 0 - - 0 0
- - 0 0 - - 0 0
- - 0 0 - - 0 0
- - u u - - u u
PA
●
●
●
●
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
u u u u u u u u
PAC
●
●
●
●
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
u u u u u u u u
PAPU
●
●
●
●
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
u u u u u u u u
PAWU
●
●
●
●
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
u u u u u u u u
IFS0
●
●
- - 0 0 - - 0 0
- - 0 0 - - 0 0
- - 0 0 - - 0 0
- - 0 0 - - 0 0
- - u u - - u u
●
0 0 0 0 0 - 0 0
0 0 0 0 0 - 0 0
0 0 0 0 0 - 0 0
0 0 0 0 0 - 0 0
u u u u u - u u
WDTC
●
●
●
0 1 0 1 0 0 11
0 1 0 1 0 0 11
0 1 0 1 0 0 11
0 1 0 1 0 0 11
u u u u u u u u
TBC
●
●
●
●
0 0 1 1 - 1 1 1
0 0 1 1 - 1 1 1
0 0 1 1 - 1 1 1
0 0 1 1 - 1 1 1
u u u u – u u u
SMOD1
●
●
●
●
0 - - - 0 x - 0
0 - - - 0 x - 0
0 - - - 0 x - 0
0 - - - 0 x - 0
u - - - u u - u
SCOMC
●
- 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0
- u u u u u u u
EEA
●
●
●
●
- - - 0 0 0 0 0
- - - 0 0 0 0 0
- - - 0 0 0 0 0
- - - 0 0 0 0 0
- - - u u u u u
EED
●
●
●
●
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
u u u u u u u u
SADOL
(ADRFS=0)
●
●
●
●
x x x x - - - -
x x x x - - - -
x x x x - - - -
x x x x - - - -
u u u u - - - -
SADOL
(ADRFS=1)
●
●
●
●
x x x x x x x x
x x x x x x x x
x x x x x x x x
x x x x x x x x
u u u u u u u u
SADOH
(ADRFS=0)
●
●
●
●
x x x x x x x x
x x x x x x x x
x x x x x x x x
x x x x x x x x
u u u u u u u u
SADOH
(ADRFS=1)
●
●
●
●
- - - - x x x x
- - - - x x x x
- - - - x x x x
- - - - x x x x
- - - - u u u u