Rev. 1.71
90
April 11, 2017
Rev. 1.71
91
April 11, 2017
HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM
HT66F002/HT66F0025/HT66F003/HT66F004
Cost-Effective A/D Flash MCU with EEPROM
Timer/Counter Mode
To select this mode, bits PTnM1 and PTnM0 in the PTMnC1 register should all be set to 11
respectively. The Timer/Counter Mode operates in an identical way to the Compare Match Output
Mode generating the same interrupt flags. The exception is that in the Timer/Counter Mode the
TM output pin is not used. Therefore the above description and Timing Diagrams for the Compare
Match Output Mode can be used to understand its function. As the TM output pin is not used in this
mode, the pin can be used as a normal I/O pin or other pin-shared function.
PWM Output Mode
To select this mode, bits PTnM1 and PTnM0 in the PTMnC1 register should be set to 10 respectively
and also the PTnIO1 and PTnIO0 bits should be set to 10 respectively. The PWM function within
the TM is useful for applications which require functions such as motor control, heating control,
illumination control etc. By providing a signal of fixed frequency but of varying duty cycle on the
TM output pin, a square wave AC waveform can be generated with varying equivalent DC RMS
values.
As both the period and duty cycle of the PWM waveform can be controlled, the choice of generated
waveform is extremely flexible. In the PWM mode, the PTnCCLR bit has no effect as the PWM
period. Both of the CCRP and CCRA registers are used to generate the PWM waveform, one register
is used to clear the internal counter and thus control the PWM waveform frequency, while the other
one is used to control the duty cycle. The PWM waveform frequency and duty cycle can therefore
be controlled by the values in the CCRA and CCRP registers.
An interrupt flag, one for each of the CCRA and CCRP, will be generated when a compare match
occurs from either Comparator A or Comparator P. The PTnOC bit in the PTMnC1 register is used to
select the required polarity of the PWM waveform while the two PTnIO1 and PTnIO0 bits are used
to enable the PWM output or to force the TM output pin to a fixed high or low level. The PTnPOL
bit is used to reverse the polarity of the PWM output waveform.
•
10-bit PWM Mode, Edge-aligned Mode
CCRP
CCRP = 0~1024
Period
CCRP=0 : period= 1024 clocks
CCRP=1~1023: period=1~1023 clocks
Duty
CCRA
If f
SYS
= 16MHz, PTM clock source select f
SYS
/4, CCRP = 512 and CCRA = 128,
The
P
TM PWM output frequency = (f
SYS
/4)/512 = f
SYS
/2048 = 7.8125kHz, duty = 128/512 = 25%
If the Duty value defined by the CCRA register is equal to or greater than the Period value, then the
PWM output duty is 100%.
