manualshive.com logo in svg

Hitachi H8/3935, Hardware Manual

Share
Download
Hitachi H8/3935 Hardware Manual Download Page 348

336

12.2.3

Host-to-Decoder Packet Map

The upper 8 bits of a packet comprise the packet ID. The following table describes the packet ID’s
for all of the packets that can be sent to the FLEX decoder from the host.

Table 12-1   Host-to-Decoder Packet ID Map

Packet ID
(Hexadecimal)

Packet Type

00

Checksum

01

Configuration

02

Control

03

All Frame Mode

   

04

   

    

Operator Message Address Enables   

   

05

   

    

Roaming Control Packet   

   

06

   

Timing Control Packet   

   

07

    - 0E

Reserved (Host should never send)

0F

Receiver Line Control

10

Receiver Control Configuration (Off Setting)

11

Receiver Control Configuration (Warm Up 1 Setting)

12

Receiver Control Configuration (Warm Up 2 Setting)

13

Receiver Control Configuration (Warm Up 3 Setting)

14

Receiver Control Configuration (Warm Up 4 Setting)

15

Receiver Control Configuration (Warm Up 5 Setting)

16

Receiver Control Configuration (3200sps Sync Setting)

17

Receiver Control Configuration (1600sps Sync Setting)

18

Receiver Control Configuration (3200sps Data Setting)

19

Receiver Control Configuration (1600sps Data Setting)

1A

Receiver Control Configuration (Shut Down 1 Setting)

1B

Receiver Control Configuration (Shut Down 2 Setting)

1C - 1F

Special (Ignored by FLEX decoder)

20

Frame Assignment (Frames 112 through 127)

21

Frame Assignment (Frames 96 through 111)

22

Frame Assignment (Frames 80 through 95)

23

Frame Assignment (Frames 64 through 79)

24

Frame Assignment (Frames 48 through 63)

           

Summary of Contents for H8/3935

Page 1: ......

Page 2: ......

Page 3: ...nterface and an A D converter as on chip peripheral functions necessary for system configuration The configuration of these series makes them ideal for use as embedded microcomputers in pagers using the FLEX decoder system The H8 3937 Series supports non roaming while the H8 3937R Series supports roaming This manual describes the hardware of the H8 3937 Series and H8 3937R Series For details on H8...

Page 4: ......

Page 5: ... 3 2 Memory Data Formats 19 2 4 Addressing Modes 20 2 4 1 Addressing Modes 20 2 4 2 Effective Address Calculation 22 2 5 Instruction Set 26 2 5 1 Data Transfer Instructions 28 2 5 2 Arithmetic Operations 30 2 5 3 Logic Operations 31 2 5 4 Shift Operations 31 2 5 5 Bit Manipulations 33 2 5 6 Branching Instructions 37 2 5 7 System Control Instructions 39 2 5 8 Block Data Transfer Instruction 40 2 6 ...

Page 6: ...tes 80 3 4 1 Notes on Stack Area Use 80 3 4 2 Notes on Rewriting Port Mode Registers 81 3 4 3 Notes on Interrupt Request Flag Clearing Methods 83 Section 4 Clock Pulse Generators 85 4 1 Overview 85 4 1 1 Block Diagram 85 4 1 2 System Clock and Subclock 85 4 2 System Clock Generator 86 4 3 Subclock Generator 89 4 4 Prescalers 91 4 5 Note on Oscillators 92 4 5 1 Definition of Oscillation Settling St...

Page 7: ... Clearing Subactive Mode 111 5 6 3 Operating Frequency in Subactive Mode 111 5 7 Active Medium Speed Mode 112 5 7 1 Transition to Active Medium Speed Mode 112 5 7 2 Clearing Active Medium Speed Mode 112 5 7 3 Operating Frequency in Active Medium Speed Mode 112 5 8 Direct Transfer 113 5 8 1 Overview of Direct Transfer 113 5 8 2 Direct Transition Times 114 5 8 3 Notes on External Input Signal Change...

Page 8: ... 148 8 4 3 Pin Functions 151 8 4 4 Pin States 153 8 4 5 MOS Input Pull Up 153 8 5 Port 4 154 8 5 1 Overview 154 8 5 2 Register Configuration and Description 154 8 5 3 Pin Functions 156 8 5 4 Pin States 157 8 6 Port 5 158 8 6 1 Overview 158 8 6 2 Register Configuration and Description 158 8 6 3 Pin Functions 160 8 6 4 Pin States 161 8 6 5 MOS Input Pull Up 161 8 7 Port 6 162 8 7 1 Overview 162 8 7 ...

Page 9: ...sion Function 176 8 13 1 Overview 176 8 13 2 Register Configuration and Descriptions 176 8 13 3 Note on Modification of Serial Port Control Register 178 8 14 Application Note 178 8 14 1 The Management of the Un Use Terminal 178 Section 9 Timers 179 9 1 Overview 179 9 2 Timer A 180 9 2 1 Overview 180 9 2 2 Register Descriptions 182 9 2 3 Timer Operation 186 9 2 4 Timer A Operation States 187 9 2 5 ...

Page 10: ... 250 10 2 4 Interrupt Source 252 10 2 5 Application Note 253 10 3 SCI3 254 10 3 1 Overview 254 10 3 2 Register Descriptions 258 10 3 3 Operation 280 10 3 4 Interrupts 308 10 3 5 Application Notes 309 Section 11 A D Converter 315 11 1 Overview 315 11 1 1 Features 315 11 1 2 Block Diagram 316 11 1 3 Pin Configuration 317 11 1 4 Register Configuration 317 11 2 Register Descriptions 318 11 2 1 A D Res...

Page 11: ...nable Packet 347 12 3 6 Roaming Control Packet 347 12 3 7 Timing Control Packet 350 12 3 8 Receiver Line Control Packet 351 12 3 9 Receiver Control Configuration Packets 351 12 3 10 Frame Assignment Packets 355 12 3 11 User Address Enable Packet 356 12 3 12 User Address Assignment Packets 357 12 4 Decoder to Host Packet Descriptions 358 12 4 1 Block Information Word Packet 359 12 4 2 Address Packe...

Page 12: ...uctions 407 A 2 Operation Code Map 415 A 3 Number of Execution States 417 Appendix B Internal I O Registers 423 B 1 Addresses 423 B 2 Functions 426 Appendix C I O Port Block Diagrams 478 C 1 Block Diagrams of Port 1 478 C 2 Block Diagrams of Port 2 Chip Internal I O Port 482 C 3 Block Diagrams of Port 3 486 C 4 Block Diagrams of Port 4 493 C 5 Block Diagram of Port 5 497 C 6 Block Diagram of Port ...

Page 13: ...e as embedded microcomputers in pagers using the FLEX system which require low power consumption Models in the H8 3937 Series and H8 3937R Series are the H8 3935 and H8 3935R with on chip 40 kbyte ROM and 2 kbyte RAM the H8 3936 and H8 3936R with on chip 48 kbyte ROM and 2 kbyte RAM and the H8 3937 and H8 3937R with on chip 60 kbyte ROM and 2 kbyte RAM The H8 3937 and H8 3937R Series are also avai...

Page 14: ...egisters MOV instruction for data transfer between memory and registers Typical instructions Multiply 8 bits 8 bits Divide 16 bits 8 bits Bit accumulator Register indirect designation of bit position Interrupts 36 interrupt sources 12 external interrupt sources IRQ4 to IRQ1 WKP7 to WKP0 23 internal interrupt sources 1 internal IRQ0 interrupt source IRQ0 Clock pulse generators Two on chip clock pul...

Page 15: ... timers Count up timer with selection of four internal clock signals or event input from external pin Provision for toggle output by means of compare match function Timer G 8 bit timer Count up timer with selection of four internal clock signals Incorporates input capture function built in noise canceler Watchdog timer Reset signal generated by overflow of 8 bit counter Serial communication interf...

Page 16: ...M Size Byte Non roaming HD6433935X 100 pin TQFP TFP 100B 40 k 2 k HD6433935W 100 pin TQFP TFP 100G HD6433936X 100 pin TQFP TFP 100B 48 k 2 k HD6433936W 100 pin TQFP TFP 100G HD6433937X HD6473937X 100 pin TQFP TFP 100B 60 k 2 k HD6433937W HD6473937W 100 pin TQFP TFP 100G Roaming HD6433935RX 100 pin TQFP TFP 100B 40 k 2 k HD6433935RW 100 pin TQFP TFP 100G HD6433936RX 100 pin TQFP TFP 100B 48 k 2 k H...

Page 17: ... V SS V CC V CC RES TEST TEST9H H8 300L CPU ROM 60 k 48 k 40 k RAM 2 k Timer A Timer C Timer F Timer G Serial communication interface 32 Serial communication interface 31 Serial communication interface 1 WDT A D 10 bit Port 4 Internal I O port PA3 PA2 PA1 PA0 TEST20 TEST21 TEST22 TEST23 TEST24 TEST43 P87 P86 P85 P84 P83 P82 P81 P80 P77 P76 P75 P74 P73 P72 P71 P70 P67 P66 P65 P64 P63 P62 P61 P60 Po...

Page 18: ... PA2 PA3 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 S5 S4 S3 S2 S1 S0 IFIN CLKOUT TESTD DX2 DX1 TEST P80 P81 P82 P83 P84 P85 P86 P87 P90 P91 P92 P93 AVCC PB0 AN0 P67 P66 P65 P64 P63 P62 P61 P60 P57 WKP7 P56 WKP6 P55 WKP5 P54 WK...

Page 19: ...in It should be connected to the system power supply 0V Clock pins OSC1 10 Input These pins connect to a crystal or OSC2 9 Output ceramic oscillator or can be used to input an external clock See section 4 Clock Pulse Generators for a typical connection diagram DX1 85 Input These pins connect to a 76 8 kHz or DX2 84 160 kHz crystal oscillator Output See section 4 Clock Pulse Generators for a typica...

Page 20: ... event input This is an event input pin for input to the timer C counter UD 27 Input Timer C up down select This pin selects up or down counting for the timer C counter The counter operates as a down counter when this pin is high and as an up counter when low TMIF 21 Input Timer F event input This is an event input pin for input to the timer F counter TMOFL 15 Output Timer FL output This is an out...

Page 21: ...h bit by means of port control register 6 PCR6 P77 to P70 60 to 53 I O Port 7 This is an 8 bit I O port Input or output can be designated for each bit by means of port control register 7 PCR7 P87 to P80 94 to 87 I O Port 8 This is an 8 bit I O port Input or output can be designated for each bit by means of port control register 8 PCR8 P93 to P90 98 to 95 I O Port 9 This is a 4 bit I O port Input o...

Page 22: ...ut channels 7 to 0 These are analog data input channels to the A D converter ADTRG 18 Input A D converter trigger input This is the external trigger input pin to the A D converter FLEX decoder II RESET Input Decoder reset A reset is executed when this pin goes low EXTS1 71 Input Decode symbol input MSb of the symbol currently being decoded EXTS0 72 Input Decode symbol input LSb of the symbol curre...

Page 23: ...ystal oscillator SYMCLK 73 Output Symbol clock output Recovered symbol clock pin S0 81 Output Receiver control output Receiver control signal output pin when using external demodulator S1 to S7 80 to 74 Output Receiver control output Three state receiver control signal output IFIN 81 Input IF signal input Limited IF signal input pin when using internal demodulator ...

Page 24: ...12 ...

Page 25: ...de instructions Powerful bit manipulation instructions Eight addressing modes Register direct Register indirect Register indirect with displacement Register indirect with post increment or pre decrement Absolute address Immediate Program counter relative Memory indirect 64 kbyte address space High speed operation All frequently used instructions are executed in two to four states High speed arithm...

Page 26: ...e H8 300L CPU There are two groups of registers the general registers and control registers 7 0 7 0 15 0 PC R0H R1H R2H R3H R4H R5H R6H R7H R0L R1L R2L R3L R4L R5L R6L R7L SP SP Stack pointer PC Program counter CCR Condition code register Carry flag Overflow flag Zero flag Negative flag Half carry flag Interrupt mask bit User bit User bit CCR I U H U N Z V C General registers Rn Control registers ...

Page 27: ...ddress side H 0000 Upper address side H FFFF Unused area Stack area SP R7 Figure 2 2 Stack Pointer 2 2 2 Control Registers The CPU control registers include a 16 bit program counter PC and an 8 bit condition code register CCR Program Counter PC This 16 bit register indicates the address of the next instruction the CPU will execute All instructions are fetched 16 bits 1 word at a time so the least ...

Page 28: ...Set to 1 to indicate a zero result and cleared to 0 to indicate a non zero result Bit 1 Overflow Flag V Set to 1 when an arithmetic overflow occurs and cleared to 0 at other times Bit 0 Carry Flag C Set to 1 when a carry occurs and cleared to 0 otherwise Used by Add instructions to indicate a carry Subtract instructions to indicate a borrow Shift and rotate instructions to store the value shifted ...

Page 29: ... in a byte operand n 0 1 2 7 All arithmetic and logic instructions except ADDS and SUBS can operate on byte data The MOV W ADD W SUB W CMP W ADDS SUBS MULXU 8 bits 8 bits and DIVXU 16 bits 8 bits instructions operate on word data The DAA and DAS instructions perform decimal arithmetic adjustments on byte data in packed BCD form Each nibble of the byte is treated as a decimal digit ...

Page 30: ... 1 0 don t care 7 0 1 bit data RnL MSB LSB don t care 7 0 Byte data RnH Byte data RnL Word data Rn 4 bit BCD data RnH 4 bit BCD data RnL Notation RnH RnL MSB LSB Upper byte of general register Lower byte of general register Most significant bit Least significant bit MSB LSB don t care 7 0 MSB LSB 15 0 Upper digit Lower digit don t care 7 0 3 4 don t care Upper digit Lower digit 7 0 3 4 Figure 2 3 ...

Page 31: ...a Format 7 6 5 4 3 2 1 0 Address Data Type 7 0 Address n MSB LSB MSB LSB Upper 8 bits Lower 8 bits MSB LSB CCR CCR MSB LSB MSB LSB Address n Even address Odd address Even address Odd address Even address Odd address 1 bit data Byte data Word data Byte data CCR on stack Word data on stack CCR Condition code register Note Ignored on return Figure 2 4 Memory Data Formats When the stack is accessed us...

Page 32: ... register containing the operand Only the MOV W ADD W SUB W CMP W ADDS SUBS MULXU 8 bits 8 bits and DIVXU 16 bits 8 bits instructions have 16 bit operands 2 Register Indirect Rn The register field of the instruction specifies a 16 bit general register containing the address of the operand in memory 3 Register Indirect with Displacement d 16 Rn The instruction has a second word bytes 3 and 4 contai...

Page 33: ...F00 to H FFFF 65280 to 65535 6 Immediate xx 8 or xx 16 The instruction contains an 8 bit operand xx 8 in its second byte or a 16 bit operand xx 16 in its third and fourth bytes Only MOV W instructions can contain 16 bit immediate values The ADDS and SUBS instructions implicitly contain the value 1 or 2 as immediate data Some bit manipulation instructions contain 3 bit immediate data in the second ...

Page 34: ...each of the addressing modes Arithmetic and logic instructions use register direct addressing 1 The ADD B ADDX SUBX CMP B AND OR and XOR instructions can also use immediate addressing 6 Data transfer instructions can use all addressing modes except program counter relative 7 and memory indirect 8 Bit manipulation instructions can use register direct 1 register indirect 2 or 8 bit absolute addressi...

Page 35: ... 0 15 Register indirect with displacement d 16 Rn op rm rn 8 7 3 4 0 15 op rm 7 6 3 4 0 15 disp op rm 7 6 3 4 0 15 Register indirect with post increment Rn op rm 7 6 3 4 0 15 Register indirect with pre decrement Rn 2 3 4 Incremented or decremented by 1 if operand is byte size and by 2 if word size 0 15 disp 0 15 0 15 0 15 1 or 2 0 15 0 15 1 or 2 0 15 rm 3 0 rn 3 0 Contents 16 bits of register indi...

Page 36: ...d Effective Address EA 5 Absolute address aa 8 Operand is 1 or 2 byte immediate data aa 16 op 8 7 0 15 op 0 15 IMM op disp 7 0 15 Program counter relative d 8 PC 6 7 0 15 PC contents 0 15 0 15 abs H FF 8 7 0 15 0 15 abs op xx 16 op 8 7 0 15 IMM Immediate xx 8 8 Sign extension disp ...

Page 37: ...fective Address Calculation Method Effective Address EA 8 Memory indirect aa 8 op 8 7 0 15 Memory contents 16 bits 0 15 abs H 00 8 7 0 15 Notation rm rn op disp IMM abs Register field Operation field Displacement Immediate data Absolute address abs ...

Page 38: ...Bit manipulation BSET BCLR BNOT BTST BAND BIAND BOR BIOR BXOR BIXOR BLD BILD BST BIST 14 Branch Bcc 2 JMP BSR JSR RTS 5 System control RTE SLEEP LDC STC ANDC ORC XORC NOP 8 Block data transfer EEPMOV 1 Total 55 Notes 1 PUSH Rn is equivalent to MOV W Rn SP POP Rn is equivalent to MOV W SP Rn The same applies to the machine language 2 Bcc is a conditional branch instruction in which cc represents a ...

Page 39: ...e flag of CCR Z Z zero flag of CCR V V overflow flag of CCR C C carry flag of CCR PC Program counter SP Stack pointer IMM Immediate data disp Displacement Addition Subtraction Multiplication Division AND logical OR logical Exclusive OR logical Move Logical negation logical complement 3 3 bit length 8 8 bit length 16 16 bit length Contents of operand indicated by effective address ...

Page 40: ...egister The Rn Rn d 16 Rn aa 16 xx 16 Rn and Rn addressing modes are available for word data The aa 8 addressing mode is available for byte data only The R7 and R7 modes require word operands Do not specify byte size for these two modes POP W SP Rn Pops a 16 bit general register from the stack Equivalent to MOV W SP Rn PUSH W Rn SP Pushes a 16 bit general register onto the stack Equivalent to MOV ...

Page 41: ... or Rn Rm 15 0 8 7 op rn abs aa 8 Rn 15 0 8 7 op rn aa 16 Rn abs 15 0 8 7 op rn IMM xx 8 Rn 15 0 8 7 op rn xx 16 Rn IMM 15 0 8 7 op rn PUSH POP Notation op rm rn disp abs IMM Operation field Register field Displacement Absolute address Immediate data SP Rn or Rn SP 1 1 1 Figure 2 5 Data Transfer Instruction Codes ...

Page 42: ...ts or decrements a general register by 1 ADDS SUBS W Rd 1 Rd Rd 2 Rd Adds or subtracts 1 or 2 to or from a general register DAA DAS B Rd decimal adjust Rd Decimal adjusts adjusts to 4 bit BCD an addition or subtraction result in a general register by referring to the CCR MULXU B Rd Rs Rd Performs 8 bit 8 bit unsigned multiplication on data in two general registers providing a 16 bit result DIVXU B...

Page 43: ...on a general register and another general register or immediate data NOT B Rd Rd Obtains the one s complement logical complement of general register contents Notes Size Operand size B Byte 2 5 4 Shift Operations Table 2 7 describes the eight shift instructions Table 2 7 Shift Instructions Instruction Size Function SHAL SHAR B Rd shift Rd Performs an arithmetic shift operation on general register c...

Page 44: ...n IMM Operation field Register field Immediate data 15 0 8 7 op rn ADDS SUBS INC DEC DAA DAS NEG NOT 15 0 8 7 op rn MULXU DIVXU rm 15 0 8 7 rn IMM ADD ADDX SUBX CMP XX 8 op 15 0 8 7 op rn AND OR XOR Rm rm 15 0 8 7 rn IMM AND OR XOR xx 8 op 15 0 8 7 rn SHAL SHAR SHLL SHLR ROTL ROTR ROTXL ROTXR op Figure 2 6 Arithmetic Logic and Shift Instruction Codes ...

Page 45: ...f a general register BTST B bit No of EAd Z Tests a specified bit in a general register or memory and sets or clears the Z flag accordingly The bit number is specified by 3 bit immediate data or the lower three bits of a general register BAND B C bit No of EAd C ANDs the C flag with a specified bit in a general register or memory and stores the result in the C flag BIAND B C bit No of EAd C ANDs t...

Page 46: ...fied bit in a general register or memory to the C flag BILD B bit No of EAd C Copies the inverse of a specified bit in a general register or memory to the C flag The bit number is specified by 3 bit immediate data BST B C bit No of EAd Copies the C flag to a specified bit in a general register or memory BIST B C bit No of EAd Copies the inverse of the C flag to a specified bit in a general registe...

Page 47: ... 8 7 op 0 Operand Bit No register indirect Rn register direct Rm rn 0 0 0 0 0 0 0 rm op 15 0 8 7 op Operand Bit No absolute aa 8 immediate xx 3 abs 0 0 0 0 IMM op op 15 0 8 7 op Operand Bit No absolute aa 8 register direct Rm abs 0 0 0 0 rm op 15 0 8 7 op IMM rn Operand Bit No register direct Rn immediate xx 3 BAND BOR BXOR BLD BST 15 0 8 7 op 0 Operand Bit No register indirect Rn immediate xx 3 r...

Page 48: ... op IMM rn Operand Bit No register direct Rn immediate xx 3 BIAND BIOR BIXOR BILD BIST 15 0 8 7 op 0 Operand Bit No register indirect Rn immediate xx 3 rn 0 0 0 0 0 0 0 IMM op 15 0 8 7 op Operand Bit No absolute aa 8 immediate xx 3 abs 0 0 0 0 IMM op Figure 2 7 Bit Manipulation Instruction Codes cont ...

Page 49: ...ays true Always BRN BF Never false Never BHI High C Z 0 BLS Low or same C Z 1 BCC BHS Carry clear high or same C 0 BCS BLO Carry set low C 1 BNE Not equal Z 0 BEQ Equal Z 1 BVC Overflow clear V 0 BVS Overflow set V 1 BPL Plus N 0 BMI Minus N 1 BGE Greater or equal N V 0 BLT Less than N V 1 BGT Greater than Z N V 0 BLE Less or equal Z N V 1 JMP Branches unconditionally to a specified address BSR Br...

Page 50: ...cement Absolute address 15 0 8 7 op cc disp Bcc 15 0 8 7 op rm 0 JMP Rm 0 0 0 15 0 8 7 op JMP aa 16 abs 15 0 8 7 op abs JMP aa 8 15 0 8 7 op disp BSR 15 0 8 7 op rm 0 JSR Rm 0 0 0 15 0 8 7 op JSR aa 16 abs 15 0 8 7 op abs JSR aa 8 15 0 8 7 op RTS Figure 2 8 Branching Instruction Codes ...

Page 51: ...n Modes for details LDC B Rs CCR IMM CCR Moves immediate data or general register contents to the condition code register STC B CCR Rd Copies the condition code register to a specified general register ANDC B CCR IMM CCR Logically ANDs the condition code register with immediate data ORC B CCR IMM CCR Logically ORs the condition code register with immediate data XORC B CCR IMM CCR Logically exclusi...

Page 52: ...s object code format Table 2 11 Block Data Transfer Instruction Instruction Size Function EEPMOV If R4L 0 then repeat R5 R6 R4L 1 R4L until R4L 0 else next Block transfer instruction Transfers the number of data bytes specified by R4L from locations starting at the address indicated by R5 to locations starting at the address indicated by R6 After the transfer the next instruction is executed Certa...

Page 53: ...41 Notation op Operation field 15 0 8 7 op op Figure 2 10 Block Data Transfer Instruction Code ...

Page 54: ...fers depending on whether access is to on chip memory or to on chip peripheral modules 2 6 1 Access to On Chip Memory RAM ROM Access to on chip memory takes place in two states The data bus width is 16 bits allowing access in byte or word size Figure 2 11 shows the on chip memory access cycle T1 state Bus cycle T2 state Internal address bus Internal read signal Internal data bus read access Intern...

Page 55: ... data two instructions must be used Figures 2 12 and 2 13 show the on chip peripheral module access cycle Two state access to on chip peripheral modules T1 state Bus cycle T2 state ø or ø Internal address bus Internal read signal Internal data bus read access Internal write signal Read data Address Write data Internal data bus write access SUB Figure 2 12 On Chip Peripheral Module Access Cycle 2 S...

Page 56: ...e Bus cycle Internal address bus Internal read signal Internal data bus read access Internal write signal Read data Address Internal data bus write access T2 state T3 state Write data SUB ø or ø Figure 2 13 On Chip Peripheral Module Access Cycle 3 State Access ...

Page 57: ...mode Active medium speed mode Subactive mode Sleep high speed mode Standby mode Watch mode Subsleep mode Low power modes The CPU executes successive program instructions at high speed synchronized by the system clock The CPU executes successive program instructions at reduced speed synchronized by the system clock The CPU executes successive program instructions at reduced speed synchronized by th...

Page 58: ...ck in active mode high speed and medium speed and with the subclock in subactive mode See section 5 Power Down Modes for details on these modes 2 7 3 Program Halt State In the program halt state there are five modes two sleep modes high speed and medium speed standby mode watch mode and subsleep mode See section 5 Power Down Modes for details on these modes 2 7 4 Exception Handling State The excep...

Page 59: ... H8 3936R in figure 2 16 2 and that of the H8 3937 and H8 3937R in figure 2 16 3 H 0000 H 0029 H 002A H 9FFF H F780 H FF7F H FF90 H FFFF Interrupt vector area On chip ROM 40 kbytes 40960 bytes 2048 bytes On chip RAM Internal I O registers 112 bytes Not used Not used Figure 2 16 1 H8 3935 and H8 3935R Memory Map ...

Page 60: ... H 002A H BFFF H F780 H FF7F H FF90 H FFFF Interrupt vector area On chip ROM 48 kbytes 49152 bytes 2048 bytes On chip RAM Internal I O registers 112 bytes Not used Not used Figure 2 16 2 H8 3936 and H8 3936R Memory Map ...

Page 61: ... H 002A H EDFF H F780 H FF7F H FF90 H FFFF Interrupt vector area On chip ROM 60 kbytes 60928 bytes 2048 bytes On chip RAM Internal I O registers 112 bytes Not used Not used Figure 2 16 3 H8 3937 and H8 3937R Memory Map ...

Page 62: ...rs Internal data transfer to or from on chip modules other than the ROM and RAM areas makes use of an 8 bit data width If word access is attempted to these areas the following results will occur Word access from CPU to I O register area Upper byte Will be written to I O register Lower byte Transferred data will be lost Word access from I O register to CPU Upper byte Will be written to upper part o...

Page 63: ... H FFA8 to H FFAF H 0000 H 0029 H 002A H 9FFF H F780 H FF7F H FF90 H FFFF H FF98 to H FF9F Notes The H8 3935 and H8 3935R are shown as an example The address is H BFFF in the H8 3936 and H8 3936R 48 kbyte on chip ROM and H EDFF in the H8 3937 and H8 3937R 60 kbyte on chip ROM Figure 2 17 Data Size and Number of States for Access to and from On Chip Peripheral Modules ...

Page 64: ...timer counter Figure 2 18 shows an example in which two timer registers share the same address When a bit manipulation instruction accesses the timer load register and timer counter of a reloadable timer since these two registers share the same address the following operations take place Order of Operation Operation 1 Read Timer counter data is read one byte 2 Modify The CPU modifies sets or reset...

Page 65: ...r executing BSET P37 P36 P35 P34 P33 P32 P31 P30 Input output Input Input Output Output Output Output Output Output Pin state Low level High level Low level Low level Low level Low level Low level High level PCR3 0 0 1 1 1 1 1 1 PDR3 0 1 0 0 0 0 0 1 D Explanation of how BSET operates When the BSET instruction is executed first the CPU reads port 3 Since P37 and P36 are input pins the CPU reads the...

Page 66: ...t Pin state Low level High level Low level Low level Low level Low level Low level Low level PCR3 0 0 1 1 1 1 1 1 PDR3 1 0 0 0 0 0 0 0 RAM0 1 0 0 0 0 0 0 0 B BSET instruction executed BSET 0 RAM0 The BSET instruction is executed designating the PDR3 work area RAM0 C After executing BSET MOV B MOV B RAM0 R0L R0L PDR3 The work area RAM0 value is written to PDR3 P37 P36 P35 P34 P33 P32 P31 P30 Input ...

Page 67: ...1 1 1 1 1 PDR3 1 0 0 0 0 0 0 0 B BCLR instruction executed BSET 0 PCR3 The BCLR instruction is executed designating PCR3 C After executing BCLR P37 P36 P35 P34 P33 P32 P31 P30 Input output Output Output Output Output Output Output Output Input Pin state Low level High level Low level Low level Low level Low level Low level High level PCR3 1 1 1 1 1 1 1 0 PDR3 1 0 0 0 0 0 0 0 D Explanation of how B...

Page 68: ...t Pin state Low level High level Low level Low level Low level Low level Low level Low level PCR3 0 0 1 1 1 1 1 1 PDR3 1 0 0 0 0 0 0 0 RAM0 0 0 1 1 1 1 1 1 B BCLR instruction executed BSET 0 RAM0 The BCLR instruction is executed designating the PCR3 work area RAM0 C After executing BCLR MOV B MOV B RAM0 R0L R0L PCR3 The work area RAM0 value is written to PCR3 P37 P36 P35 P34 P33 P32 P31 P30 Input ...

Page 69: ... register 8 1 PDR8 H FFDB Port data register 9 1 PDR9 H FFDC Port data register A 1 PDRA H FFDD Notes 1 Port data registers have the same addresses as input pins 2 I O port for interfacing to FLEX decoder Table 2 13 Registers with Write Only Bits Register Name Abbreviation Address Port control register 1 PCR1 H FFE4 Port control register 2 PCR2 H FFE5 Port control register 3 PCR3 H FFE6 Port contr...

Page 70: ...ytes specified by R4L from the address specified by R5 to the address specified by R6 R6 R6 R4L R5 R5 R4L When setting R4L and R6 make sure that the final destination address R6 R4L does not exceed H FFFF The value in R6 must not change from H FFFF to H 0000 during execution of the instruction H FFFF Not allowed R6 R6 R4L R5 R5 R4L ...

Page 71: ... priority exception The internal state of the CPU and the registers of the on chip peripheral modules are initialized 3 2 2 Reset Sequence As soon as the RES pin goes low all processing is stopped and the chip enters the reset state To make sure the chip is reset properly observe the following precautions At power on Hold the RES pin low until the clock pulse generator output stabilizes Resetting ...

Page 72: ...rt address 3 First instruction of program 2 3 2 1 Reset cleared Figure 3 1 Reset Sequence 3 2 3 Interrupt Immediately after Reset After a reset if an interrupt were to be accepted before the stack pointer SP R7 was initialized PC and CCR would not be pushed onto the stack correctly resulting in program runaway To prevent this immediately after reset exception handling all interrupts are masked For...

Page 73: ...he interrupt sources their priorities and their vector addresses When more than one interrupt is requested the interrupt with the highest priority is processed The interrupts have the following features Internal and external interrupts can be masked by the I bit in CCR When the I bit is set to 1 interrupt request flags can be set but the interrupts are not accepted IRQ4 to IRQ0 and WKP7 to WKP0 ca...

Page 74: ...001A to H 001B Timer FL Timer FL compare match Timer FL overflow 14 H 001C to H 001D Timer FH Timer FH compare match Timer FH overflow 15 H 001E to H 001F Timer G Timer G input capture Timer G overflow 16 H 0020 to H 0021 SCI31 SCI31 transmit end SCI31 transmit data empty SCI31 receive data full SCI31 overrrun error SCI31 framing error SCI31 parity error 17 H 0022 to H 0023 SCI32 SCI32 transmit en...

Page 75: ...rite is enabled only for writing of 0 to clear a flag 1 IRQ edge select register IEGR Bit Initial value Read Write 7 1 6 1 5 1 4 IEG4 0 R W 3 IEG3 0 R W 0 IEG0 0 R W 2 IEG2 0 R W 1 IEG1 0 R W IEGR is an 8 bit read write register used to designate whether pins IRQ4 to IRQ1 and the internal IRQ0 signal used to interface to the FLEX decoder are set to rising edge sensing or falling edge sensing Bits ...

Page 76: ... 1 Rising edge of IRQ2 pin input is detected Bit 1 IRQ1 edge select IEG1 Bit 3 selects the input sensing of the IRQ1 pin and TMIC pin Bit 1 IEG1 Description 0 Falling edge of IRQ1 and TMIC pin input is detected initial value 1 Rising edge of IRQ1 and TMIC pin input is detected Bit 0 IRQ0 edge select IEG0 Bit 0 selects the input sensing of the IRQ0 signal Bit 0 IEG0 Description 0 Falling edge of IR...

Page 77: ...interrupt requests initial value 1 Enables timer A interrupt requests Bit 6 SCI1 interrupt enable IENS1 Bit 6 enables or disables SCI1 transfer complete interrupt requests Bit 6 IENS1 Description 0 Disables SCI1 interrupt requests initial value 1 Enables SCI1 interrupt requests Note SCI1 is an internal function that performs interfacing to the FLEX decoder incorporated in the chip Bit 5 Wakeup int...

Page 78: ... W 0 IENEC 0 R W 2 IENTFL 0 R W 1 IENTC 0 R W IENR2 is an 8 bit read write register that enables or disables interrupt requests Bit 7 Direct transfer interrupt enable IENDT Bit 7 enables or disables direct transfer interrupt requests Bit 7 IENDT Description 0 Disables direct transfer interrupt requests initial value 1 Enables direct transfer interrupt requests Bit 6 A D converter interrupt enable ...

Page 79: ...errupt requests Bit 2 Timer FL interrupt enable IENTFL Bit 2 enables or disables timer FL compare match and overflow interrupt requests Bit 2 IENTFL Description 0 Disables timer FL interrupt requests initial value 1 Enables timer FL interrupt requests Bit 1 Timer C interrupt enable IENTC Bit 1 enables or disables timer C overflow and underflow interrupt requests Bit 1 IENTC Description 0 Disables ...

Page 80: ...ecessary to write 0 to clear each flag Bit 7 Timer A interrupt request flag IRRTA Bit 7 IRRTA Description 0 Clearing conditions When IRRTA 1 it is cleared by writing 0 initial value 1 Setting conditions When the timer A counter value overflows from H FF to H 00 Bit 6 SCI1 interrupt request flag IRRS1 Bit 6 IRRS1 Description 0 Clearing conditions When IRRS1 1 it is cleared by writing 0 initial valu...

Page 81: ...5 0 R W 4 IRRTG 0 R W 3 IRRTFH 0 R W 0 IRREC 0 R W 2 IRRTFL 0 R W 1 IRRTC 0 R W Note Only a write of 0 for flag clearing is possible IRR2 is an 8 bit read write register in which a corresponding flag is set to 1 when a direct transfer A D converter Timer G Timer FH Timer FC or Timer C interrupt is requested The flags are not cleared automatically when an interrupt is accepted It is necessary to wr...

Page 82: ...ial value 1 Setting conditions When the TMIG pin is designated for TMIG input and the designated signal edge is input and when TCG overflows while OVIE is set to 1 in TMG Bit 3 Timer FH interrupt request flag IRRTFH Bit 3 IRRTFH Description 0 Clearing conditions When IRRTFH 1 it is cleared by writing 0 initial value 1 Setting conditions When TCFH and OCRFH match in 8 bit timer mode or when TCF TCF...

Page 83: ... W 1 IWPF1 0 R W Note All bits can only be written with 0 for flag clearing IWPR is an 8 bit read write register containing wakeup interrupt request flags When one of pins WKP7 to WKP0 is designated for wakeup input and a rising or falling edge is input at that pin the corresponding flag in IWPR is set to 1 A flag is not cleared automatically when the corresponding interrupt is accepted Flags must...

Page 84: ...e input to pins WKP7 to WKP0 When these pins are designated as pins WKP7 to WKP0 in port mode register 5 and a rising or falling edge is input the corresponding bit in IWPR is set to 1 requesting an interrupt Recognition of wakeup interrupt requests can be disabled by clearing the IENWP bit to 0 in IENR1 These interrupts can all be masked by setting the I bit to 1 in CCR When WKP7 to WKP0 interrup...

Page 85: ...uests can be disabled by clearing the corresponding bit in IENR1 or IENR2 All these interrupts can be masked by setting the I bit to 1 in CCR When internal interrupt handling is initiated the I bit is set to 1 in CCR Vector numbers from 20 to 13 11 and 10 are assigned to these interrupts Table 3 2 shows the order of priority of interrupts from on chip peripheral modules 2 IRQ0 interrupt The IRQ0 i...

Page 86: ...ollows When an interrupt condition is met while the interrupt enable register bit is set to 1 an interrupt request signal is sent to the interrupt controller When the interrupt controller receives an interrupt request it sets the interrupt request flag From among the interrupts with interrupt request flags set to 1 the interrupt controller selects the interrupt request with the highest priority an...

Page 87: ...esponding to the accepted interrupt is generated and the interrupt handling routine located at the address indicated by the contents of the vector address is executed Notes 1 When disabling interrupts by clearing bits in an interrupt enable register or when clearing bits in an interrupt request register always do so while interrupts are masked I 1 2 If the above clear operations are performed whil...

Page 88: ...No Yes Yes No Notation PC CCR I Program counter Condition code register I bit of CCR IEN0 1 No Yes IENDT 1 No Yes IRRDT 1 No Yes Branch to interrupt handling routine IRRI0 1 No Yes IEN1 1 No Yes IRRI1 1 No Yes IEN2 1 No Yes IRRI2 1 Figure 3 3 Flow up to Interrupt Acceptance ...

Page 89: ...er PC Lower 8 bits of program counter PC Condition code register Stack pointer Notes CCR CCR PCH PCL 1 2 PC shows the address of the first instruction to be executed upon return from the interrupt handling routine Register contents must always be saved and restored by word access starting from an even numbered address Ignored on return Figure 3 4 Stack State after Completion of Interrupt Exception...

Page 90: ...is saved as PC contents becoming return address 2 4 Instruction code not executed 3 Instruction prefetch address Instruction is not executed 5 SP 2 6 SP 4 7 CCR 8 Vector address 9 Starting address of interrupt handling routine contents of vector 10 First instruction of interrupt handling routine 3 9 8 6 5 4 1 7 10 Stack access Internal processing Instruction prefetch Interrupt level decision and w...

Page 91: ...t until the first instruction of the interrupt handler is executed Table 3 4 Interrupt Wait States Item States Total Waiting time for completion of executing instruction 1 to 13 15 to 27 Saving of PC and CCR to stack 4 Vector fetch 2 Instruction fetch 4 Internal processing 4 Note Not including EEPMOV instruction ...

Page 92: ...is shown in figure 3 6 PC PC R1L PC SP SP SP H FEFC H FEFD H FEFF H L L MOV B R1L R7 SP set to H FEFF Stack accessed beyond SP BSR instruction Contents of PC are lost H Notation PCH PCL R1L SP Upper byte of program counter Lower byte of program counter General register R1L Stack pointer Figure 3 6 Operation when Odd Address is Set in SP When CCR contents are saved to the stack during interrupt exc...

Page 93: ...time the pin function is switched even if no valid interrupt is input at the pin Be sure to clear the interrupt request flag to 0 after switching pin functions Similarly when the pin function is switched by rewriting the port mode register that controls IRQ0 the interrupt request flag may be set to 1 at the time the pin function is switched even if no valid interrupt is input Therefore be sure to ...

Page 94: ...rom 0 to 1 while pin WKP7 is low IWPF6 When PMR5 bit WKP6 is changed from 0 to 1 while pin WKP6 is low IWPF5 When PMR5 bit WKP5 is changed from 0 to 1 while pin WKP5 is low IWPF4 When PMR5 bit WKP4 is changed from 0 to 1 while pin WKP4 is low IWPF3 When PMR5 bit WKP3 is changed from 0 to 1 while pin WKP3 is low IWPF2 When PMR5 bit WKP2 is changed from 0 to 1 while pin WKP2 is low IWPF1 When PMR5 b...

Page 95: ...ng and Interrupt Request Flag Clearing Procedure 3 4 3 Notes on Interrupt Request Flag Clearing Methods Either of the following methods should be used for flag clearing in the interrupt request registers IRR1 IRR2 IWPR Method 1 Clear the interrupt request flag with a BCLR instruction Recommended method Sample coding for clearing IRRI1 bit 1 of IRR1 BCLR 1 IRR1 8 Method 2 Write data to the interrup...

Page 96: ...84 ...

Page 97: ...m clock pulse generator Subclock pulse generator Prescaler S 13 bits Prescaler W 5 bits OSC OSC 1 2 DX DX 1 2 øOSC f OSC øW øW DEC f W ø 2 OSC ø 2 W ø 8 W øSUB ø 2 to ø 8192 ø 2 W ø 4 W ø 8 to ø 128 W W ø ø øOSC 128 øOSC 64 øOSC 32 øOSC 16 ø 4 W Figure 4 1 Block Diagram of Clock Pulse Generators 4 1 2 System Clock and Subclock The basic clock signals that drive the CPU and on chip peripheral modul...

Page 98: ...2 C1 C2 OSC OSC R 1 MΩ 20 f Rf Oscillation Recommended value frequency Manufacturer for C1 and C2 4 0 MHz Nihon Denpa Kogyo 12 pF 20 Figure 4 2 Typical Connection to Crystal Oscillator Figure 4 3 shows the equivalent circuit of a crystal oscillator An oscillator having the characteristics given in table 4 1 should be used CS C0 RS OSC1 OSC2 LS Figure 4 3 Equivalent Circuit of Crystal Oscillator Ta...

Page 99: ...on board design When generating clock pulses by connecting a crystal or ceramic oscillator pay careful attention to the following points Avoid running signal lines close to the oscillator circuit since the oscillator may be adversely affected by induction currents See figure 4 5 The board should be designed so that the oscillator and load capacitors are located as close as possible to pins OSC1 an...

Page 100: ...Figure 4 6 External Clock Input Example Frequency Oscillator Clock øOSC Duty cycle 45 to 55 Caution When a crystal or ceramic oscillator element is connected circuit constants will differ according to the oscillator element installation circuit stray capacitance and so forth and so should be determined in consultation with the crystal or ceramic oscillator element manufacturer ...

Page 101: ...X 1 C2 1 2 C C 12 5 pF typ 1 2 Figure 4 7 Typical Connection to 76 8 kHz 160 kHz Crystal Oscillator Subclock Figure 4 8 shows the equivalent circuit of the 76 8 kHz 160 kHz crystal oscillator CS C0 L RS fW 76 8 kHz 160 kHz S DX1 DX2 Figure 4 8 Equivalent Circuit of 76 8 kHz 160 kHz Crystal Oscillator 2 Pin connection when not using subclock When the subclock is not used connect pin DX1 to GND and ...

Page 102: ...put Connect the external clock to the DX1 pin and leave the DX2 pin open as shown in figure 4 10 External clock input Open DX1 DX2 Figure 4 10 Pin Connection when Inputting External Clock Frequency Subclock øw Duty 45 to 55 ...

Page 103: ...lock pulse generator stops Prescaler S also stops and is initialized to H 0000 The CPU cannot read or write prescaler S The output from prescaler S is shared by timer A timer C timer F timer G SCI1 SCI31 SC32 the A D converter and the watchdog timer The divider ratio can be set separately for each on chip peripheral function In active medium speed mode the clock input to prescaler S is øosc 16 øos...

Page 104: ...h mode or subactive mode to active high speed medium speed mode with an oscillator element connected to the system clock oscillator As shown in figure 4 11 as the system clock oscillator is halted in standby mode watch mode and subactive mode when a transition is made to active high speed medium speed mode the sum of the following two times oscillation settling time and standby time is required 1 ...

Page 105: ...oscillation waveform increases and the oscillation frequency stabilizes that is the oscillation settling time is required The oscillation settling time in the case of these state transitions is the same as the oscillation settling time at power on the time from the point at which the power supply voltage reaches the prescribed level until the oscillation stabilizes specified by oscillation settlin...

Page 106: ...onization with the system clock Depending on the individual crystal oscillator element characteristics the oscillation waveform amplitude may not be sufficiently large immediately after the oscillation settling standby time making the oscillation waveform susceptible to influence by fluctuations in the power supply potential In this state the oscillation waveform may be disrupted leading to an uns...

Page 107: ...ons are operable on the system clock The FLEX decoder is independently operable on the subclock Sleep medium speed mode The CPU halts On chip peripheral functions operate at a frequency of 1 64 1 32 1 16 or 1 8 of the system clock frequency The FLEX decoder is independently operable on the subclock Subsleep mode The CPU halts Timer A timer C timer G timer F the WDT SCI1 SCI31 SCI32 and the FLEX de...

Page 108: ...i J LSON MSON SSBY DTON 0 0 1 0 0 0 0 1 0 0 1 0 1 1 0 0 0 0 1 1 0 0 1 1 1 0 0 0 0 0 1 1 1 1 1 Don t care Mode Transition Conditions 2 1 Interrupt Sources Timer A Timer F Timer G interrupt IRQ0 interrupt WKP7 to WKP0 interrupt Timer A Timer C Timer F Timer G SCI1 SCI31 SCI32 interrupt IRQ4 to IRQ0 interrupts WKP7 to WKP0 interrupts All interrupts IRQ1 or IRQ0 interrupt WKP7 to WKP0 interrupts 2 3 4...

Page 109: ...heral Timer A Functions Functions Functions Functions Functions 4 Functions 4 Functions 4 Retained functions Timer C Retained Functions Retained 2 Functions Retained 2 Retained WDT Functions Retained 7 Retained Timer G Timer F Functions Retained 6 Functions Retained 2 Functions Retained 2 SCI1 Retained Functions Retained 2 Functions Retained 2 Retained SCI31 SCI32 Reset Functions Retained 3 Functi...

Page 110: ...R W 2 1 1 MA1 1 R W SYSCR1 is an 8 bit read write register for control of the power down modes Upon reset SYSCR1 is initialized to H 07 Bit 7 Software standby SSBY This bit designates transition to standby mode or watch mode Bit 7 SSBY Description 0 When a SLEEP instruction is executed in active mode a transition is made to sleep mode initial value When a SLEEP instruction is executed in subactive...

Page 111: ...time 4 096 states 1 0 1 Wait time 2 states External clock input mode 1 1 0 Wait time 8 states 1 1 1 Wait time 16 states Note When inputting the external clock set the standby timer select to the external clock input mode Also when not using the external clock do not set the standby timer select to the external clock input mode Bit 3 Low speed on flag LSON This bit chooses the system clock ø or sub...

Page 112: ...7 1 6 1 5 1 4 NESEL 1 R W 3 DTON 0 R W 0 SA0 0 R W 2 MSON 0 R W 1 SA1 0 R W SYSCR2 is an 8 bit read write register for power down mode control Bits 7 to 5 Reserved bits These bits are reserved they are always read as 1 and cannot be modified Bit 4 Noise elimination sampling frequency select NESEL This bit selects the frequency at which the watch clock signal øW generated by the subclock pulse gene...

Page 113: ... executed in active high speed mode a direct transition is made to active medium speed mode if SSBY 0 MSON 1 and LSON 0 or to subactive mode if SSBY 1 TMA3 1 and LSON 1 When a SLEEP instruction is executed in active medium speed mode a direct transition is made to active high speed mode if SSBY 0 MSON 0 and LSON 0 or to subactive mode if SSBY 1 TMA3 1 and LSON 1 When a SLEEP instruction is execute...

Page 114: ...mode clock select SA1 SA0 These bits select the CPU clock rate øW 2 øW 4 or øW 8 in subactive mode SA1 and SA0 cannot be modified in subactive mode Bit 1 SA1 Bit 0 SA0 Description 0 0 øW 8 initial value 0 1 øW 4 1 øW 2 Don t care ...

Page 115: ...ned by the MA1 and MA0 bits in SYSCR1 CPU register contents are retained The CPU may operate at a 1 2 state faster timing at transition to sleep medium speed mode 5 2 2 Clearing Sleep Mode Sleep mode is cleared by any interrupt timer A timer C timer F timer G asynchronous counter IRQ4 to IRQ0 WKP7 to WKP0 SCI1 SCI31 SCI32 or A D converter or by input at the RES pin Clearing by interrupt When an in...

Page 116: ...104 5 2 3 Clock Frequency in Sleep Medium Speed Mode Operation in sleep medium speed mode is clocked at the frequency designated by the MA1 and MA0 bits in SYSCR1 ...

Page 117: ...set in bits STS2 to STS0 in SYSCR1 has elapsed a stable system clock signal is supplied to the entire chip standby mode is cleared and interrupt exception handling starts Operation resumes in active high speed mode if MSON 0 in SYSCR2 or active medium speed mode if MSON 1 Standby mode is not cleared if the I bit of CCR is set to 1 or the particular interrupt is disabled in the interrupt enable reg...

Page 118: ...peration may start before the standby time is over 5 3 4 Standby Mode Transition and Pin States When a SLEEP instruction is executed in active high speed mode or active medium speed mode while bit SSBY is set to 1 and bit LSON is cleared to 0 in SYSCR1 and bit TMA3 is cleared to 0 in TMA a transition is made to standby mode At the same time pins go to the high impedance state except pins for which...

Page 119: ...dge capture is illustrated in figure 5 3 As shown in the case marked Capture not possible when an external input signal falls immediately after a transition to active high speed or medium speed mode or subactive mode after oscillation is started by an interrupt via a different signal the external input signal cannot be captured if the high level width at that point is less than 2 tcyc or 2 tsubcyc...

Page 120: ...ctive high speed medium speed mode or subactive mode Active high speed medium speed mode or subactive mode Standby mode or watch mode Wait for oscillation to settle tcyc tsubcyc tcyc tsubcyc tcyc tsubcyc Figure 5 3 External Input Signal Capture when Signal Changes before after Standby Mode or Watch Mode 4 Input pins to which these notes apply IRQ4 to IRQ1 WKP7 to WKP0 ADTRG TMIC TMIF TMIG ...

Page 121: ...ngs of LSON in SYSCR1 and MSON in SYSCR2 If both LSON and MSON are cleared to 0 transition is to active high speed mode if LSON 0 and MSON 1 transition is to active medium speed mode if LSON 1 transition is to subactive mode When the transition is to active mode after the time set in SYSCR1 bits STS2 to STS0 has elapsed a stable clock signal is supplied to the entire chip watch mode is cleared and...

Page 122: ... the transition 5 5 2 Clearing Subsleep Mode Subsleep mode is cleared by an interrupt timer A timer C timer F timer G SCI1 SCI32 SCI31 IRQ4 to IRQ0 WKP7 to WKP0 or by a low input at the RES pin Clearing by interrupt When an interrupt is requested subsleep mode is cleared and interrupt exception handling starts Subsleep mode is not cleared if the I bit of CCR is set to 1 or the particular interrupt...

Page 123: ...e Subactive mode is cleared by a SLEEP instruction or by a low input at the RES pin Clearing by SLEEP instruction If a SLEEP instruction is executed while the SSBY bit in SYSCR1 is set to 1 and TMA3 bit in TMA is set to 1 subactive mode is cleared and watch mode is entered If a SLEEP instruction is executed while SSBY 0 and LSON 1 in SYSCR1 and TMA3 1 in TMA subsleep mode is entered Direct transfe...

Page 124: ...dium speed mode is cleared by a SLEEP instruction Clearing by SLEEP instruction A transition to standby mode takes place if the SLEEP instruction is executed while the SSBY bit in SYSCR1 is set to 1 the LSON bit in SYSCR1 is cleared to 0 and the TMA3 bit in TMA is cleared to 0 The system goes to watch mode if the SSBY bit in SYSCR1 is set to 1 and bit TMA3 in TMA is set to 1 when a SLEEP instructi...

Page 125: ... 1 and the DTON bit in SYSCR2 is set to 1 a transition is made to active medium speed mode via medium speed sleep mode Direct transfer from active medium speed mode to active high speed mode When a SLEEP instruction is executed in active medium speed mode while the SSBY and LSON bits in SYSCR1 are cleared to 0 the MSON bit in SYSCR2 is cleared to 0 and the DTON bit in SYSCR2 is set to 1 a transiti...

Page 126: ...nstruction in active high speed mode while bits SSBY and LSON are both cleared to 0 in SYSCR1 and bits MSON and DTON are both set to 1 in SYSCR2 The time from execution of the SLEEP instruction to the end of interrupt exception handling the direct transition time is given by equation 1 below Direct transition time Number of SLEEP instruction execution states number of internal processing states tc...

Page 127: ...BY is set to 1 and bit LSON is cleared to 0 in SYSCR1 bit MSON is cleared to 0 and bit DTON is set to 1 in SYSCR2 and bit TMA3 is set to 1 in TMA The time from execution of the SLEEP instruction to the end of interrupt exception handling the direct transition time is given by equation 3 below Direct transition time Number of SLEEP instruction execution states number of internal processing states t...

Page 128: ...cted as the CPU operating clock and wait time 8192 states Notation tosc OSC clock cycle time tw Watch clock cycle time tcyc System clock ø cycle time tsubcyc Subclock øSUB cycle time 5 8 3 Notes on External Input Signal Changes before after Direct Transition 1 Direct transition from active high speed mode to subactive mode Since the mode transition is performed via watch mode see 5 3 5 Notes on Ex...

Page 129: ...is state is identical to standby mode Module standby mode is set for a particular module by setting the corresponding bit to 0 in clock stop register 1 CKSTPR1 or clock stop register 2 CKSTPR2 See table 5 5 5 9 2 Clearing Module Standby Mode Module standby mode is cleared for a particular module by setting the corresponding bit to 1 in clock stop register 1 CKSTPR1 or clock stop register 2 CKSTPR2...

Page 130: ...dby mode ADCKSTP 1 A D converter module standby mode is cleared 0 A D converter is set to module standby mode S1CKSTP 1 SCI1 module standby mode is cleared 0 SCI1 is set to module standby mode S32CKSTP 1 SCI32 module standby mode is cleared 0 SCI32 is set to module standby mode S31CKSTP 1 SCI31 module standby mode is cleared 0 SCI31 is set to module standby mode Table 5 5 Setting and Clearing Modu...

Page 131: ...t data bus allowing high speed two state access for both byte data and word data The H8 3937 and H8 3937R have a ZTAT version with 60 kbyte PROM 6 1 1 Block Diagram Figure 6 1 shows a block diagram of the on chip ROM H 9FFE H 9FFF Internal data bus upper 8 bits Internal data bus lower 8 bits Even numbered address Odd numbered address H 9FFE H 0002 H 0000 H 0000 H 0002 H 0001 H 0003 On chip ROM Fig...

Page 132: ...e Setting TEST High level P90 PB4 AN4 Low level P91 PB5 AN5 P92 PB6 AN6 High level 6 2 2 Socket Adapter Pin Arrangement and Memory Map A standard PROM programmer can be used to program the PROM A socket adapter is required for conversion to 32 pins as listed in table 6 2 Figure 6 2 shows the pin to pin wiring of the socket adapter Figure 6 3 shows a memory map Table 6 2 Socket Adapter Package Sock...

Page 133: ...60 P61 P62 P63 P64 P65 P66 P67 P87 P86 P85 P84 P83 P82 P81 P80 P70 TESTA9H P72 P73 P74 P75 P76 P14 P15 P77 P71 P13 VCC AVCC TEST DX1 P92 P11 P12 P16 PB6 VSS AVSS P90 P91 TESTD EXS0 EXS1 LOBAT PB4 PB5 SO Pin VPP EO0 EO1 EO2 EO3 EO4 EO5 EO6 EO7 EA0 EA1 EA2 EA3 EA4 EA5 EA6 EA7 EA8 EA9 EA10 EA11 EA12 EA13 EA14 EA15 EA16 CE OE PGM VCC VSS Note Pins not indicated in the figure should be left open H8 393...

Page 134: ...PROM mode Therefore when programming with a PROM programmer be sure to specify addresses from H 0000 to H EDFF If programming is inadvertently performed from H EE00 onward it may not be possible to continue PROM programming and verification When programming H FF should be set as the data in this address area H EE00 to H 1FFFF Figure 6 3 H8 3937 and H8 3937R Memory Map in PROM Mode ...

Page 135: ...hose for the standard HN27C101 EPROM However page programming is not supported and so page programming mode must not be set A PROM programmer that only supports page programming mode cannot be used When selecting a PROM programmer ensure that it supports high speed high reliability byte by byte programming Also be sure to specify addresses from H 0000 to H EDFF 6 3 1 Writing and Verifying An effic...

Page 136: ...ress 0 n 0 n 1 n PW Verify Write time t 3n ms OPW Last address Set read mode V 5 0 V 0 25 V V V CC PP CC Read all addresses End Error n 25 Address 1 address No Yes No Go Go Yes No No Go Go Write time t 0 2 ms 5 Figure 6 4 High Speed High Reliability Programming Flow Chart ...

Page 137: ...it Test Condition Input high level voltage EO7 to EO0 EA16 to EA0 OE CE PGM VIH 2 4 VCC 0 3 V Input low level voltage EO7 to EO0 EA16 to EA0 OE CE PGM VIL 0 3 0 8 V Output high level voltage EO7 to EO0 VOH 2 4 V IOH 200 µA Output low level voltage EO7 to EO0 VOL 0 45 V IOL 0 8 mA Input leakage current EO7 to EO0 EA16 to EA0 OE CE PGM ILI 2 µA Vin 5 25 V 0 5 V VCC current ICC 40 mA VPP current IPP ...

Page 138: ... 2 µs Programming pulse width tPW 0 19 0 20 0 21 ms PGM pulse width for overwrite programming tOPW 3 0 19 5 25 ms CE setup time tCES 2 µs VCC setup time tVCS 2 µs Data output delay time tOE 0 200 ns Notes 1 Input pulse level 0 45 V to 2 4 V Input rise time fall time 20 ns Timing reference levels Input 0 8 V 2 0 V Output 0 8 V 2 0 V 2 tDF is defined at the point at which the output is floating and ...

Page 139: ...t data Output data Verify Address Data VPP VPP tAS tAH tDS tDH tDF tOE tOES tPW tOPW tVPS tVCS tCES VCC VCC CE PGM OE VCC 1 VCC Note topw is defined by the value shown in figure 6 4 High Speed High Reliability Programming Flowchart Figure 6 5 PROM Write Verify Timing ...

Page 140: ...aligned If they are not the chip may be destroyed by excessive current flow Before programming be sure that the chip is properly mounted in the PROM programmer Avoid touching the socket adapter or chip while programming since this may cause contact faults and write errors Take care when setting the programming mode as page programming is not supported When programming with a PROM programmer be sur...

Page 141: ...creening procedure Program chip and verify programmed data Bake chip for 24 to 48 hours at 125 C to 150 C with power off Read and check program Install Figure 6 6 Recommended Screening Procedure If a series of programming errors occurs while the same PROM programmer is in use stop programming and check the PROM programmer and socket adapter for defects Please inform Hitachi of any abnormal conditi...

Page 142: ...130 ...

Page 143: ...us allowing high speed 2 state access for both byte data and word data 7 1 1 Block Diagram Figure 7 1 shows a block diagram of the on chip RAM H FF7E H FF7F Internal data bus upper 8 bits Internal data bus lower 8 bits Even numbered address Odd numbered address H FF7E H F782 H F780 H F780 H F782 H F781 H F783 On chip RAM Figure 7 1 RAM Block Diagram H8 3935 H8 3935R ...

Page 144: ...132 ...

Page 145: ...ation for information on executing bit manipulation instructions to write data in PCR or PDR Block diagrams of each port are given in Appendix C I O Port Block Diagrams Table 8 1 Port Functions Port Description Pins and Functions Other Functions Function Switching Registers Port 1 8 bit I O port MOS input pull up option P17 to P15 IRQ3 to IRQ1 TMIF TMIC External interrupts 3 to 1 Timer event inter...

Page 146: ... I O port P42 TXD32 P41 RXD32 P40 SCK32 SCI32 data output TXD32 data input RXD32 clock input output SCK32 SCR32 SMR32 Port 5 8 bit I O port MOS input pull up option P57 to P50 WKP7 to WKP0 Wakeup input WKP7 to WKP0 PMR5 Port 6 8 bit I O port MOS input pull up option P67 to P60 Port 7 8 bit I O port P77 to P70 Port 8 8 bit I O port P87 to P80 Port 9 4 bit I O port P93 to P90 Port A 4 bit I O port P...

Page 147: ...L P1 TMOW 2 1 0 Figure 8 1 Port 1 Pin Configuration 8 2 2 Register Configuration and Description Table 8 2 shows the port 1 register configuration Table 8 2 Port 1 Registers Name Abbrev R W Initial Value Address Port data register 1 PDR1 R W H 00 H FFD4 Port control register 1 PCR1 W H 00 H FFE4 Port pull up control register 1 PUCR1 R W H 00 H FFE0 Port mode register 1 PMR1 R W H 00 H FFC8 ...

Page 148: ... pins P17 to P10 functions as an input pin or output pin Setting a PCR1 bit to 1 makes the corresponding pin an output pin while clearing the bit to 0 makes the pin an input pin The settings in PCR1 and in PDR1 are valid only when the corresponding pin is designated in PMR1 as a general I O pin Upon reset PCR1 is initialized to H 00 PCR1 is a write only register which is always read as all 1s 3 Po...

Page 149: ...ng edge sensing can be designated for IRQ3 TMIF For details on TMIF settings see 3 Timer Control Register F TCRF in 9 4 2 Bit 6 P16 IRQ2 pin function switch IRQ2 This bit selects whether pin P16 IRQ2 is used as P16 or as IRQ2 Bit 6 IRQ2 Description 0 Functions as P16 I O pin initial value 1 Functions as IRQ2 input pin Note Rising or falling edge sensing can be designated for IRQ2 Bit 5 P15 IRQ1 TM...

Page 150: ...s bit selects whether pin P13 TMIG is used as P13 or as TMIG Bit 3 TMIG Description 0 Functions as P13 I O pin initial value 1 Functions as TMIG input pin Bit 2 P12 TMOFH pin function switch TMOFH This bit selects whether pin P12 TMOFH is used as P12 or as TMOFH Bit 2 TMOFH Description 0 Functions as P12 I O pin initial value 1 Functions as TMOFH output pin Bit 1 P11 TMOFL pin function switch TMOF...

Page 151: ...139 Bit 0 P10 TMOW pin function switch TMOW This bit selects whether pin P10 TMOW is used as P10 or as TMOW Bit 0 TMOW Description 0 Functions as P10 I O pin initial value 1 Functions as TMOW output pin ...

Page 152: ...CR16 in PCR1 IRQ2 0 1 PCR16 0 1 Pin function P16 input pin P16 output pin IRQ2 input pin P15 IRQ1 TMIC The pin function depends on bit IRQ1 in PMR1 bits TMC2 to TMC0 in TMC and bit PCR15 in PCR1 IRQ1 0 1 PCR15 0 1 TMC2 to TMC0 Not 111 111 Pin function P15 input pin P15 output pin IRQ1 input pin IRQ1 TMIC input pin Note When this pin is used as the TMIC input pin clear bit IEN1 to 0 in IENR1 to dis...

Page 153: ...t TMOFH in PMR1 and bit PCR12 in PCR1 TMOFH 0 1 PCR12 0 1 Pin function P12 input pin P12 output pin TMOFH output pin P11 TMOFL The pin function depends on bit TMOFL in PMR1 and bit PCR11 in PCR1 TMOFL 0 1 PCR11 0 1 Pin function P11 input pin P11 output pin TMOFL output pin P10 TMOW The pin function depends on bit TMOW in PMR1 and bit PCR10 in PCR1 TMOW 0 1 PCR10 0 1 Pin function P10 input pin P10 ...

Page 154: ...vious state High impedance Retains previous state Functional Functional Note A high level signal is output when the MOS pull up is in the on state 8 2 5 MOS Input Pull Up Port 1 has a built in MOS input pull up function that can be controlled by software When a PCR1 bit is cleared to 0 setting the corresponding PUCR1 bit to 1 turns on the MOS input pull up for that pin The MOS input pull up functi...

Page 155: ...chip P24 P23 P22 SO1 P21 SI1 P20 SCK1 Port 2 FLEX decoder RESET SS MOSI MISO SCK Note Connected inside the chip Figure 8 2 Port 2 Functional Configuration 8 3 2 Register Configuration and Description Table 8 5 shows the port 2 register configuration Table 8 5 Port 2 Registers Name Abbrev R W Initial Value Address Port data register 2 PDR2 R W H 00 H FFD5 Port control register 2 PCR2 W H 00 H FFE5 ...

Page 156: ...2 pins P24 to P20 functions as an input pin or output pin Setting a PCR2 bit to 1 makes the corresponding pin an output pin while clearing the bit to 0 makes the pin an input pin The settings in PCR2 and PDR2 are valid only when the corresponding pin is designated in PMR2 as a general I O pin Upon reset PCR2 is initialized to H 00 PCR2 is a write only register which is always read as all 1s 3 Port...

Page 157: ...tch SO1 This bit selects whether pin P22 SO1 is used as P22 or as SO1 Bit 2 SO1 Description 0 Functions as P22 I O pin initial value 1 Functions as SO1 output pin Bit 1 P21 SI1 pin function switch SI1 This bit selects whether pin P21 SI1 is used as P21 or as SI1 Bit 1 SI1 Description 0 Functions as P21 I O pin initial value 1 Functions as SI1 input pin Bit 0 P20 SCK1 pin function switch SCK1 This ...

Page 158: ...er individual port 2 pins are set as CMOS or NMOS open drain when 1 is set in PCR A 0 setting should be used for this function Upon reset PMR4 is initialized to H 00 Bit n NMOS open drain output select NMODn These bits select NMOS open drain when pin P2n is used as an output pin These bits should be cleared to 0 Bit n NMODn Description 0 CMOS setting initial value 1 NMOS open drain setting n 4 to ...

Page 159: ...he function depends on bit SI1 in PMR2 and bit PCR21 in PCR2 SI1 0 1 PCR21 0 1 Function P21 input P21 output SI1 input P20 SCK1 The function depends on bit SCK1 in PMR2 and bit PCR20 in PCR2 SCK1 0 1 PCR20 0 1 Function P20 input P20 output SCK1 I O Don t care 8 3 4 States Table 8 7 shows the port 2 states in each operating mode Table 8 7 Port 2 States Functions Reset Sleep Subsleep Standby Watch S...

Page 160: ...ure 8 3 Port 3 Pin Configuration 8 4 2 Register Configuration and Description Table 8 8 shows the port 3 register configuration Table 8 8 Port 3 Registers Name Abbrev R W Initial Value Address Port data register 3 PDR3 R W H 00 H FFD6 Port control register 3 PCR3 W H 00 H FFE6 Port pull up control register 3 PUCR3 R W H 00 H FFE1 Port mode register 3 PMR3 R W H 04 H FFCA ...

Page 161: ... pins P37 to P30 functions as an input pin or output pin Setting a PCR3 bit to 1 makes the corresponding pin an output pin while clearing the bit to 0 makes the pin an input pin The settings in PCR3 and in PDR3 are valid only when the corresponding pin is designated in PMR3 as a general I O pin Upon reset PCR3 is initialized to H 00 PCR3 is a write only register which is always read as all 1s 3 Po...

Page 162: ...it 5 Watchdog timer source clock select WDCKS This bit selects the watchdog timer source clock Bit 5 WDCKS Description 0 ø 8192 selected initial value 1 øw 32 selected Bit 4 TMIG noise canceler select NCS This bit controls the noise canceler for the input capture input signal TMIG Bit 4 NCS Description 0 Noise cancellation function not used initial value 1 Noise cancellation function used Bit 3 P4...

Page 163: ...t pin 8 4 3 Pin Functions Table 8 9 shows the port 3 pin functions Table 8 9 Port 3 Pin Functions Pin Pin Functions and Selection Method P37 P36 P30 The pin function depends on bit PCR3n in PCR3 n 7 6 0 PCR3n 0 1 Pin function P3n input pin P3n output pin P35 TXD31 The pin function depends on bit TE in SCR31 bit SPC31 in SPCR and bit PCR35 in PCR3 SPC31 0 1 TE 0 1 PCR35 0 1 Pin function P35 input p...

Page 164: ... function P33 input pin P33 output pin SCK31 output pin SCK31 input pin P32 RESO The pin function depends on bit RESO in PMR3 and bit PCR32 in PCR3 RESO 0 1 PCR32 0 1 Pin function P32 input pin P32 output pin RESO output pin P31 UD The pin function depends on bit UD in PMR3 and bit PCR31 in PCR3 UD 0 1 PCR31 0 1 Pin function P31 input pin P31 output pin UD input pin Don t care ...

Page 165: ... state Functional Functional P32 RESO Reset output P31 UD P30 High impedance Note A high level signal is output when the MOS pull up is in the on state 8 4 5 MOS Input Pull Up Port 3 has a built in MOS input pull up function that can be controlled by software When a PCR3 bit is cleared to 0 setting the corresponding PUCR3 bit to 1 turns on the MOS pull up for that pin The MOS pull up function is i...

Page 166: ...rated in the chip It cannot be connected to an IC outside the chip P4 P4 P4 P4 IRQ0 TXD32 RXD32 SCK32 3 2 1 0 Port 4 FLEX decoder READY Note Connected inside the chip P43 only Figure 8 4 Port 4 Pin Configuration 8 5 2 Register Configuration and Description Table 8 11 shows the port 4 register configuration Table 8 11 Port 4 Registers Name Abbrev R W Initial Value Address Port data register 4 PDR4 ...

Page 167: ...PDR4 is initialized to H F8 2 Port control register 4 PCR4 Bit Initial value Read Write 7 1 6 1 5 1 4 1 3 1 0 PCR4 0 W 2 PCR4 0 W 1 PCR4 0 W 2 1 0 PCR4 is an 8 bit register for controlling whether each of port 4 pins P42 to P40 functions as an input pin or output pin Setting a PCR4 bit to 1 makes the corresponding pin an output pin while clearing the bit to 0 makes the pin an input pin PCR4 and PD...

Page 168: ...SPCR and bit PCR42 in PCR4 SPC32 0 1 TE 0 1 PCR42 0 1 Pin function P42 input pin P42 output pin TXD32 output pin P41 RXD32 The pin function depends on bit RE in SCR32 and bit PCR41 in PCR4 RE 0 1 PCR41 0 1 Pin function P41 input pin P41 output pin RXD32 input pin P40 SCK32 The pin function depends on bits CKE1 and CKE0 in SCR32 bit COM32 in SMR32 and bit PCR40 in PCR4 CKE1 0 1 CKE0 0 1 COM32 0 1 P...

Page 169: ... mode Table 8 13 Port 4 Pin States Pins Reset Sleep Subsleep Standby Watch Subactive Active P43 IRQ0 High Retains previous state Retains previous state Retains previous state Retains previous state Functional Functional P42 TXD32 P41 RXD32 P40 SCK32 High impedance High impedance ...

Page 170: ...ure 8 5 Port 5 Pin Configuration 8 6 2 Register Configuration and Description Table 8 14 shows the port 5 register configuration Table 8 14 Port 5 Registers Name Abbrev R W Initial Value Address Port data register 5 PDR5 R W H 00 H FFD8 Port control register 5 PCR5 W H 00 H FFE8 Port pull up control register 5 PUCR5 R W H 00 H FFE2 Port mode register 5 PMR5 R W H 00 H FFCC ...

Page 171: ...t 5 pins P57 to P50 functions as an input pin or output pin Setting a PCR5 bit to 1 makes the corresponding pin an output pin while clearing the bit to 0 makes the pin an input pin PCR5 and PDR5 settings are valid when the corresponding pins are designated for general purpose input output by PMR5 Upon reset PCR5 is initialized to H 00 PCR5 is a write only register which is always read as all 1s 3 ...

Page 172: ...5n WKPn pin function switch WKPn These bits select whether the pin is used as P5n or WKPn Bit n WKPn Description 0 Functions as P5n I O pin initial value 1 Functions as WKPn input pin n 7 to 0 8 6 3 Pin Functions Table 8 15 shows the port 5 pin functions Table 8 15 Port 5 Pin Functions Pin Pin Functions and Selection Method P57 WKP7 to The pin function depends on bit WKPn in PMR5 and bit PCR5n in ...

Page 173: ...etains previous state Functional Functional Note A high level signal is output when the MOS pull up is in the on state 8 6 5 MOS Input Pull Up Port 5 has a built in MOS input pull up function that can be controlled by software When a PCR5 bit is cleared to 0 setting the corresponding PUCR5 bit to 1 turns on the MOS pull up for that pin The MOS pull up function is in the off state after a reset PCR...

Page 174: ...Port 6 Figure 8 6 Port 6 Pin Configuration 8 7 2 Register Configuration and Description Table 8 17 shows the port 6 register configuration Table 8 17 Port 6 Registers Name Abbrev R W Initial Value Address Port data register 6 PDR6 R W H 00 H FFD9 Port control register 6 PCR6 W H 00 H FFE9 Port pull up control register 6 PUCR6 R W H 00 H FFE3 ...

Page 175: ... register for controlling whether each of the port 6 pins P67 to P60 functions as an input pin or output pin Setting a PCR6 bit to 1 makes the corresponding pin P67 to P60 an output pin while clearing the bit to 0 makes the pin an input pin Upon reset PCR6 is initialized to H 00 PCR6 is a write only register which always reads all 1s 3 Port pull up control register 6 PUCR6 Bit Initial value Read W...

Page 176: ...leep Standby Watch Subactive Active P67 to P60 High impedance Retains previous state Retains previous state High impedance Retains previous state Functional Functional Note A high level signal is output when the MOS pull up is in the on state 8 7 5 MOS Input Pull Up Port 6 has a built in MOS pull up function that can be controlled by software When a PCR6 bit is cleared to 0 setting the correspondi...

Page 177: ...4 P73 Port 7 P72 P71 P70 Figure 8 7 Port 7 Pin Configuration 8 8 2 Register Configuration and Description Table 8 20 shows the port 7 register configuration Table 8 20 Port 7 Registers Name Abbrev R W Initial Value Address Port data register 7 PDR7 R W H 00 H FFDA Port control register 7 PCR7 W H 00 H FFEA ...

Page 178: ... are cleared to 0 the pin states are read Upon reset PDR7 is initialized to H 00 2 Port control register 7 PCR7 Bit Initial value Read Write 7 PCR7 0 W 6 PCR7 0 W 5 PCR7 0 W 4 PCR7 0 W 3 PCR7 0 W 0 PCR7 0 W 2 PCR7 0 W 1 PCR7 0 W 7 6 5 4 3 2 1 0 PCR7 is an 8 bit register for controlling whether each of the port 7 pins P77 to P70 functions as an input pin or output pin Setting a PCR7 bit to 1 makes ...

Page 179: ... bit PCR7n in PCR7 n 7 to 0 PCR7n 0 1 Pin function P7n input pin P7n output pin 8 8 4 Pin States Table 8 22 shows the port 7 pin states in each operating mode Table 8 22 Port 7 Pin States Pins Reset Sleep Subsleep Standby Watch Subactive Active P77 to P70 High impedance Retains previous state Retains previous state High impedance Retains previous state Functional Functional ...

Page 180: ...a register 8 PDR8 R W H 00 H FFDB Port control register 8 PCR8 W H 00 H FFEB 1 Port data register 8 PDR8 Bit Initial value Read Write 7 P8 0 R W 6 P8 0 R W 5 P8 0 R W 4 P8 0 R W 3 P8 0 R W 0 P8 0 R W 2 P8 0 R W 1 P8 0 R W 7 6 5 4 3 2 1 0 PDR8 is an 8 bit register that stores data for port 8 pins P87 to P80 If port 8 is read while PCR8 bits are set to 1 the values stored in PDR8 are read regardless...

Page 181: ... initialized to H 00 PCR8 is a write only register which is always read as all 1s 8 9 3 Pin Functions Table 8 24 shows the port 8 pin functions Table 8 24 Port 8 Pin Functions Pin Pin Functions and Selection Method P87 to P80 The pin function depends on bit PCR8n in PCR8 n 7 to 0 PCR8n 0 1 Pin function P8n input pin P8n output pin 8 9 4 Pin States Table 8 25 shows the port 8 pin states in each ope...

Page 182: ... P92 P91 P90 Port 9 Figure 8 9 Port 9 Pin Configuration 8 10 2 Register Configuration and Description Table 8 26 shows the port 9 register configuration Table 8 26 Port 9 Registers Name Abbrev R W Initial Value Address Port data register 9 PDR9 R W H 00 H FFDC Port control register 9 PCR9 R H F0 H FFEC ...

Page 183: ...are cleared to 0 the pin states are read Upon reset PDR9 is initialized to H F0 2 Port control register 9 PCR9 Bit Initial value Read Write 7 1 6 1 5 1 4 1 3 PCR93 0 W 0 PCR90 0 W 2 PCR92 0 W 1 PCR91 0 W PCR9 is an 8 bit register for controlling whether each of the port 9 pins P93 to P90 functions as an input pin or output pin Setting a PCR9 bit to 1 makes the corresponding pin an output pin while...

Page 184: ... bit PCR9n in PCR9 n 3 to 0 PCR9n 0 1 Pin function P9n input pin P9n output pin 8 10 4 Pin States Table 8 28 shows the port 9 pin states in each operating mode Table 8 28 Port 9 Pin States Pins Reset Sleep Subsleep Standby Watch Subactive Active P93 to P90 High impedance Retains previous state Retains previous state High impedance Retains previous state Functional Functional ...

Page 185: ...ess Port data register A PDRA R W H F0 H FFDD Port control register A PCRA W H F0 H FFED 1 Port data register A PDRA Bit Initial value Read Write 7 1 6 1 5 1 4 1 3 PA 0 R W 0 PA 0 R W 2 PA 0 R W 1 PA 0 R W 3 2 1 0 PDRA is an 8 bit register that stores data for port A pins PA3 to PA0 If port A is read while PCRA bits are set to 1 the values stored in PDRA are read regardless of the actual pin state...

Page 186: ...is a write only register which always reads all 1s 8 11 3 Pin Functions Table 8 30 shows the port A pin functions Table 8 30 Port A Pin Functions Pin Pin Functions and Selection Method PA3 to PA0 The pin function depends on bit PCRAn in PCRA n 3 to 0 PCRAn 0 1 Pin function PAn input pin PAn output pin 8 11 4 Pin States Table 8 31 shows the port A pin states in each operating mode Table 8 31 Port A...

Page 187: ...tion Table 8 32 shows the port B register configuration Table 8 32 Port B Register Name Abbrev R W Address Port data register B PDRB R H FFDE Port Data Register B PDRB Bit Read Write 7 PB R 6 PB R 5 PB R 4 PB R 3 PB R 0 PB R 2 PB R 1 PB R 3 2 1 0 7 6 5 4 Reading PDRB always gives the pin states However if a port B pin is selected as an analog input channel for the A D converter by AMR bits CH3 to ...

Page 188: ...escriptions Table 8 33 shows the registers used by the input output data inversion function Table 8 33 Register Configuration Name Abbreviation R W Initial Value Address Serial port control register SPCR R W H C0 H FF91 Serial Port Control Register SPCR Bit Initial value Read Write 7 1 6 1 5 SPC32 0 R W 4 SPC31 0 R W 3 SCINV3 0 R W 0 SCINV0 0 R W 2 SCINV2 0 R W 1 SCINV1 0 R W SPCR is an 8 bit read...

Page 189: ...pin P35 TXD31 is used as P35 or as TXD31 Bit 4 SPC31 Description 0 Functions as P35 I O pin initial value 1 Functions as TXD31 output pin Note Set the TE bit in SCR3 after setting this bit to 1 Bit 3 TXD32 pin output data inversion switch Bit 3 specifies whether or not TXD32 pin output data is to be inverted Bit 3 SCINV3 Description 0 TXD32 output data is not inverted initial value 1 TXD32 output ...

Page 190: ...tput When modifying a serial port control register do so in a state in which data changes are invalidated 8 14 Application Note 8 14 1 The Management of the Un Use Terminal If an I O pin not used by the user system is floating pull it up or down If an unused pin is an input pin handle it in one of the following ways Pull it up to VCC with an on chip pull up MOS Pull it up to VCC with an external r...

Page 191: ... 32 øW øW 4 to øW 32 9 choices TMOW Timer C 8 bit timer Interval function Event counting function Up count down count selectable ø 4 to ø 8192 øW 4 7 choices TMIC Up count down count controllable by software or hardware Timer F 16 bit timer Event counting function Also usable as two independent 8 bit timers Output compare output function ø 4 to ø 32 øW 4 4 choices TMIF TMOFL TMOFH Timer G 8 bit ti...

Page 192: ... Features of timer A are given below Choice of eight internal clock sources ø 8192 ø 4096 ø 2048 ø 512 ø 256 ø 128 ø 32 ø 8 Choice of four overflow periods øw 32768 øw 16384 øw 8192 øw 1024 when timer A is used as a time base An interrupt is requested when the counter overflows Any of nine clock signals can be output at the TMOW pin øw divided by 32 16 8 or 4 and the system clock divided by 32 16 ...

Page 193: ...WOSR Note Can be selected only when the prescaler W output øW 128 is used as the TCA input clock Timer mode register A Timer counter A Timer A overflow interrupt request flag Prescaler W Prescaler S Subclock output select register W ø Figure 9 1 Block Diagram of Timer A 3 Pin configuration Table 9 2 shows the timer A pin configuration Table 9 2 Pin Configuration Name Abbrev I O Function Clock outp...

Page 194: ... H FFB1 Clock stop register 1 CKSTPR1 R W H FF H FFFA Subclock output select register CWOSR R W H FE H FF92 9 2 2 Register Descriptions 1 Timer mode register A TMA Bit Initial value Read Write 7 TMA7 0 R W 6 TMA6 0 R W 5 TMA5 0 R W 4 1 3 TMA3 0 R W 0 TMA0 0 R W 2 TMA2 0 R W 1 TMA1 0 R W TMA is an 8 bit read write register for selecting the prescaler input clock and output clock Upon reset TMA is i...

Page 195: ...sleep mode A øw signal divided by 32 16 8 or 4 can be output in active mode sleep mode and subactive mode øw is output in all modes except the reset state CWOSR TMA CWOS Bit 7 TMA7 Bit 6 TMA6 Bit 5 TMA5 Clock Output 0 0 0 0 ø 32 initial value 1 ø 16 1 0 ø 8 1 ø 4 1 0 0 øW 32 1 øW 16 1 0 øW 8 1 øW 4 1 øW Don t care Bit 4 Reserved bit Bit 4 is reserved it is always read as 1 and cannot be modified ...

Page 196: ...t 2 TMA2 Bit 1 TMA1 Bit 0 TMA0 Prescaler and Divider Ratio or Overflow Period Function 0 0 0 0 PSS ø 8192 initial value Interval timer 1 PSS ø 4096 1 0 PSS ø 2048 1 PSS ø 512 1 0 0 PSS ø 256 1 PSS ø 128 1 0 PSS ø 32 1 PSS ø 8 1 0 0 0 PSW øw 32768 Time base 1 PSW øw 16384 overflow period 1 0 PSW øw 8192 1 PSW øw 1024 1 0 0 PSW and TCA are reset 1 1 0 1 ...

Page 197: ...g bits TMA3 and TMA2 of TMA to 11 Upon reset TCA is initialized to H 00 3 Clock stop register 1 CKSTPR1 Bit 7 6 5 4 3 2 1 0 S1CKSTP S31CKSTPS32CKSTP ADCKSTP TGCKSTP TFCKSTP TCCKSTP TACKSTP Initial value 1 1 1 1 1 1 1 1 Read Write R W R W R W R W R W R W R W R W CKSTPR1 is an 8 bit read write register that performs module standby mode control for peripheral modules Only the bit relating to timer A ...

Page 198: ...ode register A TMA is cleared to 0 timer A functions as an 8 bit interval timer Upon reset TCA is cleared to H 00 and bit TMA3 is cleared to 0 so up counting and interval timing resume immediately The clock input to timer A is selected by bits TMA2 to TMA0 in TMA any of eight internal clock signals output by prescaler S can be selected After the count value in TCA reaches H FF the next clock signa...

Page 199: ... all modes except the reset state 9 2 4 Timer A Operation States Table 9 4 summarizes the timer A operation states Table 9 4 Timer A Operation States Operation Mode Reset Active Sleep Watch Sub active Sub sleep Standby Module Standby TCA Interval Reset Functions Functions Halted Halted Halted Halted Halted Time base Reset Functions Functions Functions Functions Functions Halted Halted TMA Reset Fu...

Page 200: ... ø 8192 ø 2048 ø 512 ø 64 ø 16 ø 4 øW 4 or an external clock can be used to count external events An interrupt is requested when the counter overflows Up down counter switching is possible by hardware or software Subactive mode and subsleep mode operation is possible when øW 4 is selected as the internal clock or when an external clock is selected Use of module standby mode enables this module to ...

Page 201: ... Timer counter C Timer load register C Timer C overflow interrupt request flag Prescaler S Figure 9 2 Block Diagram of Timer C 3 Pin configuration Table 9 5 shows the timer C pin configuration Table 9 5 Pin Configuration Name Abbrev I O Function Timer C event input TMIC Input Input pin for event input to TCC Timer C up down count selection UD Input Timer C up down select ...

Page 202: ...ons 1 Timer mode register C TMC Bit Initial value Read Write 7 TMC7 0 R W 6 TMC6 0 R W 5 TMC5 0 R W 4 1 3 1 0 TMC0 0 R W 2 TMC2 0 R W 1 TMC1 0 R W TMC is an 8 bit read write register for selecting the auto reload function and input clock and performing up down counter control Upon reset TMC is initialized to H 18 Bit 7 Auto reload function select TMC7 Bit 7 selects whether timer C is used as an in...

Page 203: ...ts 2 to 0 Clock select TMC2 to TMC0 Bits 2 to 0 select the clock input to TCC For external event counting either the rising or falling edge can be selected Bit 2 TMC2 Bit 1 TMC1 Bit 0 TMC0 Description 0 0 0 Internal clock ø 8192 initial value 0 0 1 Internal clock ø 2048 0 1 0 Internal clock ø 512 0 1 1 Internal clock ø 64 1 0 0 Internal clock ø 16 1 0 1 Internal clock ø 4 1 1 0 Internal clock øW 4...

Page 204: ... 3 Timer load register C TLC Bit Initial value Read Write 7 TLC7 0 W 6 TLC6 0 W 5 TLC5 0 W 4 TLC4 0 W 3 TLC3 0 W 0 TLC0 0 W 2 TLC2 0 W 1 TLC1 0 W TLC is an 8 bit write only register for setting the reload value of timer counter C TCC When a reload value is set in TLC the same value is loaded into timer counter C as well and TCC starts counting up from that value When TCC overflows or underflows du...

Page 205: ... so TCC continues up counting as an interval up counter without halting immediately after a reset The timer C operating clock is selected from seven internal clock signals output by prescalers S and W or an external clock input at pin TMIC The selection is made by bits TMC2 to TMC0 in TMC TCC up down count control can be performed either by software or hardware The selection is made by bits TMC6 a...

Page 206: ... mode are the same as in interval mode In auto reload mode TMC7 1 when a new value is set in TLC the TLC value is also set in TCC 3 Event counter operation Timer C can operate as an event counter counting rising or falling edges of an external event signal input at pin TMIC External event counting is selected by setting bits TMC2 to TMC0 in timer mode register C to all 1s 111 When timer C is used ...

Page 207: ...selected as the TCC internal clock in active mode or sleep mode since the system clock and internal clock are mutually asynchronous synchronization is maintained by a synchronization circuit This results in a maximum count cycle error of 1 ø s When the counter is operated in subactive mode or subsleep mode either select øw 4 as the internal clock or select an external clock The counter will not op...

Page 208: ...t sources one compare match one overflow Can operate as two independent 8 bit timers timer FH and timer FL in 8 bit mode Timer FH 8 Bit Timer Timer FL 8 Bit Timer Event Counter Internal clock Choice of 4 ø 32 ø 16 ø 4 øw 4 Event input TMIF pin Toggle output One compare match signal output to TMOFH pin initial value settable One compare match signal output to TMOFL pin initial value settable Counte...

Page 209: ...gend IRRTFH IRRTFL TCRF TCSRF TCFH TCFL OCRFH OCRFL IRRTFH IRRTFL PSS Timer control register F Timer control status register F 8 bit timer counter FH 8 bit timer counter FL Output compare register FH Output compare register FL Timer FH interrupt request flag Timer FL interrupt request flag Prescaler S Internal data bus Toggle circuit Figure 9 3 Block Diagram of Timer F ...

Page 210: ...le output pin 4 Register configuration Table 9 9 shows the register configuration of timer F Table 9 9 Timer F Registers Name Abbrev R W Initial Value Address Timer control register F TCRF W H 00 H FFB6 Timer control status register F TCSRF R W H 00 H FFB7 8 bit timer counter FH TCFH R W H 00 H FFB8 8 bit timer counter FL TCFL R W H 00 H FFB9 Output compare register FH OCRFH R W H FF H FFBA Output...

Page 211: ...nd TCFL are each initialized to H 00 upon reset a 16 bit mode TCF When CKSH2 is cleared to 0 in TCRF TCF operates as a 16 bit counter The TCF input clock is selected by bits CKSL2 to CKSL0 in TCRF TCF can be cleared in the event of a compare match by means of CCLRH in TCSRF When TCF overflows from H FFFF to H 0000 OVFH is set to 1 in TCSRF If OVIEH in TCSRF is 1 at this time IRRTFH is set to 1 in ...

Page 212: ...et a 16 bit mode OCRF When CKSH2 is cleared to 0 in TCRF OCRF operates as a 16 bit register OCRF contents are constantly compared with TCF and when both values match CMFH is set to 1 in TCSRF At the same time IRRTFH is set to 1 in IRR2 If IENTFH in IENR2 is 1 at this time an interrupt request is sent to the CPU Toggle output can be provided from the TMOFH pin by means of compare matches and the ou...

Page 213: ...e output level H TOLH Bit 7 sets the TMOFH pin output level The output level is effective immediately after this bit is written Bit 7 TOLH Description 0 Low level initial value 1 High level Bits 6 to 4 Clock select H CKSH2 to CKSH0 Bits 6 to 4 select the clock input to TCFH from among four internal clock sources or TCFL overflow Bit 6 CKSH2 Bit 5 CKSH1 Bit 4 CKSH0 Description 0 0 0 16 bit mode cou...

Page 214: ...0 0 Counting on external event TMIF rising falling initial value 0 0 1 edge 1 0 1 0 0 1 1 Not available 1 0 0 Internal clock counting on ø 32 1 0 1 Internal clock counting on ø 16 1 1 0 Internal clock counting on ø 4 1 1 1 Internal clock counting on øw 4 Don t care Note 1 External event edge selection is set by IEG3 in the IRQ edge select register IEGR For details see 1 IRQ edge select register IE...

Page 215: ...ag H OVFH Bit 7 is a status flag indicating that TCFH has overflowed from H FF to H 00 This flag is set by hardware and cleared by software It cannot be set by software Bit 7 OVFH Description 0 Clearing conditions After reading OVFH 1 cleared by writing 0 to OVFH initial value 1 Setting conditions Set when TCFH overflows from H FF to H 00 Bit 6 Compare match flag H CMFH Bit 6 is a status flag indi...

Page 216: ...CRFH match Bit 4 CCLRH Description 0 16 bit mode TCF clearing by compare match is disabled 8 bit mode TCFH clearing by compare match is disabled initial value 1 16 bit mode TCF clearing by compare match is enabled 8 bit mode TCFH clearing by compare match is enabled Bit 3 Timer overflow flag L OVFL Bit 3 is a status flag indicating that TCFL has overflowed from H FF to H 00 This flag is set by har...

Page 217: ... interrupt request is disabled initial value 1 TCFL overflow interrupt request is enabled Bit 0 Counter clear L CCLRL Bit 0 selects whether TCFL is cleared when TCFL and OCRFL match Bit 0 CCLRL Description 0 TCFL clearing by compare match is disabled initial value 1 TCFL clearing by compare match is enabled 5 Clock stop register 1 CKSTPR1 Bit 7 6 5 4 3 2 1 0 S1CKSTP S31CKSTPS32CKSTP ADCKSTP TGCKST...

Page 218: ...is connected to the on chip peripheral modules by an 8 bit data bus When the CPU accesses these registers it therefore uses an 8 bit temporary register TEMP In 16 bit mode TCF read write access and OCRF write access must be performed 16 bits at a time using two consecutive byte size MOV instructions and the upper byte must be accessed before the lower byte Data will not be transferred correctly if...

Page 219: ...n TEMP to the upper register byte and direct transfer of the lower byte write data to the lower register byte Figure 9 4 shows an example in which H AA55 is written to TCF Write to upper byte CPU H AA TEMP H AA TCFH TCFL Bus interface Module data bus Write to lower byte CPU H 55 TEMP H AA TCFH H AA TCFL H 55 Bus interface Module data bus Figure 9 4 Write Access to TCF CPU TCF ...

Page 220: ... upper byte is read the upper byte data is transferred directly to the CPU When the lower byte is read the lower byte data is transferred directly to the CPU Figure 9 5 shows an example in which TCF is read when it contains H AAFF Read upper byte CPU H AA TEMP H FF TCFH H AA TCFL H FF Bus interface Module data bus Read lower byte CPU H FF TEMP H FF TCFH AB TCFL 00 Bus interface Module data bus Not...

Page 221: ...aler S or an external clock by means of bits CKSL2 to CKSL0 in TCRF OCRF contents are constantly compared with TCF and when both values match CMFH is set to 1 in TCSRF If IENTFH in IENR2 is 1 at this time an interrupt request is sent to the CPU and at the same time TMOFH pin output is toggled If CCLRH in TCSRF is 1 TCF is cleared TMOFH pin output can also be set by TOLH in TCRF When TCF overflows ...

Page 222: ...t on either the rising or falling edge of external event input External event edge selection is set by IEG3 in the interrupt controller s IEGR register An external event pulse width of at least 2 system clocks ø is necessary Shorter pulses will not be counted correctly 3 TMOFH TMOFL output timing In TMOFH TMOFL output the value set in TOLH TOLL in TCRF is output The output is toggled by the occurr...

Page 223: ... Operation Modes Operation Mode Reset Active Sleep Watch Subactive Subsleep Standby Module Standby TCF Reset Functions Functions Functions Halted Functions Halted Functions Halted Halted Halted OCRF Reset Functions Held Held Functions Held Held Held TCRF Reset Functions Held Held Functions Held Held Held TCSRF Reset Functions Held Held Functions Held Held Held Note When øw 4 is selected as the TCF...

Page 224: ... flag CMFL is set if the setting conditions for the lower 8 bits are satisfied When TCF overflows OVFH is set OVFL is set if the setting conditions are satisfied when the lower 8 bits overflow If a TCFL write and overflow signal output occur simultaneously the overflow signal is not output 2 8 bit timer mode a TCFH OCRFH In toggle output TMOFH pin output is toggled when a compare match occurs If a...

Page 225: ...f validity of Overflow signal and Compare match signal For interrupt request flag is set right after interrupt request is cleared interrupt process to one time timer FH timer FL interrupt might be repeated figure 9 7 2 Therefore to definitely clear interrupt request flag in active high speed medium speed mode clear should be processed after the time that calculated with below 1 formula And to defi...

Page 226: ...tion signal Internal signal nega active Overflow signal Compare match signal Internal signal nega active Interrupt Interrupt Normal Interrupt request flag clear Interrupt request flag clear 1 2 Figure 9 7 Clear Interrupt Request Flag when Interrupt Factor Generation Signal is Valid 4 Timer counter TCF read write When øw 4 is selected as the internal clock in active high speed medium speed mode wri...

Page 227: ...functions for rising and falling edges Level detection at counter overflow It is possible to detect whether overflow occurred when the input capture input signal was high or when it was low Selection of whether or not the counter value is to be cleared at the input capture input signal rising edge falling edge or both edges Two interrupt sources one input capture one overflow The input capture inp...

Page 228: ... Edge detector Level detector IRRTG ø øw 4 TMIG NCS Notation TMG TCG ICRGF ICRGR IRRTG NCS PSS Timer mode register G Timer counter G Input capture register GF Input capture register GR Timer G interrupt request flag Noise canceler select Prescaler S Internal data bus Figure 9 8 Block Diagram of Timer G ...

Page 229: ...r Descriptions 1 Timer counter TCG TCG7 TCG2 TCG1 TCG0 TCG6 TCG5 TCG4 TCG3 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 Bit Initial value Read Write TCG is an 8 bit up counter which is incremented by clock input The input clock is selected by bits CKS1 and CKS0 in TMG TMIG in PMR1 is set to 1 to operate TCG as an input capture timer or cleared to 0 to operate TCG as an interval timer In input capture timer ope...

Page 230: ...put capture operation the pulse width of the input capture input signal must be at least 2ø or 2øSUB when the noise canceler is not used ICRGF is initialized to H 00 upon reset 3 Input capture register GR ICRGR ICRGR7 ICRGR2 ICRGR1 ICRGR0 ICRGR6 ICRGR5 ICRGR4 ICRGR3 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 R R R R R R R R Bit Initial value Read Write ICRGR is an 8 bit read only register When a rising edge ...

Page 231: ...s a status flag indicating that TCG has overflowed from H FF to H 00 when the input capture input signal is high This flag is set by hardware and cleared by software It cannot be set by software Bit 7 OVFH Description 0 Clearing conditions After reading OVFH 1 cleared by writing 0 to OVFH initial value 1 Setting conditions Set when TCG overflows from H FF to H 00 Bit 6 Timer overflow flag L OVFL B...

Page 232: ...ignal Bits 3 and 2 Counter clear 1 and 0 CCLR1 CCLR0 Bits 3 and 2 specify whether or not TCG is cleared by the rising edge falling edge or both edges of the input capture input signal Bit 3 CCLR1 Bit 2 CCLR0 Description 0 0 TCG clearing is disabled initial value 0 1 TCG cleared by falling edge of input capture input signal 1 0 TCG cleared by rising edge of input capture input signal 1 1 TCG cleare...

Page 233: ...3 controls setting and clearing of module standby mode for timer G TGCKSTP Description 0 Timer G is set to module standby mode 1 Timer G module standby mode is cleared initial value 9 5 3 Noise Canceler The noise canceler consists of a digital low pass filter that eliminates high frequency component noise from the pulses input from the input capture input pin The noise canceler is set by NCS in PM...

Page 234: ... the input capture input signal has been sampled five times Therefore after making a setting for use of the noise cancellation function a pulse with at least five times the width of the sampling clock is a dependable input capture signal Even if noise cancellation is not used an input capture input signal pulse width of at least 2ø or 2øSUB is necessary to ensure that input capture operations are ...

Page 235: ...red by a rising edge falling edge or both edges of the input capture signal according to the setting of bits CCLR1 and CCLR0 in TMG If TCG overflows when the input capture signal is high the OVFH bit is set in TMG if TCG overflows when the input capture signal is low the OVFL bit is set in TMG If the OVIE bit in TMG is 1 when these bits are set IRRTG is set to 1 in IRR2 and if the IENTG bit in IEN...

Page 236: ... functions are provided for rising and falling edges Figure 9 11 shows the timing for rising falling edge input capture input Input capture input signal Input capture signal F Input capture signal R Figure 9 11 Input Capture Input Timing without Noise Cancellation Function b With noise cancellation function When noise cancellation is performed on the input capture input the passage of the input ca...

Page 237: ...e signal R Figure 9 12 Input Capture Input Timing with Noise Cancellation Function 4 Timing of input capture by input capture input Figure 9 13 shows the timing of input capture by input capture input Input capture signal TCG N 1 N N H XX N 1 Input capture register Figure 9 13 Timing of Input Capture by Input Capture Input ...

Page 238: ... rising edge falling edge or both edges of the input capture input signal Figure 9 14 shows the timing for clearing by both edges Input capture input signal Input capture signal F Input capture signal R TCG N N H 00 H 00 Figure 9 14 TCG Clear Timing ...

Page 239: ...se canceler operate on the øw 4 internal clock without regard to the ø subclock øw 8 øw 4 øw 2 Note that when another internal clock is selected TCG and the noise canceler do not operate and input of the input capture input signal does not result in input capture To operate the timer G in subactive mode or subsleep mode select øw 4 as the TCG internal clock and øw 2 as the subclock øSUB Note that ...

Page 240: ...low level Clock before switching Clock after switching Count clock TCG N N 1 Write to CKS1 and CKS0 2 Goes from low level to high level Clock before switching Clock before switching Count clock TCG N N 1 N 2 Write to CKS1 and CKS0 3 Goes from high level to low level TCG N N 1 N 2 Clock before switching Clock before switching Count clock Write to CKS1 and CKS0 ...

Page 241: ...ints should be noted when a port mode register is modified to switch the input capture function or the input capture input noise canceler function Switching input capture input pin function Note that when the pin function is switched by modifying TMIG in port mode register 1 PMR1 which performs input capture input pin control an edge will be regarded as having been input at the pin even though no ...

Page 242: ...pture input signal is low Switching input capture input noise canceler function When performing noise canceler function switching by modifying NCS in port mode register 3 PMR3 which controls the input capture input noise canceler TMIG should first be cleared to 0 Note that if NCS is modified without first clearing TMIG an edge will be regarded as having been input at the pin even though no valid e...

Page 243: ...cks when the noise canceler is used before clearing the interrupt enable flag to 0 There are two ways of preventing interrupt request flag setting when the pin function is switched by controlling the pin level so that the conditions shown in tables 9 16 and 9 17 are not satisfied or by setting the opposite of the generated edge in the IIEGS bit in TMG Set I bit to 1 in CCR Manipulate port mode reg...

Page 244: ...ut capture input signal as absolute values For this purpose CCLR1 and CCLR0 should both be set to 1 in TMG Figure 9 16 shows an example of the operation in this case Counter cleared TCG H FF H 00 Input capture input signal Input capture register GF Input capture register GR Figure 9 16 Timer G Application Example ...

Page 245: ...or øw 32 A reset signal is generated when the counter overflows The overflow period can be set from from 1 to 256 times 8192 ø or 32 øw from approximately 4 ms to 1000 ms when ø 2 00 MHz Use of module standby mode enables this module to be placed in standby mode independently when not used 2 Block diagram Figure 9 17 shows a block diagram of the watchdog timer PSS TCSRW TCW ø 8192 Notation TCSRW T...

Page 246: ...l value Read Write 7 B6WI 1 R 6 TCWE 0 R W 5 B4WI 1 R 4 TCSRWE 0 R W 3 B2WI 1 R 0 WRST 0 R W 2 WDON 0 R W 1 B0WI 1 R Note Write is permitted only under certain conditions which are given in the descriptions of the individual bits TCSRW is an 8 bit read write register that controls write access to TCW and TCSRW itself controls watchdog timer operations and indicates operating status Bit 7 Bit 6 wri...

Page 247: ...al value This bit is always read as 1 Data written to this bit is not stored Bit 4 Timer control status register W write enable TCSRWE Bit 4 controls the writing of data to TCSRW bits 2 and 0 Bit 4 TCSRWE Description 0 Data cannot be written to bits 2 and 0 initial value 1 Data can be written to bits 2 and 0 Bit 3 Bit 2 write inhibit B2WI Bit 3 controls the writing of data to bit 2 in TCSRW Bit 3 ...

Page 248: ... Bit 1 controls the writing of data to bit 0 in TCSRW Bit 1 B0WI Description 0 Bit 0 is write enabled 1 Bit 0 is write protected initial value This bit is always read as 1 Data written to this bit is not stored Bit 0 Watchdog timer reset WRST Bit 0 indicates that TCW has overflowed generating an internal reset signal The internal reset signal generated by the overflow resets the entire chip WRST i...

Page 249: ...control for peripheral modules Only the bit relating to the watchdog timer is described here For details of the other bits see the sections on the relevant modules Bit 2 Watchdog timer module standby mode control WDCKSTP Bit 2 controls setting and clearing of module standby mode for the watchdog timer WDCKSTP Description 0 Watchdog timer is set to module standby mode 1 Watchdog timer module standb...

Page 250: ...ck input ø 8192 or øw 32 The input clock is selected by bit WDCKS in port mode register 3 PMR3 ø 8192 is selected when WDCKS is cleared to 0 and øw 32 when set to 1 When TCSRWE 1 in TCSRW if 0 is written in B2WI and 1 is simultaneously written in WDON TCW starts counting up When the TCW count value reaches H FF the next clock input causes the watchdog timer to overflow and an internal reset signal...

Page 251: ... 2 106 30 10 3 7 3 8192 Figure 9 18 Typical Watchdog Timer Operations Example 9 6 4 Watchdog Timer Operation States Table 9 18 summarizes the watchdog timer operation states Table 9 18 Watchdog Timer Operation States Operation Mode Reset Active Sleep Watch Subactive Subsleep Standby Module Standby TCW Reset Functions Functions Halted Functions Halted Halted Halted Halted TCSRW Reset Functions Func...

Page 252: ...240 ...

Page 253: ...fer data length 8 or 16 bits Continuous clock output function Choice of 8 internal clocks ø 1024 to ø 4 øW 4 or external clock Interrupt generated on completion of transfer SCI31 SCI32 Synchronous serial transfer functions 8 bit transfer data length Transmission reception simultaneous transmission and reception Asynchronous serial transfer functions Multiprocessor communication function Choice of ...

Page 254: ...ction that performs interfacing to the FLEX decoder incorporated in the chip It cannot be connected to an IC outside the chip for data communication use 1 Features Features of SCI1 are listed below Choice of 8 bit or 16 bit transfer data length Choice of 8 internal clocks ø 1024 ø 256 ø 64 ø 32 ø 16 ø 8 ø 4 or øW 4 as clock source Interrupt request generated on completion of transfer ...

Page 255: ...control circuit SCR1 SCSR1 Transfer bit counter SDRU SDRL IRRS1 Transfer bit counter Notation SCR1 Serial control register 1 SCSR1 Serial control status register 1 SDRU Serial data register U SDRL Serial data register L IRRS1 Serial 1 interrupt request flag PSS Prescaler S Figure 10 1 SCI1 Block Diagram ...

Page 256: ... R W H 00 H FFA0 Serial control status register 1 SCSR1 R W H 9C H FFA1 Serial data register U SDRU R W Undefined H FFA2 Serial data register L SDRL R W Undefined H FFA3 Clock stop register 1 CKSTPR1 R W H FF H FFFA 10 2 2 Register Descriptions 1 Serial control register 1 SCR1 Bit Initial value Read Write 7 SNC1 0 R W 6 SNC0 0 R W 5 MRKON 0 R W 4 LTCH 0 R W 3 CKS3 0 R W 0 CKS0 0 R W 2 CKS2 0 R W 1...

Page 257: ...control MRKON Bit 5 controls tail mark output after transfer of 8 bit or 16 bit data Bit 5 MRKON Description 0 Tail mark is not output synchronous mode initial value 1 Tail mark is output SSB mode Note SCI1 is an internal function that performs interfacing to the on chip FLEX decoder It cannot be used with SSB mode selected Bit 4 LATCH TAIL select LTCH Bit 4 selects whether LATCH TAIL or HOLD TAIL...

Page 258: ...to 0 bits 2 to 0 selects the prescaler division ratio and the serial clock cycle Bit 2 Bit 1 Bit 0 Serial Clock Cycle CKS2 CKS1 CKS0 Prescaler Division Ratio ø 2 5 MHz 0 0 0 ø 1024 initial value 409 6 µs 0 0 1 ø 256 102 4 µs 0 1 0 ø 64 25 6 µs 0 1 1 ø 32 12 8 µs 1 0 0 ø 16 6 4 µs 1 0 1 ø 8 3 2 µs 1 1 0 ø 4 1 6 µs 1 1 1 øW 4 50 µs or 104 2 µs 2 Serial control status register 1 SCSR1 Bit Initial val...

Page 259: ... not be manipulated during transmission Note The SOL bit setting is also invalid in SSB mode Bit 6 SOL Description 0 Read SO1 output level is low initial value Write Changes SO1 output to low level 1 Read SO1 output level is high Write Changes SO1 output to high level Bit 5 Overrun error flag ORER Bit 5 indicates that an overrun error has occurred when using an external clock If extra pulses are s...

Page 260: ...ess Write Starts transfer operation 3 Serial data register U SDRU Bit Initial value Read Write 7 SDRU7 Undefined R W 6 SDRU6 Undefined R W 5 SDRU5 Undefined R W 4 SDRU4 Undefined R W 3 SDRU3 Undefined R W 0 SDRU0 Undefined R W 2 SDRU2 Undefined R W 1 SDRU1 Undefined R W SDRU is an 8 bit read write register used as the data register for the upper 8 bits in 16 bit transfer while SDRL is used for the...

Page 261: ...MSB LSB direction The operation in 16 bit transfer is the same as for 8 bit transfer except that the input data is taken from SDRU SDRL read write operations must only be performed after data transmission reception has been completed Data contents are not guaranteed if read write operations are executed while data transmission reception is in progress The value of SDRL is undefined upon reset 5 Cl...

Page 262: ...om 8 internal clocks When an internal clock is selected the SCK1 functions as the clock output When continuous clock output mode is set SNC1 SNC0 10 in SCR1 the clock selected by bits CKS2 to CKS0 ø 1024 to øW 4 is output continuously from the SCK1 2 Data transfer format The SCI1 transfer format is shown in figure 10 2 LSB first transfer is used i e transmission and reception are performed startin...

Page 263: ...neously with transmit data output When transmission ends the serial clock is not output until the start flag is next set to 1 During this interval the SO1 continuously outputs the last bit of the previous data While transmission is halted the output value of the SO1 can be changed by means of the SOL bit in SCSR1 Receiving The procedure for receiving data is as follows 1 Set both SI1 and SCK1 to 1...

Page 264: ...s output from the SO1 or receive data is input from the SI1 5 After transmission reception is completed IRRS1 is set to 1 in IRR1 6 Read the transfer data from SDRL SDRU 8 bit transfer mode SDRL 16 bit transfer mode Upper byte from SDRU lower byte from SDRL When an internal clock is used the serial clock is output from the SCK1 simultaneously with transmit data output When transmission ends the se...

Page 265: ...the end of serial transfer Do not read or write to SCSR1 during serial transfer The following two methods can be used to confirm the end of serial transfer a Using SCI1 interrupt exception handling Set the IENS1 bit to 1 in IENR1 and execute interrupt exception handling b Performing IRR1 polling With SCI1 interrupts disabled IENS1 0 in IENR1 confirm that the IRRS1 bit in IRR1 has been set to 1 ...

Page 266: ...us mode for serial data communication Asynchronous mode Serial data communication is performed asynchronously with synchronization provided character by character In this mode serial data can be exchanged with standard asynchronous communication LSIs such as a Universal Asynchronous Receiver Transmitter UART or Asynchronous Communication Interface Adapter ACIA A multiprocessor communication functi...

Page 267: ...sion and reception units are provided enabling transmission and reception to be carried out simultaneously The transmission and reception units are both double buffered allowing continuous transmission and reception On chip baud rate generator allowing any desired bit rate to be selected Choice of an internal or external clock as the transmit receive clock source Six interrupt sources transmit end...

Page 268: ...DR SMR SCR3 SSR BRR BRC SPCR Receive shift register Receive data register Transmit shift register Transmit data register Serial mode register Serial control register 3 Serial status register Bit rate register Bit rate counter Serial port control register Interrupt request TEI TXI RXI ERI 3x Internal clock ø 64 ø 16 øw 2 ø External clock BRC Baud rate generator Figure 10 3 SCI3 Block Diagram ...

Page 269: ...configuration Table 10 5 Registers Name Abbrev R W Initial Value Address Serial mode register SMR R W H 00 H FFA8 FF98 Bit rate register BRR R W H FF H FFA9 FF99 Serial control register 3 SCR3 R W H 00 H FFAA FF9A Transmit data register TDR R W H FF H FFAB FF9B Serial data register SSR R W H 84 H FFAC FF9C Receive data register RDR R H 00 H FFAD FF9D Transmit shift register TSR Protected Receive s...

Page 270: ...y by the CPU 2 Receive data register RDR Bit Initial value Read Write 7 RDR7 0 R 6 RDR6 0 R 5 RDR5 0 R 4 RDR4 0 R 3 RDR3 0 R 0 RDR0 0 R 2 RDR2 0 R 1 RDR1 0 R RDR is an 8 bit register that stores received serial data When reception of one byte of data is finished the received data is transferred from RSR to RDR and the receive operation is completed RSR is then able to receive data RSR and RDR are ...

Page 271: ...R if bit TDRE is set to 1 in the serial status register SSR TSR cannot be read or written directly by the CPU 4 Transmit data register TDR Bit Initial value Read Write 7 TDR7 1 R W 6 TDR6 1 R W 5 TDR5 1 R W 4 TDR4 1 R W 3 TDR3 1 R W 0 TDR0 1 R W 2 TDR2 1 R W 1 TDR1 1 R W TDR is an 8 bit register that stores transmit data When TSR is found to be empty the transmit data written in TDR is transferred...

Page 272: ...M Bit 7 selects whether SCI3 operates in asynchronous mode or synchronous mode Bit 7 COM Description 0 Asynchronous mode initial value 1 Synchronous mode Bit 6 Character length CHR Bit 6 selects either 7 or 8 bits as the data length to be used in asynchronous mode In synchronous mode the data length is always 8 bits irrespective of the bit 6 setting Bit 6 CHR Description 0 8 bit data 5 bit data 2 ...

Page 273: ...addition and checking The PM bit setting is only valid in asynchronous mode when bit PE is set to 1 enabling parity bit addition and checking The PM bit setting is invalid in synchronous mode and in asynchronous mode if parity bit addition and checking is disabled Bit 4 PM Description 0 Even parity 1 initial value 1 Odd parity 2 Notes 1 When even parity is selected a parity bit is added in transmi...

Page 274: ... of the STOP bit setting If the second stop bit is 1 it is treated as a stop bit but if 0 it is treated as the start bit of the next transmit character Bit 2 Multiprocessor mode MP Bit 2 enables or disables the multiprocessor communication function When the multiprocessor communication function is disabled the parity settings in the PE and PM bits are invalid The MP bit setting is only valid in as...

Page 275: ...and high speed mode 2 øW clock is selected in subactive or subsleep mode SCI3 can be used only when the øW 2 is selected as the CPU clock in subactive or subsleep mode 6 Serial control register 3 SCR3 Bit Initial value Read Write 7 TIE 0 R W 6 RIE 0 R W 5 TE 0 R W 4 RE 0 R W 3 MPIE 0 R W 0 CKE0 0 R W 2 TEIE 0 R W 1 CKE1 0 R W SCR3 is an 8 bit register for selecting transmit or receive operation th...

Page 276: ...atus register SSR is set to 1 There are three kinds of receive error overrun framing and parity RXI can be released by clearing bit RDRF or the FER PER or OER error flag to 0 or by clearing bit RIE to 0 Bit 6 RIE Description 0 Receive data full interrupt request RXI and receive error interrupt request ERI disabled initial value 1 Receive data full interrupt request RXI and receive error interrupt ...

Page 277: ...is only valid when asynchronous mode is selected and reception is carried out with bit MP in SMR set to 1 The MPIE bit setting is invalid when bit COM is set to 1 or bit MP is cleared to 0 Bit 3 MPIE Description 0 Multiprocessor interrupt request disabled normal receive operation Clearing conditions When data is received in which the multiprocessor bit is set to 1 initial value 1 Multiprocessor in...

Page 278: ...lock input pin The CKE0 bit setting is only valid in case of internal clock operation CKE1 0 in asynchronous mode In synchronous mode or when external clock operation is used CKE1 1 bit CKE0 should be cleared to 0 After setting bits CKE1 and CKE0 set the operating mode in the serial mode register SMR For details on clock source selection see table 10 4 in 10 1 3 Operation Bit 1 Bit 0 Description C...

Page 279: ...1 must first be read Bits TEND and MPBR are read only bits and cannot be modified SSR is initialized to H 84 upon reset and in standby module standby or watch mode Bit 7 Transmit data register empty TDRE Bit 7 indicates that transmit data has been transferred from TDR to TSR Bit 7 TDRE Description 0 Transmit data written in TDR has not been transferred to TSR Clearing conditions After reading TDRE...

Page 280: ...is completed while bit RDRF is still set to 1 an overrun error OER will result and the receive data will be lost Bit 5 Overrun error OER Bit 5 indicates that an overrun error has occurred during reception Bit 5 OER Description 0 Reception in progress or completed 1 Clearing conditions After reading OER 1 cleared by writing 0 to OER initial value 1 An overrun error has occurred during reception 2 S...

Page 281: ...ption cannot be continued with bit FER set to 1 In synchronous mode neither transmission nor reception is possible when bit FER is set to 1 Bit 3 Parity error PER Bit 3 indicates that a parity error has occurred during reception with parity added in asynchronous mode Bit 3 PER Description 0 Reception in progress or completed 1 Clearing conditions After reading PER 1 cleared by writing 0 to PER ini...

Page 282: ...uring multiprocessor format reception in asynchronous mode Bit 1 is a read only bit and cannot be modified Bit 1 MPBR Description 0 Data in which the multiprocessor bit is 0 has been received initial value 1 Data in which the multiprocessor bit is 1 has been received Note When bit RE is cleared to 0 in SCR3 with the multiprocessor format bit MPBR is not affected and retains its previous state Bit ...

Page 283: ...ndby or watch mode Table 10 6 shows examples of BRR settings in asynchronous mode The values shown are for active high speed mode Table 10 6 Examples of BRR Settings for Various Bit Rates Asynchronous Mode 1 OSC 32 8 kHz 38 4 kHz 2 MHz 2 4576 MHz 4 MHz Bit Rate bit s n N Error n N Error n N Error n N Error n N Error 110 Cannot be used 2 21 0 83 150 as error exceeds 0 3 0 2 12 0 16 3 3 0 2 25 0 16 ...

Page 284: ...00 Notes 1 The setting should be made so that the error is not more than 1 2 The value set in BRR is given by the following equation N OSC 64 22n B 1 where B Bit rate bit s N Baud rate generator BRR setting 0 N 255 OSC Value of øOSC Hz n Baud rate generator input clock number n 0 2 or 3 The relation between n and the clock is shown in table 10 7 3 The error in table 10 6 is the value obtained from...

Page 285: ... 2 is selected as the CPU clock in subactive or subsleep mode Table 10 8 shows the maximum bit rate for each frequency The values shown are for active high speed mode Table 10 8 Maximum Bit Rate for Each Frequency Asynchronous Mode Setting OSC MHz Maximum Bit Rate bit s n N 0 0384 600 0 0 2 31250 0 0 2 4576 38400 0 0 4 62500 0 0 10 156250 0 0 16 250000 0 0 Note When SMR is set up to CKS1 0 CKS0 1 ...

Page 286: ...ynchronous Mode 1 OSC 38 4 kHz 2 MHz 4 MHz Bit Rate bit s n N Error n N Error n N Error 200 0 23 0 250 2 124 0 300 2 0 0 500 1k 0 249 0 2 5k 0 99 0 0 199 0 5k 0 49 0 0 99 0 10k 0 24 0 0 49 0 25k 0 9 0 0 19 0 50k 0 4 0 0 9 0 100k 0 4 0 250k 0 0 0 0 1 0 500k 0 0 0 1M ...

Page 287: ...4 0 0 39 0 100k 0 19 0 250k 0 4 0 0 7 0 500k 0 3 0 1M 0 1 0 Blank Cannot be set A setting can be made but an error will result Continuous transmission reception is not possible Notes The value set in BRR is given by the following equation N OSC 8 22n B 1 where B Bit rate bit s N Baud rate generator BRR setting 0 N 255 OSC Value of øOSC Hz n Baud rate generator input clock number n 0 2 or 3 The rel...

Page 288: ... 1 øW 2 0 1 2 ø 16 1 0 3 ø 64 1 1 Notes 1 øW 2 clock is selected in active medium and high speed or sleep medium and high speed mode 2 øW clock is selected in subactive or subsleep mode SCI3 can be used only when the øW 2 is selected as the CPU operation clock in subactive or subsleep mode ...

Page 289: ...nt modules Bit 6 SCI31 module standby mode control S31CKSTP Bit 6 controls setting and clearing of module standby mode for SCI31 S31CKSTP Description 0 SCI31 is set to module standby mode 1 SCI31 module standby mode is cleared initial value Note Setting to module standby mode resets all the registers in SCI31 Bit 5 SCI32 module standby mode control S32CKSTP Bit 5 controls setting and clearing of m...

Page 290: ...ects whether pin P42 TXD32 is used as P42 or as TXD32 Bit 5 SPC32 Description 0 Functions as P42 I O pin initial value 1 Functions as TXD32 output pin Note Set the TE bit in SCR3 after setting this bit to 1 Bit 4 P35 TXD31 pin function switch SPC31 This bit selects whether pin P35 TXD31 is used as P35 or as TXD31 Bit 4 SPC31 Description 0 Functions as P35 I O pin initial value 1 Functions as TXD31...

Page 291: ...D31 pin output data inversion switch Bit 1 specifies whether or not TXD31 pin output data is to be inverted Bit 1 SCINV1 Description 0 TXD31 output data is not inverted initial value 1 TXD31 output data is inverted Bit 0 RXD31 pin input data inversion switch Bit 0 specifies whether or not RXD31 pin input data is to be inverted Bit 0 SCINV0 Description 0 RXD31 input data is not inverted initial val...

Page 292: ...the data transfer format and the character length Framing error FER parity error PER overrun error OER and break detection during reception Choice of internal or external clock as the clock source When internal clock is selected SCI3 operates on the baud rate generator clock and a clock with the same frequency as the bit rate can be output When external clock is selected A clock with a frequency 1...

Page 293: ...hronous 8 bit data No No 1 bit 0 0 0 0 1 mode 2 bits 0 0 0 1 0 Yes 1 bit 0 0 0 1 1 2 bits 0 1 0 0 0 7 bit data No 1 bit 0 1 0 0 1 2 bits 0 1 0 1 0 Yes 1 bit 0 1 0 1 1 2 bits 0 0 1 0 0 8 bit data Yes No 1 bit 0 0 1 0 1 2 bits 0 0 1 1 0 5 bit data No 1 bit 0 0 1 1 1 2 bits 0 1 1 0 0 7 bit data Yes 1 bit 0 1 1 0 1 2 bits 0 1 1 1 0 5 bit data No Yes 1 bit 0 1 1 1 1 2 bits 1 0 Synchronous mode 8 bit da...

Page 294: ...ce SCK3X Pin Function 0 0 0 Asynchronous Internal I O port SCK3X pin not used 0 0 1 mode Outputs clock with same frequency as bit rate 0 1 0 External Outputs clock with frequency 16 times bit rate 1 0 0 Synchronous Internal Outputs serial clock 1 1 0 mode External Inputs serial clock 0 1 1 Reserved Do not specify these combinations 1 0 1 1 1 1 ...

Page 295: ...til reception of the next RSR data is completed TXI TDRE TIE When TSR is found to be empty on completion of the previous transmission and the transmit data placed in TDR is transferred to TSR bit TDRE is set to 1 If bit TIE is set to 1 at this time TXI is enabled and an interrupt is requested See figure 10 4 b The TXI interrupt routine writes the next transmit data to TDR and clears bit TDRE to 0 ...

Page 296: ...nterrupt TDR next transmit data TSR transmission in progress TDRE 0 TXD3x pin TDR TSR transmission completed transfer TDRE 1 TXI request when TIE 1 TXD3x pin Figure 10 4 b TDRE Setting and TXI Interrupt TDR TSR transmission in progress TEND 0 TXD3x pin TDR TSR reception completed TEND 1 TEI request when TEIE 1 TXD3x pin Figure 10 4 c TEND Setting and TEI Interrupt ...

Page 297: ...haracter or frame 1 bit or none 1 or 2 bits Mark state 1 MSB LSB Figure 10 5 Data Format in Asynchronous Communication In asynchronous communication the communication line is normally in the mark state high level SCI3 monitors the communication line and when it detects a space low level identifies this as a start bit and begins serial data communication One transfer data character consists of a st...

Page 298: ...d Frame Length SMR STOP S 6 7 8 9 10 11 12 8 bit data S 7 bit data STOP STOP S STOP 7 bit data S STOP STOP 5 bit data S STOP 5 bit data S STOP STOP 8 bit data P S STOP 8 bit data P S STOP STOP 8 bit data MPB S STOP 8 bit data MPB S STOP STOP 7 bit data P STOP S STOP 7 bit data STOP S 5 bit data STOP P P P S 5 bit data STOP STOP S Notation S STOP P MPB Start bit Stop bit Parity bit Multiprocessor b...

Page 299: ... 6 1 character 1 frame 0 D0 D1 D2 D3 D4 D5 D6 D7 0 1 1 1 Clock Serial data Figure 10 6 Phase Relationship between Output Clock and Transfer Data Asynchronous Mode 8 bit data parity 2 stop bits c Data transfer operations SCI3 initialization Before data is transferred on SCI3 bits TE and RE in SCR3 must first be cleared to 0 and then SCI3 must be initialized as follows Note If the operation mode or ...

Page 300: ...its CKE1 and CKE0 If clock output is selected for reception in synchronous mode the clock is output immediately after bits CKE1 CKE0 and RE are set to 1 Set the data transfer format in the serial mode register SMR Write the value corresponding to the transfer rate in BRR This operation is not necessary when an external clock is selected Wait for at least one bit period then set bits TIE RIE MPIE a...

Page 301: ...and check that bit TDRE is set to 1 then write transmit data to the transmit data register TDR When data is written to TDR bit TDRE is cleared to 0 automatically After the TE bit is set to 1 one frame of 1s is output then transmission is possible When continuing data transmission be sure to read TDRE 1 to confirm that a write can be performed before writing data to TDR When data is written to TDR ...

Page 302: ...op bit has been sent starts transmission of the next frame If bit TDRE is set to 1 bit TEND in SSR bit is set to 1the mark state in which 1s are transmitted is established after the stop bit has been sent If bit TEIE in SCR3 is set to 1 at this time a TEI request is made Figure 10 9 shows an example of the operation when transmitting in asynchronous mode 1 frame Start bit Start bit Transmit data T...

Page 303: ...A Read bits OER PER and FER in the serial status register SSR to determine if there is an error If a receive error has occurred execute receive error processing Read SSR and check that bit RDRF is set to 1 If it is read the receive data in RDR When the RDR data is read bit RDRF is cleared to 0 automatically When continuing data reception finish reading of bit RDRF and RDR before receiving the stop...

Page 304: ...ssing If a receive error has occurred read bits OER PER and FER in SSR to identify the error and after carrying out the necessary error processing ensure that bits OER PER and FER are all cleared to 0 Reception cannot be resumed if any of these bits is set to 1 In the case of a framing error a break can be detected by reading the value of the RXD3x pin 4 Figure 10 10 Example of Data Reception Flow...

Page 305: ... is stored in RDR If bit RIE is set to 1 in SCR3 an RXI interrupt is requested If the error checks identify a receive error bit OER PER or FER is set to 1 depending on the kind of error Bit RDRF retains its state prior to receiving the data If bit RIE is set to 1 in SCR3 an ERI interrupt is requested Table 10 15 shows the conditions for detecting a receive error and receive data processing Note No...

Page 306: ...st in response to framing error Figure 10 11 Example of Operation when Receiving in Asynchronous Mode 8 bit data parity 1 stop bit 3 Operation in Synchronous Mode In synchronous mode SCI3 transmits and receives data in synchronization with clock pulses This mode is suitable for high speed serial communication SCI3 has separate transmission and reception units allowing full duplex communication wit...

Page 307: ...and ends with the MSB After output of the MSB the communication line retains the MSB state When receiving in synchronous mode SCI3 latches receive data at the rising edge of the serial clock The data transfer format uses a fixed 8 bit data length Parity and multiprocessor bits cannot be added b Clock Either an internal clock generated by the baud rate generator or an external clock input at the SC...

Page 308: ...ar bit TE to 0 in SCR3 No TDRE 1 Yes Continue data transmission No TEND 1 Yes Yes No Read the serial status register SSR and check that bit TDRE is set to 1 then write transmit data to the transmit data register TDR When data is written to TDR bit TDRE is cleared to 0 automatically the clock is output and data transmission is started When clock output is selected the clock is output and data trans...

Page 309: ...a from TDR to TSR and starts transmission of the next frame If bit TDRE is set to 1 SCI3 sets bit TEND to 1 in SSR and after sending the MSB bit 7 retains the MSB state If bit TEIE in SCR3 is set to 1 at this time a TEI request is made After transmission ends the SCK pin is fixed at the high level Note Transmission is not possible if an error flag OER FER or PER that indicates the data reception s...

Page 310: ... register SSR to determine if there is an error If an overrun error has occurred execute overrun error processing Read SSR and check that bit RDRF is set to 1 If it is read the receive data in RDR When the RDR data is read bit RDRF is cleared to 0 automatically When continuing data reception finish reading of bit RDRF and RDR before receiving the MSB bit 7 of the current frame When the data in RDR...

Page 311: ... set to 1 Bit RDRF remains set to 1 If bit RIE is set to 1 in SCR3 an ERI interrupt is requested See table 10 15 for the conditions for detecting a receive error and receive data processing Note No further receive operations are possible while a receive error flag is set Bits OER FER PER and RDRF must therefore be cleared to 0 before resuming reception Figure 10 16 shows an example of the operatio...

Page 312: ...bit RDRF and RDR before receiving the MSB bit 7 of the current frame Before receiving the MSB bit 7 of the current frame also read TDRE 1 to confirm that a write can be performed then write data to TDR When data is written to TDR bit TDRE is cleared to 0 automatically and when the data in RDR is read bit RDRF is cleared to 0 automatically If an overrun error has occurred read bit OER in SSR and af...

Page 313: ...o cycles are differentiated by means of the multiprocessor bit 1 indicating an ID transmission cycle and 0 a data transmission cycle The sender first sends transfer data with a 1 multiprocessor bit added to the ID code of the receiver it wants to communicate with and then sends transfer data with a 0 multiprocessor bit added to the transmit data When a receiver receives transfer data with the mult...

Page 314: ...n Using Multiprocessor Format Sending data H AA to receiver A There is a choice of four data transfer formats If a multiprocessor format is specified the parity bit specification is invalid See table 10 14 for details For details on the clock used in multiprocessor communication see 10 3 3 2 Operation in Asynchronous Mode Multiprocessor transmitting Figure 10 19 shows an example of a flowchart for...

Page 315: ...t bit MPBT in SSR to 0 or 1 and write transmit data to the transmit data register TDR When data is written to TDR bit TDRE is cleared to 0 automatically When continuing data transmission be sure to read TDRE 1 to confirm that a write can be performed before writing data to TDR When data is written to TDR bit TDRE is cleared to 0 automatically If a break is to be output when data transmission ends ...

Page 316: ... to 1 the mark state in which 1s are transmitted is established after the stop bit has been sent If bit TEIE in SCR3 is set to 1 at this time a TEI request is made Figure 10 20 shows an example of the operation when transmitting using the multiprocessor format 1 frame Start bit Start bit Transmit data Transmit data MPB MPB Stop bit Stop bit Mark state 1 frame 0 1 D0 D1 D7 0 1 1 1 1 0 D0 D1 D7 0 1 ...

Page 317: ...ing Read SSR and check that bit RDRF is set to 1 If it is read the receive data in RDR and compare it with this receiver s own ID If the ID is not this receiver s set bit MPIE to 1 again When the RDR data is read bit RDRF is cleared to 0 automatically Read SSR and check that bit RDRF is set to 1 then read the data in RDR If a receive error has occurred read bits OER and FER in SSR to identify the ...

Page 318: ... OER and FER to 0 in SSR Yes OER 1 Yes Yes FER 1 Break No No No Overrun error processing Framing error processing A Figure 10 21 Example of Multiprocessor Data Reception Flowchart cont Figure 10 22 shows an example of the operation when receiving using the multiprocessor format ...

Page 319: ...frame Start bit Start bit Receive data ID2 Receive data Data2 MPB MPB Stop bit Stop bit Mark state idle state 1 frame 0 1 D0 D1 D7 1 1 1 1 0 a When data does not match this receiver s ID b When data matches this receiver s ID D0 D1 D7 ID2 Data2 ID1 0 Serial data MPIE RDRF LSI operation RXI request MPIE cleared to 0 User processing RDRF cleared to 0 RXI request RDRF cleared to 0 RDR data read When ...

Page 320: ...nitial value of bit TDRE in SSR is 1 Therefore if the transmit data empty interrupt request TXI is enabled by setting bit TIE to 1 in SCR3 before transmit data is transferred to TDR a TXI interrupt will be requested even if the transmit data is not ready Also the initial value of bit TEND in SSR is 1 Therefore if the transmit end interrupt request TEI is enabled by setting bit TEIE to 1 in SCR3 be...

Page 321: ... 2 Operation when a number of receive errors occur simultaneously If a number of receive errors are detected simultaneously the status flags in SSR will be set to the states shown in table 10 17 If an overrun error is detected data transfer from RSR to RDR will not be performed and the receive data will be lost Table 10 17 SSR Status Flag States and Receive Data Transfer SSR Status Flags Receive D...

Page 322: ...functions as an I O port and 1 is output To detect a break clear bit TE to 0 after setting PCR 1 and PDR 0 When bit TE is cleared to 0 the transmission unit is initialized regardless of the current transmission state the TXD3X pin functions as an I O port and 0 is output from the TXD3X pin 5 Receive error flags and transmit operation synchronous mode only When a receive error flag OER PER or FER i...

Page 323: ...M 0 5 1 2N D 0 5 N L 0 5 F 5 100 Equation 1 where M Receive margin N Ratio of bit rate to clock N 16 D Clock duty D 0 5 to 1 0 L Frame length L 9 to 12 F Absolute value of clock frequency deviation Substituting 0 for F absolute value of clock frequency deviation and 0 5 for D clock duty in equation 1 a receive margin of 46 875 is given by equation 2 When D 0 5 and F 0 M 0 5 1 2 16 100 46 875 Equat...

Page 324: ...n line RDRF RDR Frame 1 Frame 2 Frame 3 Data 1 Data 1 RDR read RDR read Data 1 is read at point A Data 2 Data 3 Data 2 A Data 2 is read at point B B Figure 10 24 Relation between RDR Read Timing and Data In this case only a single RDR read operation not two or more should be performed after first checking that bit RDRF is set to 1 If two or more reads are performed the data read the first time sho...

Page 325: ...set at 1 This means it cannot be used as an I O port Also to avoid intermediate potential from being applied to the SCK3X pin pull up the line connected to the SCK3X pin to VCC potential with a resistance or supply an output from other devices b When switching the SCK3X pin function from clock output to I O port When stopping signal transmission 1 Clear the bits TE and RE in SCR3 and set the CKE1 ...

Page 326: ...314 ...

Page 327: ...nalog input 11 1 1 Features The A D converter has the following features 10 bit resolution 8 input channels Conversion time approx 12 4 µs per channel at 5 MHz operation Built in sample and hold function Interrupt requested on completion of A D conversion A D conversion can be started by external trigger input Use of module standby mode enables this module to be placed in standby mode independentl...

Page 328: ...H ADRRL Control logic Com parator AN AN AN AN AN AN AN AN ADTRG AV AV CC SS Multiplexer Reference voltage IRRAD AVCC AVSS 0 1 2 3 4 5 6 7 Notation AMR ADSR ADRR IRRAD A D mode register A D start register A D result register A D conversion end interrupt request flag Figure 11 1 Block Diagram of the A D Converter ...

Page 329: ...t channel 3 Analog input 4 AN4 Input Analog input channel 4 Analog input 5 AN5 Input Analog input channel 5 Analog input 6 AN6 Input Analog input channel 6 Analog input 7 AN7 Input Analog input channel 7 External trigger input ADTRG Input External trigger input for starting A D conversion 11 1 4 Register Configuration Table 11 2 shows the A D converter register configuration Table 11 2 Register Co...

Page 330: ...ata are held in ADRRH and the lower 2 bits in ADRRL ADRRH and ADRRL can be read by the CPU at any time but the ADRRH and ADRRL values during A D conversion are not fixed After A D conversion is complete the conversion result is stored as 10 bit data and this data is held until the next conversion operation starts ADRRH and ADRRL are not cleared on reset 11 2 2 A D Mode Register AMR Bit Initial val...

Page 331: ...ger select TRGE Bit 6 enables or disables the start of A D conversion by external trigger input Bit 6 TRGE Description 0 Disables start of A D conversion by external trigger initial value 1 Enables start of A D conversion by rising or falling edge of external trigger at pin ADTRG Note The external trigger ADTRG edge is selected by bit INTEG4 of IEGR See 1 IRQ edge select register IEGR in 3 3 2 for...

Page 332: ...5 1 0 1 0 AN6 1 0 1 1 AN7 1 1 Reserved Don t care 11 2 3 A D Start Register ADSR Bit Initial value Read Write 7 ADSF 0 R W 6 1 5 1 4 1 3 1 0 1 2 1 1 1 The A D start register ADSR is an 8 bit read write register for starting and stopping A D conversion A D conversion is started by writing 1 to the A D start flag ADSF or by input of the designated edge of the external trigger signal which also sets ...

Page 333: ...STP TACKSTP S31CKSTP S32CKSTP ADCKSTP TGCKSTP 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 R W R W R W R W R W R W R W R W Bit Initial value Read Write CKSTPR1 is an 8 bit read write register that performs module standby mode control for peripheral modules Only the bit relating to the A D converter is described here For details of the other bits see the sections on the relevant modules Bit 4 A D converter modu...

Page 334: ...on time or input channel needs to be changed in the A D mode register AMR during A D conversion bit ADSF should first be cleared to 0 stopping the conversion operation in order to avoid malfunction 11 3 2 Start of A D Conversion by External Trigger Input The A D converter can be made to start A D conversion by input of an external trigger signal External trigger input is enabled at pin ADTRG when ...

Page 335: ...isabled by means of bit IENAD in interrupt enable register 2 IENR2 For further details see 3 3 Interrupts 11 5 Typical Use An example of how the A D converter can be used is given below using channel 1 pin AN1 as the analog input channel Figure 11 3 shows the operation timing 1 Bits CH3 to CH0 of the A D mode register AMR are set to 0101 making pin AN1 the analog input channel A D interrupts are e...

Page 336: ...ocedures for using the A D converter Idle A D conversion 1 Idle A D conversion 2 Idle Interrupt IRRAD IENAD ADSF Channel 1 AN1 operation state ADRRH ADRRL Set Set Set Read conversion result Read conversion result A D conversion result 1 A D conversion result 2 A D conversion starts Note indicates instruction execution by software Figure 11 3 Typical A D Converter Operation Timing ...

Page 337: ... and input channel Perform A D conversion End Yes No Disable A D conversion end interrupt Start A D conversion ADSF 0 No Yes Read ADSR Read ADRRH ADRRL data Figure 11 4 Flow Chart of Procedure for Using A D Converter Polling by Software ...

Page 338: ... Enable A D conversion end interrupt Start A D conversion A D conversion end interrupt Yes No End Yes No Clear bit IRRAD to 0 in IRR2 Read ADRRH ADRRL data Perform A D conversion Figure 11 5 Flow Chart of Procedure for Using A D Converter Interrupts Used ...

Page 339: ... A D conversion is started after clearing module standby mode wait for 10 ø clock cycles before starting In active mode and sleep mode the analog power supply current AISTOP1 flows in the ladder resistance even when the A D converter is on standby Therefore if the A D converter is not used it is recommended that AVCC be connected to the system power supply and the ADCKSTP A D converter module stan...

Page 340: ...328 ...

Page 341: ...ing Any phase or single phase decoding Uses standard Serial Peripheral Interface SPI in slave mode Allows low current STOP mode operation of host processor Highly programmable receiver control Real time clock time base FLEX fragmentation and group messaging support Real time clock over the air update support Compatible with synthesized receivers SSID and NID Roaming support Low Battery Indication ...

Page 342: ... use the internal demodulator the FLEX decoder connects to a receiver capable of generating a limited i e 1 bit digitized 455 kHz or 140 kHz IF signal In this mode the FLEX decoder has 7 receiver control lines used for warming up and shutting down a receiver in stages The FLEX decoder has the ability to detect a low battery signal during the receiver control sequences It interfaces to a host MCU t...

Page 343: ...capable of converting a 4 level audio signal into a 2 bit digital signal In this mode the FLEX decoder has 8 receiver control lines used for warming up and shutting down a receiver in stages It also includes configuration settings for the two post detection filter bandwidths required to decode the two symbol rates of the FLEX signal Also when using an external demodulator the oscillator or externa...

Page 344: ...or Clock Generator Receiver Control Demodulator Data Slicer Symbol Sync Sync Correlator De interleaver Address Comparator Correlator Error Corrector Noise Detector Local Message Filter SPI Buffer SPI Control Status Registers External Control Unit Internal Control Unit EXTS0 EXTS1 SYMCLK øDEC CLKOUT Figure 12 3 Block Diagram ...

Page 345: ...mmunication are specified in 12 6 1 SPI Timing 12 2 1 Packet Communication Initiated by the Host Refer to figure 12 4 When the host sends a packet to the FLEX decoder it performs the following steps 1 Select the FLEX decoder by driving the SS pin low 2 Wait for the FLEX decoder to drive the READY pin low 3 Send the 32 bit packet 4 De select the FLEX decoder by driving the SS pin high 5 Repeat step...

Page 346: ...t de selects the FLEX decoder by driving the SS pin high optional SS READY SCK MOSI MISO 2 1 3 4 D31 D1 D0 D31 D1 D0 D31 D1 D0 D31 D1 D0 D31 D1 D0 D31 D1 D0 High impedance state Figure 12 5 Typical Multiple Packet Communications Initiated by the FLEX decoder When the host is reading a packet from the FLEX decoder it must send a valid packet to the FLEX decoder If the host has no data to send it is...

Page 347: ...335 SS READY SCK MOSI MISO D31 D1 D0 D31 D1 D0 D31 D1 D0 D31 D1 D0 D31 D1 D0 D31 D1 D0 High impedance state Figure 12 6 Multiple Packet Communications Initiated by the FLEX decoder with No De select ...

Page 348: ...tting 12 Receiver Control Configuration Warm Up 2 Setting 13 Receiver Control Configuration Warm Up 3 Setting 14 Receiver Control Configuration Warm Up 4 Setting 15 Receiver Control Configuration Warm Up 5 Setting 16 Receiver Control Configuration 3200sps Sync Setting 17 Receiver Control Configuration 1600sps Sync Setting 18 Receiver Control Configuration 3200sps Data Setting 19 Receiver Control C...

Page 349: ...3 User Address Assignment User address 3 84 User Address Assignment User address 4 85 User Address Assignment User address 5 86 User Address Assignment User address 6 87 User Address Assignment User address 7 88 User Address Assignment User address 8 89 User Address Assignment User address 9 8A User Address Assignment User address 10 8B User Address Assignment User address 11 8C User Address Assig...

Page 350: ...der exclusive or s the 24 data bits of every packet it receives except the Checksum Packet and the special packet ID s 1C through 1F hexadecimal with an internal checksum register Upon reset and whenever the host writes a packet to the FLEX decoder the FLEX decoder is disabled from sending any information to the host processor until the host processor sends a Checksum Packet with the proper checks...

Page 351: ...bits When the host reads a packet out of the FLEX decoder but has no data to send the Checksum Packet should be sent so the FLEX decoder will not be disabled The data in the Checksum Packet could be a null packet 32 bit stream of all zeros since a Checksum Packet will not disable the FLEX decoder When the host re configures the FLEX decoder the FLEX decoder will be disabled from sending any packet...

Page 352: ...nitiates Part ID Packet Decoder waits for SPI packet from host Yes Yes Yes No No No Packet data matches checksum register data Decoder enables itself Decoder sets checksum register to the XOR of the packet data bits with the checksum register bits Checksum Packet Decoder enabled Figure 12 7 FLEX decoder Checksum Flow Chart ...

Page 353: ...lator Enable When this bit is set the internal demodulator is enabled and the clock frequency at øDEC is expected to be 160 kHz When this bit is cleared the internal demodulator is disabled and the clock frequency at øDEC is expected to be 76 8 kHz value after reset 0 OFD Oscillator Frequency Difference These bits describe the maximum difference in the frequency of the 76 8 kHz oscillator crystal ...

Page 354: ... after reset 0 The polarity of the EXTS0 and EXTS1 bits will be determined by the receiver design Signal Polarity SP1 SP0 EXTS1 EXTS0 0 0 Normal Normal 0 1 Normal Inverted 1 0 Inverted Normal 1 1 Inverted Inverted FSK Modulation SP 0 0 EXTS1 EXTS0 4800 Hz 1 0 1600 Hz 1 1 1600 Hz 0 1 4800 Hz 0 0 SME Synchronous Mode Enable When this bit is set a Status Packet will be automatically sent whenever the...

Page 355: ...llator until the IDE bit is set value after reset 0 LBP Low Battery Polarity This bit defines the polarity of the FLEX decoder s LOBAT pin The LB bit in the Status Packet is initialized to the inverse value of this bit when the FLEX decoder is turned on by setting the ON bit in the Control Packet When the FLEX decoder is turned on the first low battery update in the Status Packet will be sent to t...

Page 356: ...ul for acquiring transmitted time information or channel attributes e g Local ID value after reset 0 SPM Single Phase Mode When this bit is set the FLEX decoder will decode only one phase of the transmitted data When this bit is clear the FLEX decoder will decode all of the phases it receives A change to this bit while the FLEX decoder is on will not take affect until the next block 0 of the next ...

Page 357: ... these steps is specified below and is measured from the positive edge of the last clock of one packet to the positive edge of the last clock of the next packet The minimum time between steps 1 and 2 is 2ms or the programmed shut down time whichever is greater The programmed shut down time is the sum of all the of the times programmed in the used Receiver Shut Down Settings Packets There is no max...

Page 358: ...l Frame Mode Packet Bit Assignments Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Byte 3 0 0 0 0 0 0 1 1 Byte 2 DAF FAF 0 0 0 0 0 0 Byte 1 DTA15 DTA 14 DTA 13 DTA12 DTA11 DTA10 DTA9 DTA 8 Byte 0 DTA7 DTA 6 DTA 5 DTA 4 DTA 3 DTA 2 DTA 1 DTA 0 DAF Decrement All Frame counter Setting this bit decrements the all frame mode counter by one If a packet is sent with this bit clear the all frame mode cou...

Page 359: ... OAE 13 OAE 12 OAE 11 OAE 10 OAE 9 OAE 8 Byte 0 OAE 7 OAE 6 OAE 5 OAE 4 OAE 3 OAE 2 OAE 1 OAE 0 OAE Operator messaging Address Enable When a bit is set the corresponding operator messaging address is enabled When it is cleared the corresponding operator messaging address is disabled OAE0 through OAE15 corresponds to the hexadecimal operator messaging address values of 1F7810 through 1F781F respect...

Page 360: ...if the system collapse was 7 The FLEX decoder will not apply the received system collapse to the AF bits When this bit is set the received system collapse is reported to the host via SCU and RSC in the Roaming Status Packet This is so the host can modify the AF bits based on the system collapse of the channel This bit is set and cleared by the host value after reset 0 IS1 Invert EXTS1 Setting this...

Page 361: ...acket only enables errored and real time clock related block info words value after reset 0 SAS Start A word Search Setting this bit while in asynchronous battery save mode will cause the FLEX decoder to warm up the receiver and run an A word search If during the A word search the FLEX decoder finds sufficient FLEX signal it will enter synchronous mode and start decoding the frame If the A word se...

Page 362: ... 3 Bit 2 Bit 1 Bit 0 Byte 3 0 0 0 0 1 1 1 1 Byte 2 0 0 0 0 0 0 0 0 Byte 1 AST 7 AST 6 AST 5 AST 4 AST 3 AST 2 AST 1 AST 0 Byte 0 ABT 7 ABT 6 ABT 5 ABT 4 ABT 3 ABT 2 ABT 1 ABT 0 AST A word Search Time The value of these bits sets the A word search time for all asynchronous A word searches in units of 80ms e g value of 1 is 80ms value of 2 is 160ms etc If the value is 0 the FLEX decoder defaults to ...

Page 363: ...et 0 CLS Control Line Setting If the corresponding FRS bit was set in this packet these bits define what setting should be applied to the corresponding receiver control lines value after reset 0 12 3 9 Receiver Control Configuration Packets These packets allow the host to configure what setting is applied to the receiver control lines S0 S7 how long to apply the setting and when to read the value ...

Page 364: ...it 0 Byte 3 0 0 0 1 0 s2 s1 s0 Byte 2 SE 0 0 0 LBC 0 0 0 Byte 1 CLS 7 CLS 6 CLS 5 CLS 4 CLS 3 CLS 2 CLS 1 CLS0 Byte 0 0 ST 6 ST 5 ST 4 ST 3 ST 2 ST 1 ST 0 s Setting Number Receiver control setting for which this packet s values are to be applied The following truth table shows the names of each of the values for s that apply to this packet s2 s1 s0 Setting Name 0 0 1 Warm Up 1 0 1 0 Warm Up 2 0 1 ...

Page 365: ...bit is set the FLEX decoder will check the status of the LOBAT port just before leaving this receiver state value after reset 0 CLS Control Line Setting This is the value to be output on the receiver control lines S0 S7 for this receiver state value after reset 0 ST Step Time This is the time the FLEX decoder is to wait before expecting good signals on the EXTS1 and EXTS0 signals after warming up ...

Page 366: ... 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Byte 3 0 0 0 1 1 0 1 s Byte 2 SE 0 0 0 LBC 0 0 0 Byte 1 CLS 7 CLS 6 CLS 5 CLS 4 CLS 3 CLS 2 CLS 1 CLS0 Byte 0 0 0 ST 5 ST 4 ST 3 ST 2 ST 1 ST 0 s Setting Number Receiver control setting for which this packet s values are to be applied The following truth table shows the names of each of the values for s that apply to this packet s Setting Name 0 Shut Down 1 1 Shut ...

Page 367: ... bit in the Roaming Control Packet the FLEX decoder will not apply the received system collapse to the AF bits The host should set the AF bits for all frames that should be decoded on all channels For example if frames 0 and 64 should be decoded on one channel and frames 4 36 68 and 100 should be decoded on another channel all six of the corresponding AF bits should be set The host can then change...

Page 368: ...rds while the FLEX decoder is decoding FLEX signals the host must disable a user address word before changing it The ID of the User Address Enable Packet is 120 decimal Table 12 17 User Address Enable Packet Bit Assignments Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Byte 3 0 1 1 1 1 0 0 0 Byte 2 0 0 0 0 0 0 0 0 Byte 1 UAE15 UAE 14 UAE 13 UAE 12 UAE 11 UAE 10 UAE 9 UAE 8 Byte 0 UAE 7 UAE 6 UAE...

Page 369: ...yte 3 1 0 0 0 a3 a2 a1 a0 Byte 2 0 LA TOA A20 A19 A18 A17 A16 Byte 1 A15 A 14 A13 A12 A 11 A 10 A9 A8 Byte 0 A7 A 6 A 5 A 4 A 3 A 2 A 1 A 0 a User Address Word Number This specifies which address word is being configured A zero in this field corresponds to address index zero AI 0 in the Address Packet received from the FLEX decoder when an address is detected See 12 4 2 Address Packet for a descri...

Page 370: ... be sent If there is no receiver shutdown packet pending but there is a roaming status packet pending the roaming status packet will be sent If neither the receiver shutdown packet nor the roaming status packet is pending and there is data in the transmit buffer a packet from the transmit buffer will be sent Otherwise the FLEX decoder will send the Status Packet which is not buffered In the event ...

Page 371: ...ck information word to the host with the e bit setregardless of the value of the f field in the block information word The FLEX decoder does not support decoding of the vector and message words associated with the Data System Message block info word f 101 The ID of a Block Information Word Packet is 0 decimal Table 12 19 Block Information Word Packet Bit Assignments Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 B...

Page 372: ...l of the addresses in the frame If less than three bit errors are detected in a received address word and it matches an enabled address assigned to the FLEX decoder an Address Packet will be sent to the host processor The Address Packet contains assorted data about the address and its associated vector and message The ID of an Address Packet is 1 decimal Table 12 20 Address Packet Bit Assignments ...

Page 373: ...e Building for a message building example In this case the word number identified by b6 to b0 in the Vector Packet will indicate the message start of the second message word if the message is longer than 1 word There are several types of vectors 3 types of Numeric Vectors a Short Message Tone Only Vector a Hex Binary Vector an Alphanumeric Vector a Secure Message Vector and a Short Instruction Vec...

Page 374: ...ed information has been numbered by the service provider to indicate all messages have been properly received WN Word number of vector 2 87 decimal Describes the location of the vector word in the frame e Set if more than 2 bit errors are detected in the word if the check character calculation fails after error correction has been performed or if the vector value is determined to be invalid p Phas...

Page 375: ... bit in this packet is not set the decoder will send a Message Packet from the word location immediately following the Vector Packet Except for the short message on a non network address t 0 all message bits in the Message Packet are unused and should be ignored t1 t0 d1 1 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 Description 0 0 c3 c2 c1 c0 b3 b2 b1 b0 a3 a2 a1 a0 Short Numeric 3 numeric chars 1 when on ...

Page 376: ...rors are detected in the word if the check character calculation fails after error correction has been performed or if the vector value is determined to be invalid p Phase on which the vector was found 0 a 1 b 2 c 3 d n Number of message words in this frame including the first Message word that immediately follows a long address vector Valid values are 1 through 85 decimal b Word number of message...

Page 377: ...d a Message Packet immediately following the Vector Packet All message bits in the message packet are unused and should be ignored for all modes except the Temporary address assignment with MSN i2 i1 i0 010 i2 i1 I0 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 Description 0 0 0 a3 a2 a1 a0 f6 f5 f4 f3 f2 f1 f0 Temporary address assignment 1 0 0 1 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 11 Event Flags for System Ev...

Page 378: ...it 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Byte 3 0 WN 6 WN5 WN4 WN3 WN 2 WN1 WN 0 Byte 2 e p1 p0 i 20 i 19 i 18 i 17 i 16 Byte 1 i 15 i 14 i 13 i 12 i 11 i 10 i 9 i 8 Byte 0 i 7 i 6 i5 i 4 i 3 i 2 i1 i 0 WN Word number of message word 3 87 decimal Describes the location of the message word in the frame e Set if more than 2 bit errors are detected in the word p Phase on which the message word was found 0 ...

Page 379: ...cond synchronization pattern C C of a frame and FLEX decoder was configured to report missed frame information via the MFC bit in the roaming control packet This bit is cleared when read MBI Missed Block Information word 1 Set when at least one of the block information word ones is received with an uncorrectable number of errors and FLEX decoder was configured to report missed frame information vi...

Page 380: ...ol packet only the No FLEX signal detected result will be reported These bits are cleared when read NDR Noise Detect Result 00 No Information 01 Noise Detect was abandoned 10 FLEX signal detected 11 FLEX signal not detected SCU System Collapse Update Set when the FLEX decoder is configured for manual collapse mode by setting the MCM bit in the roaming control packet and the system collapse of a fr...

Page 381: ...line when this packet is sent to the host The value of this field is valid only if the FLEX decoder is in synchronous mode and the FIV bit in the status packet is set When in asynchronous mode this value will be 0 TNF Time to Next Frame When in synchronous mode TNF indicates the time to the start of the A word check if the FLEX decoder were to warm up for the next frame When in asynchronous mode T...

Page 382: ...LBU x MT x EOF EA BOE FIV Frame Info Valid Set when a valid frame info word has been received since becoming synchronous to the system and the f and c fields contain valid values If this bit is clear no valid frame info words have been received since the FLEX decoder became synchronous to the system This value will change from 0 to 1 at the end of block 0 of the frame in which the 1st frame info w...

Page 383: ...his bit is initialized to 0 when the FLEX decoder is reset LBU Low Battery Update Set if the value on two consecutive reads of the LOBAT pin yielded different results Cleared when read The host controls when the LOBAT pin is read via the Receiver Control Packets Changes in the LB bit due to turning on the FLEX decoder will not cause the LBU bit to be set This bit is initialized to 0 when the FLEX ...

Page 384: ...6 REV 5 REV 4 REV 3 REV 2 REV 1 REV 0 MDL Model This identifies the FLEX decoder model Current value is 0 CID Compatibility ID This value describes the FLEX decoders to which this part is backwards compatible See table below for meaning and current value Bit Indicates this IC can be used in place of Value for FLEXTM Roaming Decoder II CID0 FLEX Alphanumeric Decoder I 1 1 TRUE CID1 FLEX Roaming Dec...

Page 385: ...la Semiconductor Products Sector 00 01 08 FLEX Alphanumeric Decoder II Texas Instruments 00 03 03 FLEX Roaming Decoder I Motorola Semiconductor Products Sector 00 03 05 FLEX Roaming Decoder I Texas Instruments 00 03 09 FLEX Roaming Decoder II Motorola Semiconductor Products Sector 00 03 0A FLEX Roaming Decoder II Texas Instruments 00 04 01 FLEX Numeric Decoder Texas Instruments 00 01 15 FLEX Alpha...

Page 386: ...he FLEX decoder is turned on by setting the ON bit in the Control Packet This allows the designer to force the receiver control lines to the receiver off setting with external pull up or pull down resistors before the host can configure these settings in the FLEX decoder When the FLEX decoder is turned on the receiver control ports are driven to the settings configured by the 12 3 9 Receiver Contr...

Page 387: ...se to a host request the first warm up setting if enabled is applied to the receiver control lines for the amount of time programmed for that setting Each subsequent warm up setting is applied to the receiver control lines for their corresponding time until a disabled warm up setting is found Once a disabled warm up setting is found the 3200sps Sync Setting for ON and SND warm ups or the 1600sps S...

Page 388: ...l complete the shut down sequence before starting the warm up sequence Shut Down Setting 1 Shut Down Time 2 RECEIVER CONTROL LINE SETTING 1600sps or 3200sps Sync or Data Setting Shut Down Setting 2 Off Possible LOBAT Check Possible LOBAT Check Possible LOBAT Check Shut Down Time 1 Figure 12 11 Receiver Shut Down Sequence 5 Miscellaneous Receiver States In addition to the warm up and shut down stat...

Page 389: ... FLEX decoder changes the receiver control lines from that setting to another setting The FLEX decoder will send a Status Packet whenever the value on two consecutive reads of the LOBAT pin yields different results 12 5 2 Message Building A simple message consists of an Address Packet followed by a Vector Packet indicating the word numbers of associated Message Packets The tables below show a more...

Page 390: ...1 6 LONG ADDRESS 3 WORD 2 7 VECTOR 1 1 8 VECTOR 2 9 MESSAGE 1 1 10 MESSAGE 1 2 VECTOR 3 11 MESSAGE 1 3 MESSAGE 3 1 12 MESSAGE 2 1 13 MESSAGE 2 2 14 MESSAGE 2 3 MESSAGE 3 2 15 MESSAGE 2 4 MESSAGE 3 3 Table 12 31 shows the sequence of packets received by the host The FLEX decoder processes the FLEX signal one block at a time and one phase at a time Thus the address and vector information in block 0 ...

Page 391: ...formation for Address 2 13th MESSAGE A 14 Message information for Address 2 14th MESSAGE A 15 Message information for Address 2 15th VECTOR C 10 Vector for Long Address 3 Message Words located at WN 14 15 phase C 16th MESSAGE C 11 Second word of Long Vector is first message information word of Address 3 17th MESSAGE C 14 Message information for Address 3 18th MESSAGE C 15 Message information for A...

Page 392: ...ide based on the Message Packet to return to normal decoding operation If the message is indicated as fragmented by the Message Continued Flag C being set in the Message Packet then the host does not decrement the all frame mode counter at this time The host decrements the counter if the Message Continued Flag C is clear by writing the All Frame Mode Packet to the FLEX decoder with the DAF bit 1 I...

Page 393: ... of fragmented messages being decoded and insure the all frame mode counter decrements after each fragment or after each fragmented message Table 12 32 Alphanumeric Message without fragmentation PACKET PACKET TYPE PHASE All Frame Counter COMMENT 1st ADDRESS 1 A 0 Address 1 is received 2nd VECTOR 1 A 1 Vector Alphanumeric Type 3rd MESSAGE A 1 Message Word received C bit 0 No more fragments are expe...

Page 394: ...h Variable 0 Host writes All Frame Mode Packet to the FLEX decoder with the DAF bit 1 Note Host Initiated Packet The FLEX decoder returns a packet according to 12 4 Decoder to Host Packet Descriptions 12 5 4 Operation of a Temporary Address 1 Group Messaging The FLEX protocol allows for a dynamic group call for the purpose of sending a common message to a group of paging devices The dynamic group ...

Page 395: ...frames and passes any address infor mation vector information and message information to the host followed by a status packet indicating the end of each frame and the current frame number There are several scenarios which may occur with temporary addresses 1 The temporary address is not found in the any of the assigned frames and therefore the host must terminate the temporary address mode by send...

Page 396: ...lete any host initiated tasks e g by setting SND or SAS in the roaming control packet The formula s for calculating these times depend on whether the FLEX decoder is in synchronous mode or asynchronous mode SYNCHRONOUS MODE TimeToWarmUpStart TNF 80ms SkippedFrames 1874 375ms ReceiverOffTime 167 5ms TimeToTasksDisabled TNF 80ms SkippedFrames 1874 375ms 247 5ms ASYNCHRONOUS MODE TimeToWarmUpStart TN...

Page 397: ...t the DAS bit of the roaming control packet was set TimeToPerformNoiseDetect TotalWarmUpTime 82ms Where TotalWarmUpTime The sum of the times programmed for the used warm up steps plus the time programmed for the 3200sps Sync Setting in the receiver control configuration packets The following formula calculates how long it will take to complete an A word search initiated by setting the SAS bit in t...

Page 398: ...me The sum of the times programmed for the used warm up steps plus the time programmed for the 3200sps Sync Setting in the receiver control configuration packets AST The value configured using the timing control packet ...

Page 399: ... apply to this LSI and should be used only for reference 12 6 1 SPI Timing The following diagram and table describe the timing specifications of the SPI interface READY SCK Hi Z Hi Z D31 D31 D0 D0 MISO MOSI SS tRDY tLEAD1 tR tF tLAG2 tLAG1 tRH tRS tSSH tCYC tLEAD2 tSCKL tSCKH tV tAC tSU tHI tHO tDIS Figure 12 13 SPI Timing ...

Page 400: ...ess Time CL 50pf tAC 0 200 ns MISO Disable Time tDIS 300 ns MISO Data Valid Time CL 50pf tV 200 ns MISO Data Hold Time tHO 0 ns SS High Time tSSH 200 ns SCK High Time tSCKH 300 ns SCK Low Time tSCKL 300 ns SCK Rise Time 20 to 70 VDD tR 1 µs SCK Fall Time 20 to 70 VDD tF 1 µs Notes 1 The specifications given in this data sheet indicate the minimum performance level of all FLEX decoders regardless o...

Page 401: ... Oscillator Start up Time tSTART 5 sec RESET Hold Time tRESET 200 ns RESET High to READY Low tRHRL 76 800 76 800 T 2 Notes 1 The specifications given in this data sheet indicate the minimum performance level of all manufacturers of the FLEX decoder Individual manufacturers may have better performance than indicated 2 T is one period of the øDEC clock source Note that from power up the oscillator s...

Page 402: ... V TA 20ºC to 75ºC Characteristic Conditions Symbol Min 1 Max 1 Unit RESET Pulse Width tRL 200 ns RESET Low to READY High tRLRH 200 ns RESET High to READY Low tRHRL 76 800 76 800 T 2 Notes 1 The specifications given in this data sheet indicate the minimum performance level of all manufacturers of the FLEX decoder Individual manufacturers may have better performance than indicated 2 T is one period...

Page 403: ...o 7 0 V Programming voltage VPP 0 3 to 13 0 V Input voltage Ports other than Port B Vin 0 3 to VCC 0 3 V Port B AVin 0 3 to AVCC 0 3 V Operating temperature Topr 20 to 75 C Storage temperature Tstg 55 to 125 C Note Permanent damage may occur to the chip if maximum ratings are exceeded Normal operation should be under the conditions specified in Electrical Characteristics Exceeding these values can...

Page 404: ...eries and H8 3937R Series are indicated by the shaded region in the figures 1 Power supply voltage and oscillator frequency range 10 0 4 0 2 0 1 8 2 7 3 6 VCC V f osc MHz Active high speed mode Sleep high speed mode Note fosc is the frequency when an oscillator element or external clock is used All operating modes 160 76 8 1 8 3 6 VCC V f W kHz ...

Page 405: ...ep high speed mode except CPU Active medium speed mode except A D converter Sleep medium speed mode except A D converter Subactive mode Subsleep mode except CPU Watch mode except CPU 3 Analog power supply voltage and A D converter operating range 5 0 1 0 1 8 2 7 3 6 AVCC V ø MHz 625 500 1 8 3 6 AVCC V ø kHz 2 7 Active medium speed mode Sleep medium speed mode Active high speed mode Sleep high spee...

Page 406: ...VCC VCC 0 3 V OSC1 0 9 VCC VCC 0 3 V DX1 0 9 VCC VCC 0 3 V P10 to P17 P30 to P37 P40 to P42 P50 to P57 P60 to P67 P70 to P77 P80 to P87 P90 to P93 PA0 to PA3 0 8 VCC VCC 0 3 V PB0 to PB7 0 8 VCC AVCC 0 3 V IFIN 0 9 VCC VCC 0 3 V EXTS0 EXTS1 LOBAT 0 8 VCC VCC 0 3 V Input low voltage VIL RES WKP0 to WKP7 IRQ1 to IRQ4 TMIC TMIF TMIG SCK31 SCK32 ADTRG 0 3 0 1 VCC V RXD31 RXD32 UD 0 3 0 2 VCC V OSC1 0 ...

Page 407: ...PA3 0 5 V IOL 0 4 mA CLKOUT 0 5 V VCC 2 5 V to 3 6 V IOL 1 5 mA 0 5 V IOL 1 0 mA SYMCLK S0 to S7 0 5 V VCC 2 5 V to 3 6 V IOL 0 4 mA 0 3 V IOL 0 1 mA Input IIL RES 20 0 µA VIN 0 5 V to 2 output 1 0 VCC 0 5 V 1 leak age current OSC1 DX1 P10 to P17 P30 to P37 P40 to P42 P50 to P57 P60 to P67 P70 to P77 P80 to P87 P90 to P93 PA0 to PA3 1 0 µA VIN 0 5 V to VCC 0 5 V PB0 to PB7 1 0 VIN 0 5 V to AVCC 0 ...

Page 408: ...leep mode current dissi pation ISLEEP VCC 0 45 mA VCC 3 V fOSC 2 MHz 3 4 Refer ence value Sub active mode current dissi pation ISUB VCC 56 µA VCC 2 7 V 160 kHz crystal oscillator øSUB øW 2 3 4 Refer ence value Sub sleep mode current dissi pation ISUBSP VCC 30 µA VCC 2 7 V 160 kHz crystal oscillator øSUB øW 2 3 4 Refer ence value Watch mode current dissi pation IWATCH VCC 18 µA VCC 2 7 V 160 kHz cr...

Page 409: ...3 Pin states during current measurement Pin States during Current Dissipation Measurement Mode RES Pin Internal State Other Pins Oscillator Pins Active high speed mode VCC Only CPU Operates decoder stops VCC System clock oscillator Crystal Active medium speed mode Subclock oscillator PinDX1 GND Sleep mode VCC Only timers operate decoder stops VCC Subactive mode VCC Only CPU Operates decoder stops ...

Page 410: ...ycle time tOSC OSC1 OSC2 100 500 ns VCC 2 7 V to 3 6 V Figure 13 1 250 500 VCC 1 8 V to 3 6 V System clock ø tcyc 2 128 tOSC cycle time 208 3 µs Subclock oscilla tion frequency fW DX1 DX2 76 8 or 160 kHz Watch clock øW cycle time tW DX1 DX2 26 0 or 12 5 µs Figure 13 1 Subclock øSUB cycle time tsubcyc 2 8 tW Instruction cycle time 2 tcyc tsubcyc Oscillation stabilization time trc OSC1 OSC2 20 45 µs...

Page 411: ... Figure 13 1 fall time 25 VCC 1 8 V to 3 6 V DX1 55 0 ns Figure 13 1 Pin RES low width tREL RES 10 tcyc Figure 13 2 Input pin high width tIH IRQ1 to IRQ4 WKP0 to WKP7 ADTRG TMIC TMIF TMIG 2 tcyc tsubcyc Figure 13 3 Input pin low width tIL IRQ1 to IRQ4 WKP0 to WKP7 ADTRG TMIC TMIF TMIG 2 tcyc tsubcyc Figure 13 3 UD pin minimum modulation width tUDH tUDL UD 4 tcyc tsubcyc Figure 13 4 Note Selected w...

Page 412: ...nce Item Symbol Min Typ Max Unit Test Conditions Figure Input clock Asynchronous tScyc 4 tcyc or Figure 13 5 cycle Synchronous 6 tsubcyc Input clock pulse width tSCKW 0 4 0 6 tScyc Figure 13 5 Transmit data delay time synchronous tTXD 1 tcyc or tsubcyc Figure 13 6 Receive data setup time synchronous tRXS 400 0 ns Figure 13 6 Receive data hold time synchronous tRXH 400 0 ns Figure 13 6 ...

Page 413: ...3 Analog input capacitance CAIN AN0 to AN7 15 0 pF Allowable signal source impedance RAIN 10 0 kΩ Resolution data length 10 bit Nonlinearity error 2 5 LSB AVCC 3 0 to 3 6 V VCC 3 0 to 3 6 V 5 5 AVCC 2 0 to 3 6 V VCC 2 0 to 3 6 V 7 5 Except the above 4 Quantization error 0 5 LSB Absolute accuracy 3 0 LSB AVCC 3 0 to 3 6 V VCC 3 0 to 3 6 V 6 0 AVCC 2 0 to 3 6 V VCC 2 0 to 3 6 V 8 0 Except the above ...

Page 414: ...3 1 to 13 7 show timing diagrams t tw OSC VIH VIL tCPH tCPL tCPr OSC1 Dx1 tCPf Figure 13 1 Clock Input Timing RES VIL tREL Figure 13 2 RES Low Width VIH VIL tIL IRQ1 to IRQ4 WKP0 to WKP7 ADTRG TMIC TMIF TMIG tIH Figure 13 3 Input Timing ...

Page 415: ...403 VIL VIH tUDL UD tUDH Figure 13 4 UD Pin Minimum Modulation Width Timing tscyc 31 tSCKW SCK 32 SCK Figure 13 5 SCK3 Input Clock Timing ...

Page 416: ...L OL VOL OH CC OL SCK 31 SCK TXD31 TXD32 transmit data RXD31 RXD32 receive data Note Output timing reference levels Output high Output low Load conditions are shown in figure 13 7 V 1 2 V 0 2 V V 0 8 V Figure 13 6 SCI3 Synchronous Mode Input Output Timing ...

Page 417: ...e 13 7 Output Load Condition 13 5 Resonator Equivalent Circuit CS CO Crystal Resonator Parameter RS OSC2 OSC1 LS Ceramic Resonator Parameters Frequency MHz RS max CO max 4 193 100 Ω 16 pF Frequency MHz RS max CO max 4 8 8 Ω 36 pF Figure 13 8 Resonator Equivalent Circuit ...

Page 418: ...acteristic values operating margins noise margins and other properties may vary due to differences in manufacturing process on chip ROM layout patterns and so on When system evaluation testing is carried out using the ZTAT version the same evaluation testing should also be conducted for the mask ROM version when changing over to that version ...

Page 419: ...overflow flag in CCR C C carry flag in CCR PC Program counter SP Stack pointer xx 3 8 16 Immediate data 3 8 or 16 bits d 8 16 Displacement 8 or 16 bits aa 8 16 Absolute address 8 or 16 bits Addition Subtraction Multiplication Division Logical AND Logical OR Exclusive logical OR Move Logical complement Condition Code Notation Symbol Modified according to the instruction result Not fixed value not g...

Page 420: ...8 Rd8 2 0 4 MOV B aa 16 Rd B aa 16 Rd8 4 0 6 MOV B Rs Rd B Rs8 Rd16 2 0 4 MOV B Rs d 16 Rd B Rs8 d 16 Rd16 4 0 6 MOV B Rs Rd B Rd16 1 Rd16 Rs8 Rd16 2 0 6 MOV B Rs aa 8 B Rs8 aa 8 2 0 4 MOV B Rs aa 16 B Rs8 aa 16 4 0 6 MOV W xx 16 Rd W xx 16 Rd 4 0 4 MOV W Rs Rd W Rs16 Rd16 2 0 2 MOV W Rs Rd W Rs16 Rd16 2 0 4 MOV W d 16 Rs Rd W d 16 Rs16 Rd16 4 0 6 MOV W Rs Rd W Rs16 Rd16 Rs16 2 Rs16 2 0 6 MOV W aa...

Page 421: ... B Rd8 Rs8 Rd8 2 2 SUB W Rs Rd W Rd16 Rs16 Rd16 2 1 2 SUBX B xx 8 Rd B Rd8 xx 8 C Rd8 2 2 2 SUBX B Rs Rd B Rd8 Rs8 C Rd8 2 2 2 SUBS W 1 Rd W Rd16 1 Rd16 2 2 SUBS W 2 Rd W Rd16 2 Rd16 2 2 DEC B Rd B Rd8 1 Rd8 2 2 DAS B Rd B Rd8 decimal adjust Rd8 2 2 NEG B Rd B 0 Rd Rd 2 2 CMP B xx 8 Rd B Rd8 xx 8 2 2 CMP B Rs Rd B Rd8 Rs8 2 2 CMP W Rs Rd W Rd16 Rs16 2 1 2 MULXU B Rs Rd B Rd8 Rs8 Rd16 2 14 DIVXU B ...

Page 422: ... Rd B b7 b0 0 C 2 0 0 2 ROTXL B Rd B C b7 b0 2 0 2 ROTXR B Rd B C b7 b0 2 0 2 ROTL B Rd B C b7 b0 2 0 2 ROTR B Rd B C b7 b0 2 0 2 BSET xx 3 Rd B xx 3 of Rd8 1 2 2 BSET xx 3 Rd B xx 3 of Rd16 1 4 8 BSET xx 3 aa 8 B xx 3 of aa 8 1 4 8 BSET Rn Rd B Rn8 of Rd8 1 2 2 BSET Rn Rd B Rn8 of Rd16 1 4 8 BSET Rn aa 8 B Rn8 of aa 8 1 4 8 BCLR xx 3 Rd B xx 3 of Rd8 0 2 2 BCLR xx 3 Rd B xx 3 of Rd16 0 4 8 BCLR x...

Page 423: ...3 Rd B xx 3 of Rd8 Z 2 2 BTST xx 3 Rd B xx 3 of Rd16 Z 4 6 BTST xx 3 aa 8 B xx 3 of aa 8 Z 4 6 BTST Rn Rd B Rn8 of Rd8 Z 2 2 BTST Rn Rd B Rn8 of Rd16 Z 4 6 BTST Rn aa 8 B Rn8 of aa 8 Z 4 6 BLD xx 3 Rd B xx 3 of Rd8 C 2 2 BLD xx 3 Rd B xx 3 of Rd16 C 4 6 BLD xx 3 aa 8 B xx 3 of aa 8 C 4 6 BILD xx 3 Rd B xx 3 of Rd8 C 2 2 BILD xx 3 Rd B xx 3 of Rd16 C 4 6 BILD xx 3 aa 8 B xx 3 of aa 8 C 4 6 BST xx 3...

Page 424: ...B C xx 3 of Rd16 C 4 6 BIOR xx 3 aa 8 B C xx 3 of aa 8 C 4 6 BXOR xx 3 Rd B C xx 3 of Rd8 C 2 2 BXOR xx 3 Rd B C xx 3 of Rd16 C 4 6 BXOR xx 3 aa 8 B C xx 3 of aa 8 C 4 6 BIXOR xx 3 Rd B C xx 3 of Rd8 C 2 2 BIXOR xx 3 Rd B C xx 3 of Rd16 C 4 6 BIXOR xx 3 aa 8 B C xx 3 of aa 8 C 4 6 BRA d 8 BT d 8 PC PC d 8 2 4 BRN d 8 BF d 8 PC PC 2 2 4 BHI d 8 If condition C Z 0 2 4 BLS d 8 is true then C Z 1 2 4 ...

Page 425: ... JSR Rn SP 2 SP PC SP PC Rn16 2 6 JSR aa 16 SP 2 SP PC SP PC aa 16 4 8 JSR aa 8 SP 2 SP PC SP PC aa 8 2 8 RTS PC SP SP 2 SP 2 8 RTE CCR SP SP 2 SP PC SP SP 2 SP 2 10 SLEEP Transit to sleep mode 2 2 LDC xx 8 CCR B xx 8 CCR 2 2 LDC Rs CCR B Rs8 CCR 2 2 STC CCR Rd B CCR Rd8 2 2 ANDC xx 8 CCR B CCR xx 8 CCR 2 2 ORC xx 8 CCR B CCR xx 8 CCR 2 2 XORC xx 8 CCR B CCR xx 8 CCR 2 2 NOP PC PC 2 2 2 EEPMOV if ...

Page 426: ...lag is retained otherwise the flag is cleared to 0 3 Set to 1 if decimal adjustment produces a carry otherwise retains value prior to arithmetic operation 4 The number of states required for execution is 4n 9 n value of R4L 5 Set to 1 if the divisor is negative otherwise cleared to 0 6 Set to 1 if the divisor is zero otherwise cleared to 0 ...

Page 427: ...hows the operation codes contained in the first byte of the instruction code bits 15 to 8 of the first instruction word Instruction when first bit of byte 2 bit 7 of first instruction word is 0 Instruction when first bit of byte 2 bit 7 of first instruction word is 1 ...

Page 428: ...BLS BTST ROTXR ROTR ORC OR BCC RTS XORC XOR BCS BSR BOR BIOR BXOR BIXOR BAND BIAND ANDC AND BNE RTE LDC BEQ NOT NEG BLD BILD BST BIST ADD SUB BVC BVS MOV INC DEC BPL JMP ADDS SUBS BMI EEPMOV MOV CMP BGE BLT ADDX SUBX BGT JSR DAA DAS BLE MOV ADD ADDX CMP SUBX OR XOR AND MOV MOV Note Bit manipulation instructions The PUSH and POP instructions are identical in machine language to MOV instructions ...

Page 429: ...hip RAM is accessed BSET 0 FF00 From table A 4 I L 2 J K M N 0 From table A 3 SI 2 SL 2 Number of states required for execution 2 2 2 2 8 When instruction is fetched from on chip ROM branch address is read from on chip ROM and on chip RAM is used for stack area JSR 30 From table A 4 I 2 J K 1 L M N 0 From table A 3 SI SJ SK 2 Number of states required for execution 2 2 1 2 1 2 8 Table A 3 Number o...

Page 430: ... ADDS W 2 Rd 1 ADDX ADDX B xx 8 Rd 1 ADDX B Rs Rd 1 AND AND B xx 8 Rd 1 AND B Rs Rd 1 ANDC ANDC xx 8 CCR 1 BAND BAND xx 3 Rd 1 BAND xx 3 Rd 2 1 BAND xx 3 aa 8 2 1 Bcc BRA d 8 BT d 8 2 BRN d 8 BF d 8 2 BHI d 8 2 BLS d 8 2 BCC d 8 BHS d 8 2 BCS d 8 BLO d 8 2 BNE d 8 2 BEQ d 8 2 BVC d 8 2 BVS d 8 2 BPL d 8 2 BMI d 8 2 BGE d 8 2 BLT d 8 2 BGT d 8 2 BLE d 8 2 BCLR BCLR xx 3 Rd 1 BCLR xx 3 Rd 2 2 BCLR x...

Page 431: ...x 3 aa 8 2 1 BIST BIST xx 3 Rd 1 BIST xx 3 Rd 2 2 BIST xx 3 aa 8 2 2 BIXOR BIXOR xx 3 Rd 1 BIXOR xx 3 Rd 2 1 BIXOR xx 3 aa 8 2 1 BLD BLD xx 3 Rd 1 BLD xx 3 Rd 2 1 BLD xx 3 aa 8 2 1 BNOT BNOT xx 3 Rd 1 BNOT xx 3 Rd 2 2 BNOT xx 3 aa 8 2 2 BNOT Rn Rd 1 BNOT Rn Rd 2 2 BNOT Rn aa 8 2 2 BOR BOR xx 3 Rd 1 BOR xx 3 Rd 2 1 BOR xx 3 aa 8 2 1 BSET BSET xx 3 Rd 1 BSET xx 3 Rd 2 2 BSET xx 3 aa 8 2 2 BSET Rn Rd...

Page 432: ...CMP B xx 8 Rd 1 CMP B Rs Rd 1 CMP W Rs Rd 1 DAA DAA B Rd 1 DAS DAS B Rd 1 DEC DEC B Rd 1 DIVXU DIVXU B Rs Rd 1 12 EEPMOV EEPMOV 2 2n 2 1 INC INC B Rd 1 JMP JMP Rn 2 JMP aa 16 2 2 JMP aa 8 2 1 2 JSR JSR Rn 2 1 JSR aa 16 2 1 2 JSR aa 8 2 1 1 LDC LDC xx 8 CCR 1 LDC Rs CCR 1 MOV MOV B xx 8 Rd 1 MOV B Rs Rd 1 MOV B Rs Rd 1 1 MOV B d 16 Rs Rd 2 1 MOV B Rs Rd 1 1 2 MOV B aa 8 Rd 1 1 MOV B aa 16 Rd 2 1 MO...

Page 433: ... W Rs Rd 1 1 MOV W d 16 Rs Rd 2 1 MOV W Rs Rd 1 1 2 MOV W aa 16 Rd 2 1 MOV W Rs Rd 1 1 MOV W Rs d 16 Rd 2 1 MOV W Rs Rd 1 1 2 MOV W Rs aa 16 2 1 MULXU MULXU B Rs Rd 1 12 NEG NEG B Rd 1 NOP NOP 1 NOT NOT B Rd 1 OR OR B xx 8 Rd 1 OR B Rs Rd 1 ORC ORC xx 8 CCR 1 ROTL ROTL B Rd 1 ROTR ROTR B Rd 1 ROTXL ROTXL B Rd 1 ROTXR ROTXR B Rd 1 RTE RTE 2 2 2 RTS RTS 2 1 2 SHAL SHAL B Rd 1 SHAR SHAR B Rd 1 SHLL S...

Page 434: ... Byte Data Access L Word Data Access M Internal Operation N SUB SUB B Rs Rd 1 SUB W Rs Rd 1 SUB SUB B Rs Rd 1 SUB W Rs Rd 1 SUBS SUBS W 1 Rd 1 SUBS W 2 Rd 1 POP POP Rd 1 1 2 PUSH PUSH Rs 1 1 2 SUBX SUBX B xx 8 Rd 1 SUBX B Rs Rd 1 XOR XOR B xx 8 Rd 1 XOR B Rs Rd 1 XORC XORC xx 8 CCR 1 ...

Page 435: ...31 PER31 TEND31 MPBR31 MPBT31 H 9D RDR31 RDR317 RDR316 RDR315 RDR314 RDR313 RDR312 RDR311 RDR310 H 9E H 9F H A0 SCR1 SNC1 SNC0 MRKON LTCH CKS3 CKS2 CKS1 CKS0 SCI1 H A1 SCSR1 SOL ORER MTRF STF H A2 SDRU SDRU7 SDRU6 SDRU5 SDRU4 SDRU3 SDRU2 SDRU1 SDRU0 H A3 SDRL SDRL7 SDRL6 SDRL5 SDRL4 SDRL3 SDRL2 SDRL1 SDRL0 H A4 H A5 H A6 H A7 H A8 SMR32 COM32 CHR32 PE32 PM32 STOP32 MP32 CKS321 CKS320 SCI32 H A9 BR...

Page 436: ...RFL OCRFL7 OCRFL6 OCRFL5 OCRFL4 OCRFL3 OCRFL2 OCRFL1 OCRFL0 H BC TMG OVFH OVFL OVIE IIEGS CCLR1 CCLR0 CKS1 CKS0 Timer G H BD ICRGF ICRGF7 ICRGF6 ICRGF5 ICRGF4 ICRGF3 ICRGF2 ICRGF1 ICRGFO H BE ICRGR ICRGR7 ICRGR6 ICRGR5 ICRGR4 ICRGR3 ICRGR2 ICRGR1 ICRGRO H BF H C0 H C1 H C2 H C3 H C4 ADRRH ADR9 ADR8 ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 A D H C5 ADRRL ADR1 ADR0 converter H C6 AMR CKS TRGE CH3 CH2 CH1 CH0 H...

Page 437: ...R35 PCR34 PCR33 PCR32 PCR31 PCR30 H E7 PCR4 PCR42 PCR41 PCR40 H E8 PCR5 PCR57 PCR56 PCR55 PCR54 PCR53 PCR52 PCR51 PCR50 H E9 PCR6 PCR67 PCR66 PCR65 PCR64 PCR63 PCR62 PCR61 PCR60 H EA PCR7 PCR77 PCR76 PCR75 PCR74 PCR73 PCR72 PCR71 PCR70 H EB PCR8 PCR87 PCR86 PCR85 PCR84 PCR83 PCR82 PCR81 PCR80 H EC PCR9 PCR93 PCR92 PCR91 PCR90 H ED PCRA PCRA3 PCRA2 PCRA1 PCRA0 H EE H EF H F0 SYSCR1 SSBY STS2 STS1 S...

Page 438: ...W 5 TMC5 0 R W 3 1 0 TMC0 0 R W 2 TMC2 0 R W 1 TMC1 0 R W 4 1 Clock select 0 Internal clock Internal clock 0 0 1 Internal clock Internal clock 1 0 1 1 0 0 1 1 0 1 Internal clock Internal clock Internal clock External event TMIC ø 8192 ø 2048 ø 512 ø 64 ø 16 ø 4 ø 4 Rising or falling edge W Counter up down control TCC is an up counter TCC is a down counter 0 0 1 TCC up down control is determined by...

Page 439: ...1 0 R W 4 SPC31 0 R W RXD31 pin input data inversion switch 0 RXD31 input data is not inverted 1 RXD31 input data is inverted TXD31 pin output data inversion switch 0 TXD31 output data is not inverted 1 TXD31 output data is inverted RXD32 pin input data inversion switch 0 RXD32 input data is not inverted 1 RXD32 input data is inverted TXD32 pin output data inversion switch 0 TXD32 output data is n...

Page 440: ...428 CWOSR Subclock Output Select Register H 92 Timer A Bit Initial value Read Write 7 1 6 1 5 1 0 CWOS 0 R W 2 1 1 1 4 1 TMOW pin clock select 0 Clock output from TMA is output 1 øW is output 3 1 ...

Page 441: ... clock Multiprocessor mode 0 Multiprocessor communication function disabled 1 Multiprocessor communication function enabled Stop bit length 0 1 stop bit 1 2 stop bits Parity mode 0 Even parity 1 Odd parity Parity enable 0 Parity bit addition and checking disabled 1 Parity bit addition and checking enabled Character length 0 8 bit data 5 bit data 1 7 bit data 5 bit data Communication mode 0 Asynchr...

Page 442: ...rate register31 H 99 SCI31 Bit Initial value Read Write 7 BRR317 1 R W 6 BRR316 1 R W 5 BRR315 1 R W 4 BRR314 1 R W 3 BRR313 1 R W 0 BRR310 1 R W 2 BRR312 1 R W 1 BRR311 1 R W Serial transmit receive bit rate setting ...

Page 443: ...is received Transmit enable 0 Transmit operation disabled TXD pin is transmit data pin 1 Transmit operation enabled TXD pin is transmit data pin Receive enable 0 Receive operation disabled RXD pin is I O port 1 Receive operation enabled RXD pin is receive data pin Transmit end interrupt enable Clock enable 0 Bit 1 CKE311 0 0 1 1 Bit 0 CKE310 0 1 0 1 Communication Mode Asynchronous Synchronous Asyn...

Page 444: ... Transmit data register 31 H 9B SCI31 Bit Initial value Read Write 7 TDR317 1 R W 6 TDR316 1 R W 5 TDR315 1 R W 4 TDR314 1 R W 3 TDR313 1 R W 0 TDR310 1 R W 2 TDR312 1 R W 1 TDR311 1 R W Data for transfer to TSR ...

Page 445: ...After reading PER31 1 cleared by writing 0 to PER31 1 A parity error has occurred during reception Setting conditions Framing error 0 Reception in progress or completed normally Clearing conditions After reading FER31 1 cleared by writing 0 to FER31 1 A framing error has occurred during reception Setting conditions When the stop bit at the end of the receive data is checked for a value of 1 at com...

Page 446: ...434 RDR31 Receive data register 31 H F9D SCI31 Bit Initial value Read Write 7 RDR317 0 R 6 RDR316 0 R 5 RDR315 0 R 4 RDR314 0 R 3 RDR313 0 R 0 RDR310 0 R 2 RDR312 0 R 1 RDR311 0 R Serial receive data ...

Page 447: ...L select 0 HOLD TAIL is output 1 LATCH TAIL is output Tail mark control 0 Tail mark is not output synchronous mode 1 Tail mark is output SSB mode 0 8 bit synchronous mode 16 bit synchronous mode 1 0 1 0 1 Continuous clock output mode Reserved Clock select 2 to 0 Bit 2 CKS2 CKS1 CKS0 Bit 1 Bit 0 0 ø 1024 ø 256 1 1 0 ø 64 ø 32 1 ø 16 1 0 1 1 0 0 1 ø 8 0 0 0 0 0 1 0 ø 4 1 1 1 0 1 øW 4 ø 2 5 MHz 409 6...

Page 448: ...te Read Write Note Only a write of 0 for flag clearing is possible 0 Clearing conditions After reading ORER 1 cleared by writing 0 to ORER 1 Setting conditions When an external clock is used and the clock is input after transfer is completed 0 SO1 output level is low Changes SO1 output to low level SO1 output level is high Changes SO1 output to high level 1 Read Write Read Write Tail mark transmis...

Page 449: ...receive data storage 8 bit transfer mode Not used 16 bit transfer mode Upper 8 bits of data register SDRL Serial data register L H A3 SCI1 Bit Initial value Read Write 7 SDRL7 Undefined R W 6 SDRL6 Undefined R W 5 SDRL5 Undefined R W 4 SDRL4 Undefined R W 3 SDRL3 Undefined R W 0 SDRL0 Undefined R W 2 SDRL2 Undefined R W 1 SDRL1 Undefined R W Used for transmit data setting and receive data storage ...

Page 450: ... clock Multiprocessor mode 0 Multiprocessor communication function disabled 1 Multiprocessor communication function enabled Stop bit length 0 1 stop bit 1 2 stop bits Parity mode 0 Even parity 1 Odd parity Parity enable 0 Parity bit addition and checking disabled 1 Parity bit addition and checking enabled Character length 0 8 bit data 5 bit data 1 7 bit data 5 bit data Communication mode 0 Asynchr...

Page 451: ...ate register 32 H A9 SCI32 Bit Initial value Read Write 7 BRR327 1 R W 6 BRR326 1 R W 5 BRR325 1 R W 4 BRR324 1 R W 3 BRR323 1 R W 0 BRR3120 1 R W 2 BRR322 1 R W 1 BRR321 1 R W Serial transmit receive bit rate setting ...

Page 452: ...is received Transmit enable 0 Transmit operation disabled TXD pin is transmit data pin 1 Transmit operation enabled TXD pin is transmit data pin Receive enable 0 Receive operation disabled RXD pin is I O port 1 Receive operation enabled RXD pin is receive data pin Transmit end interrupt enable Clock enable 0 Bit 1 CKE321 0 0 1 1 Bit 0 CKE320 0 1 0 1 Communication Mode Asynchronous Synchronous Asyn...

Page 453: ... Transmit data register 32 H AB SCI32 Bit Initial value Read Write 7 TDR327 1 R W 6 TDR326 1 R W 5 TDR325 1 R W 4 TDR324 1 R W 3 TDR323 1 R W 0 TDR320 1 R W 2 TDR322 1 R W 1 TDR321 1 R W Data for transfer to TSR ...

Page 454: ... After reading PER32 1 cleared by writing 0 to PER32 1 A parity error has occurred during reception Setting conditions Framing error 0 Reception in progress or completed normally Clearing conditions After reading FER32 1 cleared by writing 0 to FER32 1 A framing error has occurred during reception Setting conditions When the stop bit at the end of the receive data is checked for a value of 1 at co...

Page 455: ...Clock output select 0 ø 32 ø 16 TMA1 0 1 TMA0 0 0 0 0 0 0 1 0 1 0 0 0 1 PSS PSS PSS PSS 1 0 1 0 0 1 0 0 1 0 1 0 1 1 1 1 PSW PSW PSW PSW 0 0 1 0 1 0 0 1 0 0 1 1 0 1 1 1 PSW and TCA are reset 1 0 1 0 1 1 0 1 1 0 1 1 1 1 1 Prescaler and Divider Ratio or Overflow Period ø 8192 ø 4096 ø 2048 ø 512 ø 256 ø 128 ø 32 ø 8 øW 32768 øW 16384 øW 8192 øW 1024 Interval timer Time base overflow period Function 0...

Page 456: ...444 TCA Timer counter A H B1 Timer A Bit Initial value Read Write 7 TCA7 0 R 6 TCA6 0 R 5 TCA5 0 R 4 TCA4 0 R 3 TCA3 0 R 0 TCA0 0 R 2 TCA2 0 R 1 TCA1 0 R Count value ...

Page 457: ...nabled Bit 0 is write protected 1 Watchdog timer on 0 Watchdog timer operation is disabled Watchdog timer operation is enabled 1 Bit 2 write inhibit 0 Bit 2 is write enabled Bit 2 is write protected 1 Timer control status register W write enable 0 Data cannot be written to bits 2 and 0 Data can be written to bits 2 and 0 1 Bit 4 write inhibit 0 Bit 4 is write enabled Bit 4 is write protected 1 Tim...

Page 458: ...load function select Clock select Internal clock Internal clock 0 1 Internal clock Internal clock 0 1 0 1 0 1 0 0 1 1 0 0 1 1 0 0 0 0 1 1 1 1 Internal clock Internal clock Internal clock External event TMIC Counting on rising or falling edge Don t care ø 8192 ø 2048 ø 512 ø 64 ø 16 ø 4 øw 4 0 Interval timer function selected 1 Auto reload function selected Counter up down control 0 TCC is an up co...

Page 459: ... R 0 TCC0 0 R 2 TCC2 0 R 1 TCC1 0 R Count value TLC Timer load register C H B5 Timer C Bit Initial value Read Write 7 TLC7 0 R W 6 TLC6 0 R W 5 TLC5 0 R W 4 TLC4 0 R W 3 TLC3 0 R W 0 TLC0 0 R W 2 TLC2 0 R W 1 TLC1 0 R W Reload value Note TLC is allocated to the same address as TCC In a write the value is written to TLC ...

Page 460: ...ble Internal clock ø 32 Internal clock ø 16 Internal clock ø 4 Internal clock øw 4 1 1 1 1 0 0 0 1 1 0 1 0 1 0 1 1 0 1 0 Toggle output level L 0 Low level 1 High level Toggle output level H 0 Low level 1 High level 3 TOLL 0 W Clock select H 0 overflow signal Not available Internal clock ø 32 Internal clock ø 16 Internal clock ø 4 Internal clock øw 4 16 bit mode counting on TCFL Don t care Don t ca...

Page 461: ...iting 0 to CMFL 1 Setting conditions Set when the TCFL value matches the OCRFL value Timer overflow flag L 0 Clearing conditions After reading OVFL 1 cleared by writing 0 to OVFL 1 Setting conditions Set when TCFL overflows from H FF to H 00 Counter clear H 0 16 bit mode TCF clearing by compare match is disabled 8 bit mode TCFH clearing by compare match is disabled 1 16 bit mode TCF clearing by co...

Page 462: ...lue Read Write 7 TCFL7 0 R W 6 TCFL6 0 R W 5 TCFL5 0 R W 4 TCFL4 0 R W 3 TCFL3 0 R W 0 TCFL0 0 R W 2 TCFL2 0 R W 1 TCFL1 0 R W Count value Note TCFH and TCFL can also be used as the upper and lower halves respectively of a 16 bit timer counter TCF OCRFH Output compare register FH H BA Timer F Bit Initial value Read Write 7 OCRFH7 1 R W 6 OCRFH6 1 R W 5 OCRFH5 1 R W 4 OCRFH4 1 R W 3 OCRFH3 1 R W 0 ...

Page 463: ...al value Read Write 7 OCRFL7 1 R W 6 OCRFL6 1 R W 5 OCRFL5 1 R W 4 OCRFL4 1 R W 3 OCRFL3 1 R W 0 OCRFL0 1 R W 2 OCRFL2 1 R W 1 OCRFL1 1 R W Note OCRFH and OCRFL can also be used as the upper and lower halves respectively of a 16 bit output compare register OCRF ...

Page 464: ...rrupt request is enabled 0 1 0 Clearing conditions After reading OVFH 1 cleared by writing 0 to OVFH 1 Setting conditions Set when TCG overflows from H FF to H 00 Note Bits 7 and 6 can only be written with 0 for flag clearing Timer overflow flag L 0 Clearing conditions After reading OVFL 1 cleared by writing 0 to OVFL 1 Setting conditions Set when TCG overflows from H FF to H 00 Input capture inte...

Page 465: ...RGF3 0 R 0 ICRGF0 0 R 2 ICRGF2 0 R 1 ICRGF1 0 R Store TCG value at falling edge of input capture signal ICRGR Input capture register GR H BE Timer G Bit Initial value Read Write 7 ICRGR7 0 R 6 ICRGR6 0 R 5 ICRGR5 0 R 4 ICRGR4 0 R 3 ICRGR3 0 R 0 ICRGR0 0 R 2 ICRGR2 0 R 1 ICRGR1 0 R Store TCG value at rising edge of input capture signal ...

Page 466: ... 1 1 0 0 External trigger select 0 Disables start of A D conversion by external trigger 1 Enables start of A D conversion by rising or falling edge of external trigger at pin ADTRG 5 1 4 AN5 AN6 AN7 1 1 1 1 0 0 0 1 1 1 0 1 Reserved 1 AN0 AN1 AN2 AN3 Clock select 62 ø Bit 7 0 Conversion Period CKS 31 ø 1 62 µs ø 1 MHz 31 µs 12 4 µs ø 5 MHz Conversion Time Note Operation is not guaranteed with a con...

Page 467: ...DR3 Undefined R 4 ADR6 Undefined R A D conversion result Bit Initial value Read Write ADRRL 7 ADR1 Undefined R 6 ADR0 Undefined R 5 3 0 2 1 4 A D conversion result ADSR A D start register H C7 A D converter Bit Initial value Read Write 7 ADSF 0 R W 6 1 5 1 4 1 3 1 0 1 2 1 1 1 A D status flag 0 1 Read Write Read Write Indicates completion of A D conversion Stops A D conversion Indicates A D convers...

Page 468: ...in P13 TMIG pin function switch 0 Functions as P13 I O pin 1 Functions as TMIG input pin P14 IRQ4 ADTRG pin function switch 0 Functions as P14 I O pin 1 Functions as IRQ4 ADTRG input pin P15 IRQ1 TMIC pin function switch 0 Functions as P15 I O pin 1 Functions as IRQ1 TMIC input pin P11 TMOFL pin function switch 0 Functions as P11 I O pin 1 Functions as TMOFL output pin P16 IRQ2 pin function switch...

Page 469: ...W 1 SI1 0 R W 5 POF1 0 R W P20 SCK1 function switch 0 Functions as P20 I O Functions as SCK1 I O 1 P22 SO1 function switch 0 Functions as P22 I O Functions as SO1 output 1 P21 SI1 function switch 0 Functions as P21 I O Functions as SI1 input 1 P22 SO1 function PMOS control 0 CMOS setting NMOS open drain setting 1 ...

Page 470: ...as IRQ0 input pin Watchdog timer switch 0 ø8192 1 P31 UD pin function switch 0 Functions as P31 I O pin 1 Functions as UD input pin TMIG noise canceler select 0 Noise cancellation function not used 1 Noise cancellation function used øw 4 PMR4 Port mode register 4 H CB I O port Bit Initial value Read Write 7 0 6 0 5 0 4 NMOD4 0 R W 3 NMOD3 0 R W 0 NMOD0 0 R W 2 NMOD2 0 R W 1 NMOD1 0 R W 0 CMOS sett...

Page 471: ...in function switch 1 Functions as WKPn input pin n 7 to 0 PDR1 Port data register 1 H D4 I O ports Bit Initial value Read Write 7 P1 0 R W 6 P1 0 R W 5 P1 0 R W 4 P1 0 R W 3 P1 0 R W 0 P1 0 R W 2 P1 0 R W 1 P1 0 R W 7 6 5 4 3 2 1 0 Data for port 1 pins PDR2 Port data register 2 H D5 I O ports Bit Initial value Read Write 7 0 6 0 5 0 4 P24 0 R W 3 P23 0 R W 0 P20 0 R W 2 P22 0 R W 1 P21 0 R W Data ...

Page 472: ...port 3 pins PDR4 Port data register 4 H D7 I O ports Bit Initial value Read Write 7 1 6 1 5 1 4 1 3 P4 1 R 0 P4 0 R W 2 P4 0 R W 1 P4 0 R W 3 0 2 1 Data for port pins P42 to P40 Reads P43 state PDR5 Port data register 5 H D8 I O ports Bit Initial value Read Write 7 P5 0 R W 6 P5 0 R W 5 P5 0 R W 4 P5 0 R W 3 P5 0 R W 0 P5 0 R W 2 P5 0 R W 1 P5 0 R W 3 0 2 1 4 5 6 7 Data for port 5 pins ...

Page 473: ... pins PDR7 Port data register 7 H DA I O ports Bit Initial value Read Write 7 P7 0 R W 6 P7 0 R W 5 P7 0 R W 4 P7 0 R W 3 P7 0 R W 0 P7 0 R W 2 P7 0 R W 1 P7 0 R W 3 2 1 0 4 5 6 7 Data for port 7 pins PDR8 Port data register 8 H DB I O ports Bit Initial value Read Write 7 P8 0 R W 6 P8 0 R W 5 P8 0 R W 4 P8 0 R W 3 P8 0 R W 0 P8 0 R W 2 P8 0 R W 1 P8 0 R W 3 0 2 1 4 5 6 7 Data for port 8 pins ...

Page 474: ... R W Data for port 9 pins PDRA Port data register A H DD I O ports Bit Initial value Read Write 7 1 6 1 5 1 4 1 3 PA 0 R W 0 PA 0 R W 2 PA 0 R W 1 PA 0 R W 3 0 2 1 Data for port A pins PDRB Port data register B H DE I O ports Bit Read Write 7 PB R 6 PB R 5 PB R 4 PB R 3 PB R 0 PB R 2 PB R 1 PB R 3 0 2 1 4 5 6 7 Read port B pin states ...

Page 475: ...rt specification Port 1 input pull up MOS control 0 Input pull up MOS is off 1 Input pull up MOS is on PUCR3 Port pull up control register 3 H E1 I O ports Bit Initial value Read Write 7 PUCR3 0 R W 6 PUCR3 0 R W 5 PUCR3 0 R W 4 PUCR3 0 R W 3 PUCR3 0 R W 0 PUCR3 0 R W 2 PUCR3 0 R W 1 PUCR3 0 R W 0 2 3 4 5 6 7 1 Note When the PCR3 specification is 0 input port specification Port 3 input pull up MOS...

Page 476: ... pull up control register 6 H E3 I O ports Bit Initial value Read Write 7 PUCR6 0 R W 6 PUCR6 0 R W 5 PUCR6 0 R W 4 PUCR6 0 R W 3 PUCR6 0 R W 0 PUCR6 0 R W 2 PUCR6 0 R W 1 PUCR6 0 R W 3 0 2 1 4 5 6 7 Note When the PCR6 specifications 0 input port specification Port 6 input pull up MOS control 0 Input pull up MOS is off 1 Input pull up MOS is on PCR1 Port control register 1 H E4 I O ports Bit Initi...

Page 477: ...Port control register 3 H E6 I O ports Bit Initial value Read Write 7 PCR3 0 W 6 PCR3 0 W 5 PCR3 0 W 4 PCR3 0 W 3 PCR3 0 W 0 PCR3 0 W 2 PCR3 0 W 1 PCR3 0 W Port 3 input output select 0 Input pin 1 Output pin 0 2 3 4 5 6 7 1 PCR4 Port control register 4 H E7 I O ports Bit Initial value Read Write 7 1 6 1 5 1 4 1 3 1 0 PCR4 0 W 2 PCR4 0 W 1 PCR4 0 W Port 4 input output select 0 Input pin 1 Output pi...

Page 478: ...ontrol register 6 H E9 I O ports Bit Initial value Read Write 7 PCR6 0 W 6 PCR6 0 W 5 PCR6 0 W 4 PCR6 0 W 3 PCR6 0 W 0 PCR6 0 W 2 PCR6 0 W 1 PCR6 0 W Port 6 input output select 0 Input pin 1 Output pin 7 6 5 4 3 0 2 1 PCR7 Port control register 7 H EA I O ports Bit Initial value Read Write 7 PCR7 0 W 6 PCR7 0 W 5 PCR7 0 W 4 PCR7 0 W 3 PCR7 0 W 0 PCR7 0 W 2 PCR7 0 W 1 PCR7 0 W Port 7 input output s...

Page 479: ...Output pin 7 6 5 4 3 0 2 1 PCR9 Port control register 9 H EC I O ports Bit Initial value Read Write 7 1 6 1 5 1 4 1 3 PCR93 0 W 0 PCR90 0 W 2 PCR92 0 W 1 PCR91 0 W Port 9 input output select 0 Input pin 1 Output pin PCRA Port control register A H ED I O ports Bit Initial value Read Write 7 0 6 0 5 0 4 0 3 PCRA 0 W 0 PCRA 0 W 2 PCRA 0 W 1 PCRA 0 W 0 1 2 3 Port A input output select 0 Input pin 1 Ou...

Page 480: ...ait time 2 048 states 1 0 1 Active medium speed mode clock select ø 16 ø 32 0 1 0 0 1 1 ø 64 ø 128 1 1 0 0 1 0 1 Wait time 4 096 states Wait time 2 states Wait time 8 states Wait time 16 states Low speed on flag 0 The CPU operates on the system clock ø 1 The CPU operates on the subclock ø SUB When a SLEEP instruction is executed in subactive mode a transition is made to subsleep mode When a SLEEP ...

Page 481: ... transition is made to active medium speed mode if SSBY 0 MSON 1 and LSON 0 or to subactive mode if SSBY 1 TMA3 1 and LSON 1 When a SLEEP instruction is executed in active medium speed mode a direct transition is made to active high speed mode if SSBY 0 MSON 0 and LSON 0 or to subactive mode if SSBY 1 TMA3 1 and LSON 1 When a SLEEP instruction is executed in subactive mode a direct transition is m...

Page 482: ...cted 1 IRQ1 edge select 0 Falling edge of IRQ1 TMIC pin input is detected Rising edge of IRQ1 TMIC pin input is detected 1 IRQ2 edge select 0 Falling edge of IRQ2 pin input is detected Rising edge of IRQ2 pin input is detected 1 IRQ3 edge select 0 Falling edge of IRQ3 TMIF pin input is detected Rising edge of IRQ3 TMIF pin input is detected 1 IRQ4 edge select 0 Falling edge of IRQ4 pin and ADTRG p...

Page 483: ...1 Wakeup interrupt enable 0 Disables WKP7 to WKP0 interrupt requests Enables WKP7 to WKP0 interrupt requests 1 Timer A interrupt enable 0 Disables timer A interrupt requests Enables timer A interrupt requests 1 SCI1 interrupt enable 0 Disables SCI1 interrupt requests Enables SCI1 interrupt requests 1 Note IRQ0 is an internal signal that performs interfacing to the FLEX decoder incorporated in the ...

Page 484: ...sables timer FH interrupt requests 1 Enables timer FH interrupt requests Timer G interrupt enable 0 Disables timer G interrupt requests 1 Enables timer G interrupt requests A D converter interrupt enable 0 Disables A D converter interrupt requests 1 Enables A D converter interrupt requests Timer C interrupt enable 0 Disables timer C interrupt requests 1 Enables timer C interrupt requests Direct tr...

Page 485: ...IRQn is designated for interrupt input and the designated signal edge is input Timer A interrupt request flag 0 Clearing conditions When IRRTA 1 it is cleared by writing 0 1 Setting conditions When the timer A counter value overflows rom H FF to H 00 SCI1 interrupt request flag 0 Clearing conditions When IRRS1 1 it is cleared by writing 0 1 Setting conditions When SCI1 completes transfer Note IRQ0...

Page 486: ...t Direct transition interrupt request flag 0 Clearing conditions When IRRDT 1 it is cleared by writing 0 1 Setting conditions When a SLEEP instruction is executed while DTON is set to 1 and a direct transition is made Timer FH interrupt request flag 0 Clearing conditions When IRRTFH 1 it is cleared by writing 0 1 Setting conditions When counter FH and output compare register FH match in 8 bit time...

Page 487: ... 0 R W 0 IWPF0 0 R W 2 IWPF2 0 R W 1 IWPF1 0 R W 4 IWPF4 0 R W 0 Clearing conditions When IWPFn 1 it is cleared by writing 0 n 7 to 0 Note All bits can only be written with 0 for flag clearing Wakeup interrupt request register 1 Setting conditions When pin WKPn is designated for wakeup input and a rising or falling edge is input at that pin ...

Page 488: ...red 1 A D converter module standby mode control 0 A D converter is set to module standby mode A D converter module standby mode is cleared 1 Timer C module standby mode control 0 Timer C is set to module standby mode Timer C module standby mode is cleared 1 0 Timer A is set to module standby mode Timer A module standby mode is cleared 1 SCI32 module standby mode control 0 SCI32 is set to module st...

Page 489: ...ck stop register 2 H FB System control Bit Initial value Read Write 7 1 6 1 5 1 3 1 0 1 2 WDCKSTP 1 R W 1 1 4 1 WDT module standby mode control 0 WDT is set to module standby mode WDT module standby mode is cleared 1 ...

Page 490: ...S PUCR1n PMR1n PDR1n PCR1n IRQn 4 SBY low level during reset and in standby mode Internal data bus PDR1 PCR1 PMR1 PUCR1 n 7 to 4 Port data register 1 Port control register 1 Port mode register 1 Port pull up control register 1 P1n Figure C 1 a Port 1 Block Diagram Pins P17 to P14 ...

Page 491: ...R13 PMR13 PDR13 PCR13 PDR1 PCR1 PMR1 PUCR1 Port data register 1 Port control register 1 Port mode register 1 Port pull up control register 1 Internal data bus P13 TMIG Timer G module Figure C 1 b Port 1 Block Diagram Pin P13 ...

Page 492: ...n SBY Internal data bus PDR1 PCR1 PMR1 PUCR1 n 2 or 1 Port data register 1 Port control register 1 Port mode register 1 Port pull up control register 1 TMOFH P12 TMOFL P11 Timer F module P1n Figure C 1 c Port 1 Block Diagram Pins P12 and P11 ...

Page 493: ...0 PDR10 PCR10 CWOS SBY Internal data bus PDR1 PCR1 PMR1 PUCR1 Port data register 1 Port control register 1 Port mode register 1 Port pull up control register 1 TMOW øw Timer A module P10 Figure C 1 d Port 1 Block Diagram Pin P10 ...

Page 494: ...CR24 PDR2 Port data register 2 PCR2 Port control register 2 Internal data bus RES Low in reset Figure C 2 a Port 2 Block Diagram Pin P24 SS PDR23 PCR23 PDR2 Port data register 2 PCR2 Port control register 2 Internal data bus RES FLEXTM Decoder Figure C 2 b Port 2 Block Diagram Pin P23 ...

Page 495: ...483 PDR22 PCR22 PDR2 Port data register 2 PCR2 Port control register 2 PMR2 Port mode register 2 PMR22 Internal data bus MOSI RES SO1 SCI1 module FLEXTM Decoder Figure C 2 c Port 2 Block Diagram Pin P22 ...

Page 496: ...484 PDR21 PCR21 PDR2 Port data register 2 PCR2 Port control register 2 PMR2 Port mode register 2 PMR21 Internal data bus MISO RES SI1 SCI1 module FLEXTM Decoder Figure C 2 d Port 2 Block Diagram Pin P21 ...

Page 497: ...DR20 PCR20 PDR2 Port data register 2 PCR2 Port control register 2 PMR2 Port mode register 2 PMR20 Internal data bus SCK RES SCK0 SCK1 EXCK SCI1 module FLEXTM Decoder Figure C 2 e Port 2 Block Diagram Pin P20 ...

Page 498: ...P3n VCC VCC PUCR3n PDR3n PCR3n Internal data bus SBY VSS PDR3 PCR3 PMR3 PUCR3 Port data register 3 Port control register 3 Port mode register 3 Port pull up control register 3 n 7 or 6 Figure C 3 a Port 3 Block Diagram Pins P37 and P36 ...

Page 499: ...NV1 PCR35 SBY VSS PDR3 PCR3 PUCR3 SCINV1 Port data register 3 Port control register 3 Port pull up control register 3 Bit 1 of serial port control register SPCR TXD31 Internal data bus TE31 VCC VCC Figure C 3 b Port 3 Block Diagram Pin P35 ...

Page 500: ...R34 SCINV0 SBY VSS PDR3 PCR3 PUCR3 SCINV0 Port data register 3 Port control register 3 Port pull up control register 3 Bit 0 of serial port control register SPCR RE31 RXD31 Internal data bus PUCR34 Figure C 3 c Port 3 Block Diagram Pin P34 ...

Page 501: ...module PDR33 PCR33 SBY VSS PDR3 PCR3 PUCR3 Port data register 3 Port control register 3 Port pull up control register 3 SCKIE31 SCKOE31 SCKO31 SCKI31 Internal data bus PUCR33 VCC Figure C 3 d Port 3 Block Diagram Pin P33 ...

Page 502: ... PUCR32 Internal data bus PMR32 PDR32 PCR32 SBY VSS PDR3 Port data register 3 PCR3 Port control register 3 PMR3 Port mode register 3 PUCR3 Port pull up control register 3 RESO Figure C 3 e Port 3 Block Diagram Pin P32 ...

Page 503: ... PDR31 PCR31 UD SBY Internal data bus PDR3 PCR3 PMR3 PUCR3 Port data register 3 Port control register 3 Port mode register 3 Port pull up control register 3 P31 Timer C module PMR31 Figure C 3 f Port 3 Block Diagram Pin P31 ...

Page 504: ...492 P30 VCC VCC PUCR30 PDR30 PCR30 SBY VSS PDR3 Port data register 3 PCR3 Port control register 3 PUCR3 Port pull up control register 3 Internal data bus Figure C 3 g Port 3 Block Diagram Pin P30 ...

Page 505: ...493 C 4 Block Diagrams of Port 4 PMR4 Port mode register 4 PMR43 Internal data bus READY FLEXTM Decoder RES IRQ0 Figure C 4 a Port 4 Block Diagram Pin P43 Chip Internal Input Port ...

Page 506: ... module Internal data bus PDR42 SCINV3 PCR42 SBY VSS PDR4 PCR4 SCINV3 Port data register 4 Port control register 4 Bit 3 of serial port control register SPCR TXD32 TE32 VCC Figure C 4 b Port 4 Block Diagram Pin P42 ...

Page 507: ...CI32 module PDR41 PCR41 SBY VSS PDR4 PCR4 SCINV2 Port data register 4 Port control register 4 Bit 2 of serial port control register SPCR RE32 RXD32 Internal data bus SCINV2 Figure C 4 c Port 4 Block Diagram Pin P41 ...

Page 508: ...496 P40 VCC SCI32 module PDR40 PCR40 SBY VSS PDR4 Port data register 4 PCR4 Port control register 4 SCKIE32 SCKOE32 SCKO32 Internal data bus SCKI32 Figure C 4 d Port 4 Block Diagram Pin P40 ...

Page 509: ... 5 P5n VCC VCC PUCR5n Internal data bus PMR5n PDR5n PCR5n SBY VSS WKPn PDR5 Port data register 5 PCR5 Port control register 5 PMR5 Port mode register 5 PUCR5 Port pull up control register 5 n 7 to 0 Figure C 5 Port 5 Block Diagram ...

Page 510: ...ock Diagram of Port 6 P6n VCC VCC PUCR6n PDR6n Internal data bus PCR6n SBY VSS PDR6 Port data register 6 PCR6 Port control register 6 PUCR6 Port pull up control register 6 n 7 to 0 Figure C 6 Port 6 Block Diagram ...

Page 511: ...499 C 7 Block Diagram of Port 7 P7n VCC PDR7n Internal data bus PCR7n SBY VSS PDR7 Port data register 7 PCR7 Port control register 7 n 7 to 0 Figure C 7 Port 7 Block Diagram ...

Page 512: ...500 C 8 Block Diagrams of Port 8 P8n VCC PDR8n Internal data bus PCR8n SBY VSS PDR8 PCR8 n 7 to 0 Port data register 8 Port control register 8 Figure C 8 Port 8 Block Diagram ...

Page 513: ...501 C 9 Block Diagram of Port 9 P9n VCC PDR9n PCR9n SBY VSS Internal data bus PDR9 Port data register 9 PCR9 Port control register 9 n 3 to 0 Figure C 9 Port 9 Block Diagram ...

Page 514: ...502 C 10 Block Diagram of Port A PAn VCC PDRAn Internal data bus PCRAn SBY VSS PDRA Port data register A PCRA Port control register A n 3 to 0 Figure C 10 Port A Block Diagram ...

Page 515: ...503 C 11 Block Diagram of Port B PBn Internal data bus AMR3 to AMR0 A D module VIN n 7 to 0 DEC Figure C 11 Port B Block Diagram ...

Page 516: ...to P50 High impedance Retained Retained High impedance 1 Retained Functions Functions P67 to P60 High impedance Retained Retained High impedance Retained Functions Functions P77 to P70 High impedance Retained Retained High impedance Retained Functions Functions P87 to P80 High impedance Retained Retained High impedance Retained Functions Functions P93 to P90 High impedance Retained Retained High i...

Page 517: ...HD6433937 W 100 pin TQFP TFP 100G ZTAT HD6473937X HD6473937X 100 pin TQFP TFP 100B versions HD6473937W HD6473937W 100 pin TQFP TFP 100G H8 3937R H8 3935R Mask ROM HD6433935RX HD6433935R X 100 pin TQFP TFP 100B Series versions HD6433935RW HD6433935R W 100 pin TQFP TFP 100G H8 3936R Mask ROM HD6433936RX HD6433936R X 100 pin TQFP TFP 100B versions HD6433936RW HD6433936R W 100 pin TQFP TFP 100G H8 393...

Page 518: ...res F 1 and F 2 respectively Hitachi Code JEDEC EIAJ Weight reference value TFP 100B Conforms 0 5 g Unit mm Dimension including the plating thickness Base material dimension 16 0 0 2 14 0 08 0 10 0 5 0 1 16 0 0 2 0 5 0 10 0 10 1 20 Max 0 17 0 05 0 8 75 51 1 25 76 100 26 50 M 0 22 0 05 1 0 1 00 1 0 0 20 0 04 0 15 0 04 Figure F 1 TFP 100B Package Dimensions ...

Page 519: ...rms 0 4 g Unit mm Dimension including the plating thickness Base material dimension 14 0 0 2 12 0 07 0 10 0 5 0 1 14 0 0 2 0 4 1 20 Max 0 17 0 05 0 8 75 51 1 25 76 100 26 50 M 0 18 0 05 1 0 1 2 0 16 0 04 0 15 0 04 1 00 0 10 0 10 Figure F 2 TFP 100G Package Dimensions ...

Page 520: ...508 ...

Page 521: ...1st Edition February 2001 Published by Electronic Devices Sales Marketing Group Semiconductor Integrated Circuits Hitachi Ltd Edited by Technical Documentation Group Hitachi Kodaira Semiconductor Co Ltd Copyright Hitachi Ltd 2001 All rights reserved Printed in Japan ...

Reviews:

No comments

Brands by name

Popular brands

Load more brands