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8.1.2
Block Diagram
Figure 8.1 shows a block diagram of the EEPROM.
The built-in timer generates the write/erase sequence. The clock pulses for this timer are obtained
from an on-chip oscillator and are independent of the CPU clock. Changing the CPU clock rate
(external clock) does not affect the EEPROM write/erase timing.
The voltage pumping circuit generates the high voltages needed for writing and erasing. No
external high-voltage power supply is required.
Internal data bus (upper 8 bits)
Internal data bus (lower 8 bits)
Voltage pumping circuit
Timer
Oscillator
EPR
ECR
EEPROM
Figure 8.1 EEPROM Block Diagram