Hitachi H8/3008, Hardware Manual

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615
D.2 Pin States at Reset
Modes 1 and 2: Figure D.1 is a timing diagram for the case in which
RES
goes low during an
external memory access in mode 1 or 2. As soon as
RES
goes low, all ports are initialized to the
input state.
AS
,
RD
,
HWR
,
LWR
, and
CS
0
go high, and D
15
to D
0
go to the high-impedance state.
The address bus is initialized to the low output level 2.5
φ
clock cycles after the low level of
RES
is sampled. Clock pin P6
7
/
φ
goes to the output state at the next rise of
φ
after
RES
goes low.
AS
,
RD
(read)
D
15
to D
0
(write)
HWR
,
LWR
(write)
Internal reset
signal
RES
P6
7
/
φ
I/O port,
CS
7
to
CS
1
CS
0
A
19
to A
0
T
1
T
2
T
3
Access to external
memory
H'00000
High impedance
High impedance
Figure D.1 Reset during Memory Access (Modes 1 and 2)