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Hitachi H8/3008, Hardware Manual

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Writing to RSTCSR: RSTCSR must be written by a word transfer instruction. It cannot be
written by byte transfer instructions. Figure 11.3 shows the format of data written to RSTCSR. To
write 0 in the WRST bit, the write data must have H'A5 in the upper byte and H'00 in the lower
byte. The data (H'00) in the lower byte is written to RSTCSR, clearing the WRST bit to 0. To
write to the RSTOE bit, the upper byte must contain H'5A and the lower byte must contain the
write data. Writing this word transfers a write data value into the RSTOE bit.

 15

8   7

0 

H'A5

H'00

Address

H'FFF8E*

 15

8   7

0 

H'5A

Write data

Address

H'FFF8E*

Writing 0 in WRST bit

Writing to RSTOE bit

Note:     Lower 20 bits of the address in advanced mode.

*

Figure 11.3   Format of Data Written to RSTCSR

Reading TCNT, TCSR, and RSTCSR: For reads of TCNT, TCSR, and RSTCSR, address
H'FFF8C is assigned to TCSR, address H'FFF8D to TCNT, and address H'FFF8F to RSTCSR.
These registers are therefore read like other registers.  Byte transfer instructions can be used for
reading.  Table 11.3 lists the read addresses of TCNT, TCSR, and RSTCSR.

Table 11.3

Read Addresses of TCNT, TCSR, and RSTCSR

Address*

Register

H'FFF8C

TCSR

H'FFF8D

TCNT

H'FFF8F

RSTCSR

Note: * Lower 20 bits of the address in advanced mode.

Summary of Contents for H8/3008

Page 1: ...Hitachi 16 Bit Microcomputer H8 3008 Hardware Manual ADE 602 221 Rev 1 0 9 14 00 Hitachi Ltd ...

Page 2: ...of bodily injury such as aerospace aeronautics nuclear power combustion control transportation traffic safety equipment or medical equipment for life support 4 Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating operating supply voltage range heat radiation characteristics installation conditions and other characteristics Hita...

Page 3: ...ing ISO IEC7816 3 character transmission as an expansion function Functions have also been added to reduce power consumption in battery powered applications individual modules can be placed in standby mode and the frequency of the system clock supplied to the chip can be divided under program control The address space is divided into eight areas The data bus width and access cycle length can be se...

Page 4: ......

Page 5: ...ts 24 2 5 1 General Register Data Formats 24 2 5 2 Memory Data Formats 25 2 6 Instruction Set 27 2 6 1 Instruction Set Overview 27 2 6 2 Instructions and Addressing Modes 28 2 6 3 Tables of Instructions Classified by Function 29 2 6 4 Basic Instruction Formats 38 2 6 5 Notes on Use of Bit Manipulation Instructions 39 2 7 Addressing Modes and Effective Address Calculation 41 2 7 1 Addressing Modes ...

Page 6: ...5 Modes 5 and 7 60 3 5 Pin Functions in Each Operating Mode 60 3 6 Memory Map in Each Operating Mode 61 3 6 1 Reserved Areas 61 Section 4 Exception Handling 63 4 1 Overview 63 4 1 1 Exception Handling Types and Priority 63 4 1 2 Exception Handling Operation 63 4 1 3 Exception Vector Table 64 4 2 Reset 66 4 2 1 Overview 66 4 2 2 Reset Sequence 66 4 2 3 Interrupts after Reset 68 4 3 Interrupts 69 4 ...

Page 7: ... 3 Interrupts during EEPMOV Instruction Execution 97 Section 6 Bus Controller 99 6 1 Overview 99 6 1 1 Features 99 6 1 2 Block Diagram 100 6 1 3 Pin Configuration 101 6 1 4 Register Configuration 102 6 2 Register Descriptions 102 6 2 1 Bus Width Control Register ABWCR 102 6 2 2 Access State Control Register ASTCR 103 6 2 3 Wait Control Registers H and L WCRH WCRL 104 6 2 4 Bus Release Control Regi...

Page 8: ... 6 145 7 3 1 Overview 145 7 3 2 Register Descriptions 145 7 4 Port 7 148 7 4 1 Overview 148 7 4 2 Register Description 148 7 5 Port 8 149 7 5 1 Overview 149 7 5 2 Register Descriptions 150 7 6 Port 9 153 7 6 1 Overview 153 7 6 2 Register Descriptions 153 7 7 Port A 156 7 7 1 Overview 156 7 7 2 Register Descriptions 157 7 8 Port B 166 7 8 1 Overview 166 7 8 2 Register Descriptions 167 Section 8 16 ...

Page 9: ... Functions 202 8 4 3 Synchronization 210 8 4 4 PWM Mode 212 8 4 5 Phase Counting Mode 216 8 4 6 16 Bit Timer Output Timing 218 8 5 Interrupts 219 8 5 1 Setting of Status Flags 219 8 5 2 Timing of Clearing of Status Flags 221 8 5 3 Interrupt Sources 222 8 6 Usage Notes 223 Section 9 8 Bit Timers 235 9 1 Overview 235 9 1 1 Features 235 9 1 2 Block Diagram 237 9 1 3 Pin Configuration 238 9 1 4 Regist...

Page 10: ...d Connection 269 9 7 8 Contention between Compare Matches A and B 270 9 7 9 8TCNT Operation and Internal Clock Source Switchover 270 Section 10 Programmable Timing Pattern Controller TPC 273 10 1 Overview 273 10 1 1 Features 273 10 1 2 Block Diagram 274 10 1 3 Pin Configuration 275 10 1 4 Register Configuration 276 10 2 Register Descriptions 277 10 2 1 Port A Data Direction Register PADDR 277 10 2...

Page 11: ...erflow Flag OVF 308 11 3 4 Timing of Setting of Watchdog Timer Reset Bit WRST 309 11 4 Interrupts 310 11 5 Usage Notes 310 Section 12 Serial Communication Interface 311 12 1 Overview 311 12 1 1 Features 311 12 1 2 Block Diagram 313 12 1 3 Pin Configuration 314 12 1 4 Register Configuration 315 12 2 Register Descriptions 316 12 2 1 Receive Shift Register RSR 316 12 2 2 Receive Data Register RDR 316...

Page 12: ...s 379 13 3 3 Data Format 380 13 3 4 Register Settings 382 13 3 5 Clock 384 13 3 6 Transmitting and Receiving Data 386 13 4 Usage Notes 393 Section 14 A D Converter 397 14 1 Overview 397 14 1 1 Features 397 14 1 2 Block Diagram 398 14 1 3 Pin Configuration 399 14 1 4 Register Configuration 400 14 2 Register Descriptions 400 14 2 1 A D Data Registers A to D ADDRA to ADDRD 400 14 2 2 A D Control Stat...

Page 13: ...tion 428 Section 17 Clock Pulse Generator 429 17 1 Overview 429 17 1 1 Block Diagram 429 17 2 Oscillator Circuit 430 17 2 1 Connecting a Crystal Resonator 430 17 2 2 External Clock Input 432 17 3 Duty Adjustment Circuit 434 17 4 Prescalers 434 17 5 Frequency Divider 434 17 5 1 Register Configuration 435 17 5 2 Division Control Register DIVCR 435 17 5 3 Usage Notes 436 Section 18 Power Down State 4...

Page 14: ...lectrical Characteristics Preliminary 451 19 1 Absolute Maximum Ratings 451 19 2 DC Characteristics 452 19 3 AC Characteristics 462 19 4 A D Conversion Characteristics 468 19 5 D A Conversion Characteristics 470 19 6 Operational Timing 471 19 6 1 Clock Timing 471 19 6 2 Control Signal Timing 472 19 6 3 Bus Timing 474 19 6 4 TPC and I O Port Timing 478 19 6 5 Timer Input Output Timing 478 19 6 6 SC...

Page 15: ... E Timing of Transition to and Recovery from Hardware Standby Mode 617 Appendix F Product Code Lineup 618 Appendix G Package Dimensions 619 Appendix H Comparison of H8 300H Series Product Specifications 622 H 1 Differences between H8 3067 and H8 3062 Series H8 3048 Series H8 3006 and H8 3007 and H8 3008 622 H 2 Comparison of Pin Functions of 100 Pin Package Products FP 100B TFP 100B 625 ...

Page 16: ...ess space Its instruction set is upward compatible at the object code level with the H8 300 CPU enabling easy porting of software from the H8 300 Series The on chip system supporting functions include RAM a 16 bit timer an 8 bit timer a programmable timing pattern controller TPC a watchdog timer WDT a serial communication interface SCI an A D converter a D A converter I O ports and other facilitie...

Page 17: ...xii ...

Page 18: ...and unsigned divide instructions 16 bits 8 bits 32 bits 16 bits Bit accumulator function Bit manipulation instructions with register indirect specification of bit positions Memory H8 3008 RAM 4 kbytes Interrupt controller Seven external interrupt pins NMI IRQ0 to IRQ5 27 internal interrupts Three selectable interrupt priority levels Bus controller Address space can be partitioned into eight areas ...

Page 19: ...e output groups or one 16 bit group or two 8 bit groups Non overlap mode available Watchdog timer WDT 1 channel Internal reset signal can be generated by overflow Reset signal can be output externally Usable as an interval timer Serial communication interface SCI 2 channels Selection of asynchronous or synchronous mode Full duplex can transmit and receive simultaneously On chip baud rate generator...

Page 20: ... disabled in modes 1 to 4 Power down state Sleep mode Software standby mode Hardware standby mode Module standby function Programmable system clock frequency division Other features On chip clock pulse generator Product lineup Product Type Model Package Hitachi Package Code H8 3008 5 V operation HD6413008F 100 pin QFP FP 100B HD6413008TE 100 pin TQFP TFP 100B HD6413008FP 100 pin QFP FP 100A 3 V op...

Page 21: ...15 PB 7 TP 14 PB 6 TP 13 PB 5 TP 12 PB 4 CS 4 TMIO 3 TP 11 PB 3 CS 5 TMO 2 TP 10 PB 2 CS 6 TMIO 1 TP 9 PB 1 CS 7 TMO 0 TP 8 PB 0 Port 8 CS0 P84 ADTRG CS1 IRQ3 P83 CS2 IRQ2 P82 CS3 IRQ1 P81 IRQ0 P80 MD MD MD EXTAL XTAL STBY RES RESO NMI 2 1 0 H8 300H CPU Clock pulse generator Interrupt controller Serial communication interface SCI 2 channels Watchdog timer WDT 15 14 13 12 11 10 9 8 Address bus Data...

Page 22: ...xcept for the differences shown in table 1 2 the pin arrangements are the same Table 1 2 Comparison of H8 3008 Pin Arrangements H8 3064F ZTAT H8 3062F ZTAT A Mask Version H8 3008 ROMless Pin Operation Model Package Number 5 V 3 V 5 V 3 V 5 V 3 V FP 100B 1 VCL VCC VCL VCC VCL VCC TFP 100B 10 FWE FWE FWE FWE RESO RESO FP 100A 3 VCL VCC VCL VCC VCL VCC 12 FWE FWE FWE FWE RESO RESO ...

Page 23: ... P84 VSS TCLKA TP0 PA0 TCLKB TP1 PA1 TCLKC TIOCA0 TP2 PA2 TCLKD TIOCB0 TP3 PA3 A23 TIOCA1 TP4 PA4 A22 TIOCB1 TP5 PA5 A21 TIOCA2 TP6 PA6 A20 TIOCB2 TP7 PA7 P8 IRQ CS P8 IRQ AV P7 AN DA P7 AN DA P7 AN P7 AN P7 AN P7 AN P7 AN P7 AN V AV 1 0 7 6 5 4 3 2 1 0 1 0 7 6 5 4 3 2 1 0 Top view FP 100B TFP 100B 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 CC SS SS 76 77 78 79 80 8...

Page 24: ... 97 98 99 100 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 P71 AN1 P72 AN2 P73 AN3 P74 AN4 P75 AN5 P76 AN6 DA0 P77 AN7 DA1 AVSS P80 IRQ0 P81 IRQ1 CS3 P82 IRQ2 CS2 P83 IRQ3 CS1 ADTRG P84 CS0 VSS PA0 TP0 TCLKA PA1 TP1 TCLKB PA2 TP2 TIOCA0 TCLKC PA3 TP3 TIOCB0 TCLKD PA4 TP4 TIOCA1 A23 PA5 TP5 TIOCB1 A22 21 2 6 6 20 2 7 7 0 8 0 1 9 1 11 3 4 3 15 7 4 12 5 13 6 14 7 2 10 2 5 6 SS 0 1 0 1 ...

Page 25: ...t connect to VCC 0 1 µF VCL Clock XTAL 67 69 Input For connection to a crystal resonator For examples of crystal resonator and external clock input see section 20 Clock Pulse Generator EXTAL 66 68 Input For connection to a crystal resonator or input of an external clock signal For examples of crystal resonator and external clock input see section 20 Clock Pulse Generator φ 61 63 Output System cloc...

Page 26: ...est 5 to 0 Maskable interrupt request pins Address bus A23 to A0 97 to 100 56 to 45 43 to 36 99 100 1 2 58 to 47 45 to 38 Output Address bus Outputs address signals Data bus D15 to D0 34 to 23 21 to 18 36 to 25 23 to 20 Input output Data bus Bidirectional data bus Bus control CS7 to CS0 2 to 5 88 to 91 4 to 7 90 to 93 Output Chip select Select signals for areas 7 to 0 AS 69 71 Output Address strob...

Page 27: ... clock input These pins input an external clock to the counters Program mable timing pattern controller TPC TP15 to TP0 9 to 2 100 to 93 11 to 4 2 1 100 to 95 Output TPC output 15 to 0 Pulse output Serial communi TxD1 TxD0 13 12 15 14 Output Transmit data channels 0 1 SCI data output cation interface SCI RxD1 RxD0 15 14 17 16 Input Receive data channels 0 1 SCI data input SCK1 SCK0 17 16 19 18 Inp...

Page 28: ... can be selected in the port 6 data direction register P6DDR P77 to P70 85 to 78 87 to 80 Input Port 7 Eight input pins P84 to P80 91 to 87 93 to 89 Input output Port 8 Five input output pins The direction of each pin can be selected in the port 8 data direction register P8DDR P95 to P90 17 to 12 19 to 14 Input output Port 9 Six input output pins The direction of each pin can be selected in the po...

Page 29: ...PB4 TP12 7 9 PB5 TP13 PB5 TP13 PB5 TP13 PB5 TP13 8 10 PB6 TP14 PB6 TP14 PB6 TP14 PB6 TP14 9 11 PB7 TP15 PB7 TP15 PB7 TP15 PB7 TP15 10 12 RESO RESO RESO RESO 11 13 VSS VSS VSS VSS 12 14 P90 TxD0 P90 TxD0 P90 TxD0 P90 TxD0 13 15 P91 TxD1 P91 TxD1 P91 TxD1 P91 TxD1 14 16 P92 RxD0 P92 RxD0 P92 RxD0 P92 RxD0 15 17 P93 RxD1 P93 RxD1 P93 RxD1 P93 RxD1 16 18 P94 SCK0 IRQ4 P94 SCK0 IRQ4 P94 SCK0 IRQ4 P94 S...

Page 30: ...C VCC VCC 36 38 A0 A0 A0 A0 37 39 A1 A1 A1 A1 38 40 A2 A2 A2 A2 39 41 A3 A3 A3 A3 40 42 A4 A4 A4 A4 41 43 A5 A5 A5 A5 42 44 A6 A6 A6 A6 43 45 A7 A7 A7 A7 44 46 VSS VSS VSS VSS 45 47 A8 A8 A8 A8 46 48 A9 A9 A9 A9 47 49 A10 A10 A10 A10 48 50 A11 A11 A11 A11 49 51 A12 A12 A12 A12 50 52 A13 A13 A13 A13 51 53 A14 A14 A14 A14 52 54 A15 A15 A15 A15 53 55 A16 A16 A16 A16 54 56 A17 A17 A17 A17 55 57 A18 A1...

Page 31: ...0 MD0 MD0 MD0 74 76 MD1 MD1 MD1 MD1 75 77 MD2 MD2 MD2 MD2 76 78 AVCC AVCC AVCC AVCC 77 79 VREF VREF VREF VREF 78 80 P70 AN0 P70 AN0 P70 AN0 P70 AN0 79 81 P71 AN1 P71 AN1 P71 AN1 P71 AN1 80 82 P72 AN2 P72 AN2 P72 AN2 P72 AN2 81 83 P73 AN3 P73 AN3 P73 AN3 P73 AN3 82 84 P74 AN4 P74 AN4 P74 AN4 P74 AN4 83 85 P75 AN5 P75 AN5 P75 AN5 P75 AN5 84 86 P76 AN6 DA0 P76 AN6 DA0 P76 AN6 DA0 P76 AN6 DA0 85 87 P7...

Page 32: ...0 TCLKD PA3 TP3 TIOCB0 TCLKD PA3 TP3 TIOCB0 TCLKD 97 99 PA4 TP4 TIOCA1 PA4 TP4 TIOCA1 PA4 TP4 TIOCA1 A23 PA4 TP4 TIOCA1 A23 98 100 PA5 TP5 TIOCB1 PA5 TP5 TIOCB1 PA5 TP5 TIOCB1 A22 PA5 TP5 TIOCB1 A22 99 1 PA6 TP6 TIOCA2 PA6 TP6 TIOCA2 PA6 TP6 TIOCA2 A21 PA6 TP6 TIOCA2 A21 100 2 PA7 TP7 TIOCB2 PA7 TP7 TIOCB2 A20 A20 Notes 1 In modes 1 and 3 the P40 to P47 functions of pins P40 D0 to P47 D7 are selec...

Page 33: ... and logic instructions Multiply and divide instructions Powerful bit manipulation instructions Eight addressing modes Register direct Rn Register indirect ERn Register indirect with displacement d 16 ERn or d 24 ERn Register indirect with post increment or pre decrement ERn or ERn Absolute address aa 8 aa 16 or aa 24 Immediate xx 8 xx 16 or xx 32 Program counter relative d 8 PC or d 16 PC Memory ...

Page 34: ...PU Enhanced addressing The addressing modes have been enhanced to make effective use of the 16 Mbyte address space Enhanced instructions Data transfer arithmetic and logic instructions can operate on 32 bit data Signed multiply divide instructions and other instructions have been added 2 2 CPU Operating Modes The H8 300H CPU has two operating modes normal and advanced Normal mode supports a maximu...

Page 35: ... kbytes in normal mode and 16 Mbytes in advanced mode For further details see section 3 6 Memory Map in Each Operating Mode The 1 Mbyte operating modes use 20 bit addressing The upper 4 bits of effective addresses are ignored H 00000 H FFFFF H 000000 H FFFFFF a 1 Mbyte mode b 16 Mbyte mode H 0000 H FFFF Advanced mode Normal mode Figure 2 2 Memory Map ...

Page 36: ...2 E3 E4 E5 E6 E7 R0H R1H R2H R3H R4H R5H R6H R7H R0L R1L R2L R3L R4L R5L R6L R7L 0 7 0 7 0 15 SP 23 0 PC 7 CCR 6 5 4 3 2 1 0 I UI H U N Z V C General Registers ERn Control Registers CR Legend SP PC CCR I UI H U N Z V C Stack pointer Program counter Condition code register Interrupt mask bit User bit or interrupt mask bit Half carry flag User bit Negative flag Zero flag Overflow flag Carry flag Fig...

Page 37: ...bit registers The E registers E0 to E7 are also referred to as extended registers The R registers divide into 8 bit general registers designated by the letters RH R0H to R7H and RL R0L to R7L These registers are functionally equivalent providing a maximum sixteen 8 bit registers Figure 2 4 illustrates the usage of the general registers The usage of each register can be selected independently Addre...

Page 38: ...ling sequence Bit 6 User Bit or Interrupt Mask Bit UI Can be written and read by software using the LDC STC ANDC ORC and XORC instructions This bit can also be used as an interrupt mask bit For details see section 5 Interrupt Controller Bit 5 Half Carry Flag H When the ADD B ADDX B SUB B SUBX B CMP B or NEG B instruction is executed this flag is set to 1 if there is a carry or borrow at bit 3 and ...

Page 39: ...rformed on CCR by the LDC STC ANDC ORC and XORC instructions The N Z V and C flags are used by conditional branch Bcc instructions For the action of each instruction on the flag bits see appendix A 1 Instruction List For the I and UI bits see section 5 Interrupt Controller 2 4 4 Initial CPU Register Values In reset exception handling PC is initialized to a value loaded from the vector table and th...

Page 40: ...neral Register Data Formats Figures 2 6 and 2 7 show the data formats in general registers 7 RnH RnL RnH RnL RnH RnL 1 bit data 1 bit data 4 bit BCD data 4 bit BCD data Byte data Byte data 6 5 4 3 2 1 0 7 0 Don t care 7 6 5 4 3 2 1 0 7 0 Don t care Don t care 7 0 4 3 Lower digit Upper digit 7 4 3 Lower digit Upper digit Don t care 0 7 0 Don t care MSB LSB Don t care 7 0 MSB LSB Data Type Data Form...

Page 41: ... General Register Data Formats 2 5 2 Memory Data Formats Figure 2 8 shows the data formats on memory The H8 300H CPU can access word data and longword data on memory but word or longword data must begin at an even address If an attempt is made to access word or longword data at an odd address no address error occurs but the least significant bit of the address is regarded as 0 so the access starts...

Page 42: ...e data Word data Longword data Address Data Type Data Format Address 2M Address 2M 1 Address 2N Address 2N 1 Address 2N 2 Address 2N 3 Figure 2 8 Memory Data Formats When ER7 SP is used as an address register to access the stack the operand size should be word size or longword size ...

Page 43: ...TU 18 Logic operations AND OR XOR NOT 4 Shift operations SHAL SHAR SHLL SHLR ROTL ROTR ROTXL ROTXR 8 Bit manipulation BSET BCLR BNOT BTST BAND BIAND BOR BIOR BXOR BIXOR BLD BILD BST BIST 14 Branch Bcc 3 JMP BSR JSR RTS 5 System control TRAPA RTE SLEEP LDC STC ANDC ORC XORC NOP 9 Block data transfer EEPMOV 1 Total 64 types Notes 1 POP W Rn is identical to MOV W SP Rn PUSH W Rn is identical to MOV W...

Page 44: ... PC aa 8 Data MOV BWL BWL BWL BWL BWL BWL B BWL BWL transfer POP PUSH WL MOVFPE MOVTPE Arithmetic ADD CMP BWL BWL operations SUB WL BWL ADDX SUBX B B ADDS SUBS L INC DEC BWL DAA DAS B MULXU BW MULXS DIVXU DIVXS NEG BWL EXTU EXTS WL Logic operations AND OR XOR BWL NOT BWL Shift instructions BWL Bit manipulation B B B Branch Bcc BSR JMP JSR RTS System TRAPA control RTE SLEEP LDC B B W W W W W W STC ...

Page 45: ...er EAd Destination operand EAs Source operand CCR Condition code register N N negative flag of CCR Z Z zero flag of CCR V V overflow flag of CCR C C carry flag of CCR PC Program counter SP Stack pointer IMM Immediate data disp Displacement Addition Subtraction Multiplication Division AND logical OR logical Exclusive OR logical Move NOT logical complement 3 8 16 24 3 8 16 or 24 bit length Note Gene...

Page 46: ... EAs Rd Cannot be used in the H8 3008 MOVTPE B Rs EAs Cannot be used in the H8 3008 POP W L SP Rn Pops a general register from the stack POP W Rn is identical to MOV W SP Rn Similarly POP L ERn is identical to MOV L SP ERn PUSH W L Rn SP Pushes a general register onto the stack PUSH W Rn is identical to MOV W Rn SP Similarly PUSH L ERn is identical to MOV L ERn SP Note Size refers to the operand s...

Page 47: ...al register INC DEC B W L Rd 1 Rd Rd 2 Rd Increments or decrements a general register by 1 or 2 Byte operands can be incremented or decremented by 1 only ADDS SUBS L Rd 1 Rd Rd 2 Rd Rd 4 Rd Adds or subtracts the value 1 2 or 4 to or from data in a 32 bit register DAA DAS B Rd decimal adjust Rd Decimal adjusts an addition or subtraction result in a general register by referring to CCR to produce 4 ...

Page 48: ...r with data in another general register or with immediate data and sets CCR according to the result NEG B W L 0 Rd Rd Takes the two s complement arithmetic complement of data in a general register EXTS W L Rd sign extension Rd Extends byte data in the lower 8 bits of a 16 bit register to word data or extends word data in the lower 16 bits of a 32 bit register to longword data by extending the sign...

Page 49: ...ther general register or immediate data NOT B W L Rd Rd Takes the one s complement logical complement of general register contents Note Size refers to the operand size B Byte W Word L Longword Table 2 6 Shift Instructions Instruction Size Function SHAL SHAR B W L Rd shift Rd Performs an arithmetic shift on general register contents SHLL SHLR B W L Rd shift Rd Performs a logical shift on general re...

Page 50: ...erand The bit number is specified by 3 bit immediate data or the lower 3 bits of a general register BTST B bit No of EAd Z Tests a specified bit in a general register or memory operand and sets or clears the Z flag accordingly The bit number is specified by 3 bit immediate data or the lower 3 bits of a general register BAND B C bit No of EAd C ANDs the carry flag with a specified bit in a general ...

Page 51: ...y flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag The bit number is specified by 3 bit immediate data BLD B bit No of EAd C Transfers a specified bit in a general register or memory operand to the carry flag The bit number is specified by 3 bit immediate data BILD B bit No of EAd C Transfers the inverse of a specified bit in ...

Page 52: ... 0 BLS Low or same C Z 1 Bcc BHS Carry clear high or same C 0 BCS BLO Carry set low C 1 BNE Not equal Z 0 BEQ Equal Z 1 BVC Overflow clear V 0 BVS Overflow set V 1 BPL Plus N 0 BMI Minus N 1 BGE Greater or equal N V 0 BLT Less than N V 1 BGT Greater than Z N V 0 BLE Less or equal Z N V 1 JMP Branches unconditionally to a specified address BSR Branches to a subroutine at a specified address JSR Bra...

Page 53: ...m memory data is read by word access STC B W CCR EAd Transfers the CCR contents to a destination location The condition code register size is one byte but in transfer to memory data is written by word access ANDC B CCR IMM CCR Logically ANDs the condition code register with immediate data ORC B CCR IMM CCR Logically ORs the condition code register with immediate data XORC B CCR IMM CCR Logically e...

Page 54: ...d an effective address extension EA field and a condition field cc Operation Field Indicates the function of the instruction the addressing mode and the operation to be carried out on the operand The operation field always includes the first 4 bits of the instruction Some instructions have two operation fields Register Field Specifies a general register Address registers are specified by 3 bits da...

Page 55: ...ructions read a byte of data modify a bit in the byte then write the byte back Care is required when these instructions are used to access registers with write only bits or to access ports Step Description 1 Read Read one data byte at the specified address 2 Modify Modify one bit in the data byte 3 Write Write the modified data byte back to the specified address Example 1 BCLR is executed to clear...

Page 56: ...it is read as H FF even though its true value is H 3F Next the CPU clears bit 0 of the read data changing the value to H FE Finally the CPU writes this value H FE back to P4DDR to complete the BCLR instruction As a result P40DDR is cleared to 0 making P40 an input pin In addition P47DDR and P46DDR are set to 1 making P47 and P46 output pins The BCLR instruction can be used to clear flags in the on...

Page 57: ...ister indirect with post increment Register indirect with pre decrement ERn ERn 5 Absolute address aa 8 aa 16 aa 24 6 Immediate xx 8 xx 16 xx 32 7 Program counter relative d 8 PC d 16 PC 8 Memory indirect aa 8 1 Register Direct Rn The register field of the instruction code specifies an 8 16 or 32 bit register containing the operand R0H to R7H and R0L to R7L can be specified as 8 bit registers R0 t...

Page 58: ...ong aa 8 16 bits long aa 16 or 24 bits long aa 24 For an 8 bit absolute address the upper 16 bits are all assumed to be 1 H FFFF For a 16 bit absolute address the upper 8 bits are a sign extension A 24 bit absolute address can access the entire address space Table 2 12 indicates the accessible address ranges Table 2 12 Absolute Address Access Ranges Absolute Address 1 Mbyte Modes 16 Mbyte Modes 8 ...

Page 59: ...ss See figure 2 10 The upper bits of the 8 bit absolute address are assumed to be 0 H 0000 so the address range is 0 to 255 H 000000 to H 0000FF Note that the first part of this range is also the exception vector area For further details see section 5 Interrupt Controller Specified by aa 8 Reserved Branch address Figure 2 10 Memory Indirect Branch Address Specification When a word size or longword...

Page 60: ...er contents 31 0 23 0 Register indirect with displacement d 16 ERn d 24 ERn 3 op r General register contents 31 0 23 0 Sign extension disp Register indirect with post increment or pre decrement 4 General register contents 31 0 23 0 1 2 or 4 op r General register contents 31 0 23 0 1 2 or 4 op r Register indirect with post increment ERn Register indirect with pre decrement ERn 1 for a byte operand ...

Page 61: ...ective Address Absolute address aa 8 5 op Program counter relative d 8 PC or d 16 PC 7 0 23 0 abs 23 0 8 7 aa 16 aa 24 op abs 23 0 16 15 H FFFF Sign extension op 23 0 abs Immediate xx 8 xx 16 or xx 32 6 Operand is immediate data op disp 23 0 PC contents disp op IMM Sign extension ...

Page 62: ...e Address 8 Legend r rm rn op disp IMM abs Register field Operation field Displacement Immediate data Absolute address Memory indirect aa 8 8 op 23 0 abs 23 0 8 7 H 0000 15 0 abs 16 15 Normal mode op 23 0 abs 23 0 8 7 H 0000 0 abs Advanced mode 31 H 00 Memory contents Memory contents ...

Page 63: ...er down state The CPU executes program instructions in sequence A transient state in which the CPU executes a hardware sequence saving PC and CCR fetching a vector etc in response to a reset interrupt or other exception The external bus has been released in response to a bus request signal from a bus master other than the CPU The CPU and all on chip supporting modules are initialized and halted Th...

Page 64: ...on Detection Timing Start of Exception Handling High Reset Synchronized with clock Exception handling starts immediately when RES changes from low to high Interrupt End of instruction execution or end of exception handling When an interrupt is requested exception handling starts at the end of the current instruction or current exception handling sequence Low Trap instruction When TRAPA instruction...

Page 65: ...tate is entered when the RES signal goes low Reset exception handling starts after that when RES changes from low to high When reset exception handling starts the CPU fetches a start address from the exception vector table and starts program execution from that address All interrupts including NMI are disabled during the reset exception handling sequence and immediately after it ends Interrupt Exc...

Page 66: ... Handling 2 8 5 Bus Released State In this state the bus is released to a bus master other than the CPU in response to a bus request The bus masters other than the CPU is an external bus master While the bus is released the CPU halts except for internal operations Interrupt requests are not accepted For details see section 6 6 Bus Arbiter 2 8 6 Reset State When the RES input goes low all current p...

Page 67: ... standby mode is made when the STBY input goes low As in software standby mode the CPU and all clocks halt and the on chip supporting modules are reset but as long as a specified voltage is supplied on chip RAM contents are retained For further information see section 18 Power Down State 2 9 Basic Operational Timing 2 9 1 Overview The H8 300H CPU operates according to the system clock ø The interv...

Page 68: ...φ 1 T2 Address bus D to D 15 0 RD HWR LWR High Address High impedance Figure 2 16 Pin States during On Chip Memory Access Address Update Mode 1 2 9 3 On Chip Supporting Module Access Timing The on chip supporting modules are accessed in three states The data bus is 8 or 16 bits wide depending on the internal I O register being accessed Figure 2 17 shows the on chip supporting module access timing ...

Page 69: ...ules T AS φ 1 T2 Address bus D to D 15 0 RD HWR LWR High High impedance T3 Address Figure 2 18 Pin States during Access to On Chip Supporting Modules 2 9 4 Access to External Address Space The external address space is divided into eight areas areas 0 to 7 Bus controller settings determine whether each area is accessed via an 8 bit or 16 bit data bus and whether it is accessed in two or three stat...

Page 70: ...54 ...

Page 71: ...Disabled Enabled 2 Mode 4 1 0 0 Expanded mode 16 bits Disabled Enabled 2 1 0 1 Setting prohibited Setting prohibited Setting prohibited Setting prohibited 1 1 0 Setting prohibited Setting prohibited Setting prohibited Setting prohibited 1 1 1 Setting prohibited Setting prohibited Setting prohibited Setting prohibited Notes 1 In modes 1 to 4 an 8 bit or 16 bit data bus can be selected on a per area...

Page 72: ...arizes these registers Table 3 2 Registers Address Name Abbreviation R W Initial Value H EE011 Mode control register MDCR R Undetermined H EE012 System control register SYSCR R W H 09 Note Lower 20 bits of the address in advanced mode 3 2 Mode Control Register MDCR MDCR is an 8 bit read only register that indicates the current operating mode of the H8 3008 Bit Initial value Read Write 7 1 6 1 5 0 ...

Page 73: ... input RAM enable Enables or disables on chip RAM Standby timer select 2 to 0 These bits select the waiting time at recovery from software standby mode Selects the output state of the address bus and bus control signals in software standby mode Software standby output port enable Bit 7 Software Standby SSBY Enables transition to software standby mode For further information about software standby ...

Page 74: ...tion 0 0 0 Waiting time 8 192 states Initial value 0 0 1 Waiting time 16 384 states 0 1 0 Waiting time 32 768 states 0 1 1 Waiting time 65 536 states 1 0 0 Waiting time 131 072 states 1 0 1 Waiting time 262 144 states 1 1 0 Waiting time 1 024 states 1 1 1 Illegal setting Bit 3 User Bit Enable UE Selects whether to use the UI bit in the condition code register as a user bit or an interrupt mask bit...

Page 75: ...tion as address pins A19 to A0 permitting access to a maximum 1 Mbyte address space The initial bus mode after a reset is 8 bits with 8 bit access to all areas If at least one area is designated for 16 bit access in ABWCR the bus mode switches to 16 bits 3 4 2 Mode 2 Ports 1 2 and 5 function as address pins A19 to A0 permitting access to a maximum 1 Mbyte address space The initial bus mode after a...

Page 76: ...rts 1 to 5 and port A vary depending on the operating mode Table 3 3 indicates their functions in each operating mode Table 3 3 Pin Functions in Each Mode Port Mode 1 Mode 2 Mode 3 Mode 4 Port 1 A7 to A0 A7 to A0 A7 to A0 A7 to A0 Port 2 A15 to A8 A15 to A8 A15 to A8 A15 to A8 Port 3 D15 to D8 D15 to D8 D15 to D8 D15 to D8 Port 4 P47 to P40 1 D7 to D0 1 P47 to P40 1 D7 to D0 1 Port 5 A19 to A16 A1...

Page 77: ... and 2 and the 16 Mbyte modes modes 3 and 4 The address range specifiable by the CPU in the 8 and 16 bit absolute addressing modes aa 8 and aa 16 also differs 3 6 1 Reserved Areas The H8 3008 memory map includes reserved areas to which access reading or writing is prohibited Normal operation cannot be guaranteed if the following reserved areas are accessed Reserved Area in Internal I O Register Sp...

Page 78: ...p ROM disabled H 000000 H 0000FF H 007FFF Memory indirect branch addresses 16 bit absolute addresses H 1FFFFF H 200000 Area 0 Area 1 Area 2 Area 3 Area 4 Area 5 Area 6 Area 7 External address space Vector area External address space 8 bit absolute addresses 16 bit absolute addresses H FF8000 H FFEF1F H FFEF20 H FFFF1F H FFFF20 H FFFF00 H FFFFE9 H FFFFEA H FFFFFF H 3FFFFF H 400000 H 5FFFFF H 600000...

Page 79: ...gh Reset Starts immediately after a low to high transition at the RES pin Interrupt Interrupt requests are handled when execution of the current instruction or handling of the current exception is completed Low Trap instruction TRAPA Started by execution of a trap instruction TRAPA 4 1 2 Exception Handling Operation Exceptions originate from various sources Trap instructions and interrupts are han...

Page 80: ... vectors are assigned to different exception sources Table 4 2 lists the exception sources and their vector addresses Exception sources Reset Interrupts Trap instruction External interrupts Internal interrupts NMI IRQ to IRQ 27 interrupts from on chip supporting modules 0 5 Figure 4 1 Exception Sources ...

Page 81: ...H 0028 to H 002B H 0014 to H 0015 11 H 002C to H 002F H 0016 to H 0017 External interrupt IRQ0 12 H 0030 to H 0033 H 0018 to H 0019 External interrupt IRQ1 13 H 0034 to H 0037 H 001A to H 001B External interrupt IRQ2 14 H 0038 to H 003B H 001C to H 001D External interrupt IRQ3 15 H 003C to H 003F H 001E to H 001F External interrupt IRQ4 16 H 0040 to H 0043 H 0020 to H 0021 External interrupt IRQ5 ...

Page 82: ...ring operation hold the RES pin low for at least 10 system clock ø cycles In the versions with on chip flash memory the RES pin must be held low for at least 20 system clock cycles See appendix D 2 Pin States at Reset for the states of the pins in the reset state When the RES pin goes high after being held low for the necessary time the chip starts reset exception handling as follows The internal ...

Page 83: ...a reset the wait state controller inserts three wait states in every bus cycle Address of reset exception handling vector 1 H 000000 3 H 000001 5 H 000002 7 H 000003 Start address contents of reset exception handling vector address Start address First instruction of program High 1 3 5 7 9 2 4 6 8 10 LWR Figure 4 2 Reset Sequence Modes 1 and 3 ...

Page 84: ...rt address First instruction of program 2 4 3 1 5 6 Figure 4 3 Reset Sequence Modes 2 and 4 4 2 3 Interrupts after Reset If an interrupt is accepted after a reset but before the stack pointer SP is initialized PC and CCR will not be saved correctly leading to a program crash To prevent this all interrupt requests including NMI are disabled immediately after a reset exception handling The first ins...

Page 85: ...ned in interrupt priority registers A and B IPRA and IPRB in the interrupt controller For details on interrupts see section 5 Interrupt Controller Interrupts External interrupts Internal interrupts NMI 1 IRQ to IRQ 6 WDT 1 16 bit timer 9 8 bit timer 8 SCI 8 A D converter 1 Notes Numbers in parentheses are the number of interrupt sources When the watchdog timer is used as an interval timer it gener...

Page 86: ...ck area CCR CCR PC PC CCR PC PC PC H L E H L After exception handling Even address Even address Pushed on stack Pushed on stack a Normal mode b Advanced mode Legend PCE PCH PCL CCR SP Notes PC indicates the address of the first instruction that will be executed after return Registers must be saved in word or longword size at even addresses Ignored at return 1 2 Bits 23 to 16 of program counter PC ...

Page 87: ...d the value of the stack pointer SP ER7 should always be kept even Use the following instructions to save registers PUSH W Rn or MOV W Rn SP PUSH L ERn or MOV L ERn SP Use the following instructions to restore registers POP W Rn or MOV W SP Rn POP L ERn or MOV L SP ERn Setting SP to an odd value may lead to a malfunction Figure 4 6 shows an example of what happens when the SP value is odd ...

Page 88: ...B R1L ER7 SP set to H FFFEFF Data saved above SP CCR contents lost Condition code register Program counter General register R1L Stack pointer Note The diagram illustrates modes 3 and 4 H FFFEFA H FFFEFB H FFFEFC H FFFEFD H FFFEFE H FFFEFF Figure 4 6 Operation when SP Value is Odd ...

Page 89: ...module by module basis in interrupt priority registers A and B IPRA and IPRB Three level enabling disabling by the I and UI bits in the CPU s condition code register CCR and the UE bit in the system control register SYSCR Seven external interrupt pins NMI has the highest priority and is always accepted either the rising or falling edge can be selected For each of IRQ5 to IRQ0 sensing of the fallin...

Page 90: ...input IRQ input IRQ input section ISR Interrupt controller Priority decision logic Interrupt request Vector number IRQ sense control register IRQ enable register IRQ status register Interrupt priority register A Interrupt priority register B System control register Legend ISCR IER ISR IPRA IPRB SYSCR Figure 5 1 Interrupt Controller Block Diagram ...

Page 91: ...tem control register SYSCR R W H 09 H EE014 IRQ sense control register ISCR R W H 00 H EE015 IRQ enable register IER R W H 00 H EE016 IRQ status register ISR R W 2 H 00 H EE018 Interrupt priority register A IPRA R W H 00 H EE019 Interrupt priority register B IPRB R W H 00 Notes 1 Lower 20 bits of the address in advanced mode 2 Only 0 can be written to clear flags 5 2 Register Descriptions 5 2 1 Sy...

Page 92: ...MI input edge Software standby output port enable RAM enable Bit 3 User Bit Enable UE Selects whether to use the UI bit in CCR as a user bit or an interrupt mask bit Bit 3 UE Description 0 UI bit in CCR is used as interrupt mask bit 1 UI bit in CCR is used as user bit Initial value Bit 2 NMI Edge Select NMIEG Selects the NMI input edge Bit 2 NMIEG Description 0 Interrupt is requested at falling ed...

Page 93: ...verter interrupt requests Priority level A2 Selects the priority level of 16 bit timer channel 0 interrupt requests Priority level A1 Selects the priority level of 16 bit timer channel 1 interrupt requests Priority level A0 Selects the priority level of 16 bit timer channel 2 interrupt requests Selects the priority level of IRQ interrupt requests Priority level A6 Selects the priority level of IRQ...

Page 94: ...3 interrupt requests Bit 5 IPRA5 Description 0 IRQ2 and IRQ3 interrupt requests have priority level 0 low priority Initial value 1 IRQ2 and IRQ3 interrupt requests have priority level 1 high priority Bit 4 Priority Level A4 IPRA4 Selects the priority level of IRQ4 and IRQ5 interrupt requests Bit 4 IPRA4 Description 0 IRQ4 and IRQ5 interrupt requests have priority level 0 low priority Initial value...

Page 95: ...ity level of 16 bit timer channel 1 interrupt requests Bit 1 IPRA1 Description 0 16 bit timer channel 1 interrupt requests have priority level 0 low priority Initial value 1 16 bit timer channel 1 interrupt requests have priority level 1 high priority Bit 0 Priority Level A0 IPRA0 Selects the priority level of 16 bit timer channel 2 interrupt requests Bit 0 IPRA0 Description 0 16 bit timer channel...

Page 96: ...0 interrupt requests Priority level B2 Selects the priority level of SCI channel 1 interrupt requests Reserved bit Reserved bits Selects the priority level of 8 bit timer channel 2 3 interrupt requests Priority level B6 IPRB is initialized to H 00 by a reset and in hardware standby mode Bit 7 Priority Level B7 IPRB7 Selects the priority level of 8 bit timer channel 0 1 interrupt requests Bit 7 IPR...

Page 97: ... requests Bit 3 IPRB3 Description 0 SCI0 channel 0 interrupt requests have priority level 0 low priority Initial value 1 SCI0 channel 0 interrupt requests have priority level 1 high priority Bit 2 Priority Level B2 IPRB2 Selects the priority level of SCI channel 1 interrupt requests Bit 2 IPRB2 Description 0 SCI1 channel 1 interrupt requests have priority level 0 low priority Initial value 1 SCI1 ...

Page 98: ...learing conditions Initial value 0 is written in IRQnF after reading the IRQnF flag when IRQnF 1 IRQnSC 0 IRQn input is high and interrupt exception handling is carried out IRQnSC 1 and IRQn interrupt exception handling is carried out 1 Setting conditions IRQnSC 0 and IRQn input is low IRQnSC 1 and IRQn input changes from high to low Note n 5 to 0 5 2 4 IRQ Enable Register IER IER is an 8 bit read...

Page 99: ...ect level sensing or falling edge sensing for IRQ to IRQ interrupts 6 0 R W 5 IRQ5SC 0 R W 4 IRQ4SC 0 R W 3 IRQ3SC 0 R W 2 IRQ2SC 0 R W 1 IRQ1SC 0 R W 0 IRQ0SC 0 R W 5 0 IRQ to IRQ sense control 5 0 Reserved bits ISCR is initialized to H 00 by a reset and in hardware standby mode Bits 7 and 6 Reserved These bits can be written and read but they do not select level or falling edge sensing Bits 5 to...

Page 100: ...mber 7 IRQ5 to IRQ0 Interrupts These interrupts are requested by input signals at pins IRQ5 to IRQ0 The IRQ5 to IRQ0 interrupts have the following features ISCR settings can select whether an interrupt is requested by the low level of the input at pins IRQ5 to IRQ0 or by the falling edge IER settings can enable or disable the IRQ5 to IRQ0 interrupts Interrupt priority levels can be assigned by fou...

Page 101: ...nternal Interrupts Twenty Seven internal interrupts are requested from the on chip supporting modules Each on chip supporting module has status flags for indicating interrupt status and enable bits for enabling or disabling interrupts Interrupt priority levels can be assigned in IPRA and IPRB 5 3 3 Interrupt Exception Handling Vector Table Table 5 3 lists the interrupt exception handling sources t...

Page 102: ...7 WOVI interval timer Watchdog timer 20 H 0050 to H 0053 H 0028 to H 0029 IPRA3 Reserved 21 H 0054 to H 0057 H 002A to H 002B 22 H 0058 to H 005B H 002C to H 002D ADI A D end A D 23 H 005C to H 005F H 002E to H 002F IMIA0 compare match input capture A0 IMIB0 compare match input capture B0 OVI0 overflow 0 16 bit timer channel 0 24 25 26 H 0060 to H 0063 H 0064 to H 0067 H 0068 to H 006B H 0030 to H...

Page 103: ...to H 0093 H 0094 to H 0097 H 0098 to H 009B H 009C to H 009F H 0048 to H 0049 H 004A to H 004B H 004C to H 004D H 004E to H 004F IPRB7 CMIA2 compare match A2 CMIB2 compare match B2 CMIA3 CMIB3 compare match A3 B3 TOVI2 TOVI3 overflow 2 3 8 bit timer channel 2 3 40 41 42 43 H 00A0 to H 00A3 H 00A4 to H 00A7 H 00A8 to H 00AB H 00AC to H 00AF H 0050 to H 0051 H 0052 to H 0053 H 0054 to H 0055 H 0056 ...

Page 104: ...o H 006B H 006C to H 006D H 006E to H 006F IPRB3 High ERI1 receive error 1 RXI1 receive data full 1 TXI1 transmit data empty 1 TEI1 transmit end 1 SCI channel 1 56 57 58 59 H 00E0 to H 00E3 H 00E4 to H 00E7 H 00E8 to H 00EB H 00EC to H 00EF H 0070 to H 0071 H 0072 to H 0073 H 0074 to H 0075 H 0076 to H 0077 IPRB2 Reserved 60 61 62 63 H 00F0 to H 00F3 H 00F4 to H 00F7 H 00F8 to H 00FB H 00FC to H 0...

Page 105: ...le bits are cleared to 0 Table 5 4 UE I and UI Bit Settings and Interrupt Handling SYSCR CCR UE I UI Description 1 0 All interrupts are accepted Interrupts with priority level 1 have higher priority 1 No interrupts are accepted except NMI 0 0 All interrupts are accepted Interrupts with priority level 1 have higher priority 1 0 NMI and interrupts with priority level 1 are accepted 1 No interrupts a...

Page 106: ...o Yes No Yes No Priority level 1 No IRQ0 Yes No IRQ1 Yes TEI1 Yes No IRQ0 Yes No IRQ1 Yes TEI1 Yes No I 0 Yes Save PC and CCR I 1 Branch to interrupt service routine Pending Yes Read vector address Figure 5 4 Process Up to Interrupt Acceptance when UE 1 ...

Page 107: ...the return from the interrupt service routine Next the I bit is set to 1 in CCR masking all interrupts except NMI The vector address of the accepted interrupt is generated and the interrupt service routine starts executing from the address indicated by the contents of the vector address UE 0 The I and UI bits in the CPU s CCR and the IPR bits enable three level masking of IRQ0 to IRQ5 interrupts a...

Page 108: ...upt controller checks the I bit If the I bit is cleared to 0 the selected interrupt request is accepted regardless of its IPR setting and regardless of the UI bit If the I bit is set to 1 and the UI bit is cleared to 0 only interrupts with priority level 1 are accepted interrupt requests with priority level 0 are held pending If the I bit and UI bit are both set to 1 all other interrupt requests a...

Page 109: ...o Priority level 1 No IRQ0 Yes No IRQ1 Yes TEI1 Yes No IRQ0 Yes No IRQ1 Yes TEI1 Yes No I 0 Yes No I 0 Yes UI 0 Yes No Save PC and CCR I 1 UI 1 Pending Branch to interrupt service routine Yes Read vector address Figure 5 6 Process Up to Interrupt Acceptance when UE 0 ...

Page 110: ...nstruction Interrupt accepted Instruction prefetch Internal processing Stack Vector fetch Internal processing Prefetch of interrupt service routine instruction High Instruction prefetch address not executed return address same as PC contents Instruction code not executed Instruction prefetch address not executed SP 2 SP 4 6 8 9 11 10 12 13 14 PC and CCR saved to stack Vector address Starting addre...

Page 111: ...til end of current instruction 1 to 23 1 to 27 1 to 31 4 1 to 23 1 to 25 4 3 Saving PC and CCR to stack 4 8 12 4 4 6 4 4 Vector fetch 4 8 12 4 4 6 4 5 Instruction fetch 2 4 8 12 4 4 6 4 6 Internal processing 3 4 4 4 4 4 Total 19 to 41 31 to 57 43 to 73 19 to 41 25 to 49 Notes 1 1 state for internal interrupts 2 Prefetch after the interrupt is accepted and prefetch of the first instruction in the i...

Page 112: ... is carried out If a higher priority interrupt is also requested however interrupt exception handling for the higher priority interrupt is carried out and the lower priority interrupt is ignored This also applies to the clearing of an interrupt flag to 0 Figure 5 8 shows an example in which an IMIEA bit is cleared to 0 in the 16 bit timer s TISRA register IMIA exception handling TISRA write cycle ...

Page 113: ...truction Execution The EEPMOV B and EEPMOV W instructions differ in their reaction to interrupt requests When the EEPMOV B instruction is executing a transfer no interrupts are accepted until the transfer is completed not even NMI When the EEPMOV W instruction is executing a transfer interrupt requests other than NMI are not accepted until the transfer is completed If NMI is requested NMI exceptio...

Page 114: ...98 ...

Page 115: ... as eight areas 0 to 7 of 128 kbytes in 1M byte modes or 2 Mbytes in 16 Mbyte modes Bus specifications can be set independently for each area Basic bus interface Chip select CS0 to CS7 can be output for areas 0 to 7 8 bit access or 16 bit access can be selected for each area Two state access or three state access can be selected for each area Program wait states can be inserted for each area Pin w...

Page 116: ...bus request signal CPU bus acknowledge signal Bus arbiter Bus mode control signal Internal signals Internal signals Bus size control signal Access state control signal Wait request signal Bus width control register Access state control register Wait control register H Wait control register L Bus release control register Chip select control register ASTCR WCRH WCRL BRCR CSCR Address control registe...

Page 117: ...ing from the external address space High write HWR Output Strobe signal indicating writing to the external address space with valid data on the upper data bus D15 to D8 Low write LWR Output Strobe signal indicating writing to the external address space with valid data on the lower data bus D7 to D0 Wait WAIT Input Wait request signal for access to external three state access areas Bus request BREQ...

Page 118: ... 6 2 Register Descriptions 6 2 1 Bus Width Control Register ABWCR ABWCR is an 8 bit readable writable register that selects 8 bit or 16 bit access for each area 7 ABW7 1 R W 0 R W 6 ABW6 1 R W 0 R W 5 ABW5 1 R W 0 R W 4 ABW4 1 R W 0 R W 3 ABW3 1 R W 0 R W 2 ABW2 1 R W 0 R W 1 ABW1 1 R W 0 R W 0 ABW0 1 R W 0 R W Bit Modes 1 and 3 Initial value Read Write Initial value Read Write Modes 2 and 4 When ...

Page 119: ... AST3 AST2 AST1 AST0 1 Initial value 1 1 1 1 1 1 1 Read Write R W R W R W R W R W R W R W R W 7 6 5 4 3 2 1 0 Bits selecting number of states for access to each area AST7 AST6 AST5 AST4 Bit ASTCR is initialized to H FF by a reset and in hardware standby mode It is not initialized in software standby mode Bits 7 to 0 Area 7 to 0 Access State Control AST7 to AST0 These bits select whether the corres...

Page 120: ...0 1 Initial value 1 1 1 1 1 1 1 Read Write R W R W R W R W R W R W R W R W 7 6 5 4 3 2 1 0 W71 W70 W61 W60 Bit Bits 7 and 6 Area 7 Wait Control 1 and 0 W71 W70 These bits select the number of program wait states when area 7 in external space is accessed while the AST7 bit in ASTCR is set to 1 Bit 7 W71 Bit 6 W70 Description 0 0 Program wait not inserted when external space area 7 is accessed 1 1 p...

Page 121: ...ST5 bit in ASTCR is set to 1 Bit 3 W51 Bit 2 W50 Description 0 0 Program wait not inserted when external space area 5 is accessed 1 1 program wait state inserted when external space area 5 is accessed 1 0 2 program wait states inserted when external space area 5 is accessed 1 3 program wait states inserted when external space area 5 is accessed Initial value Bits 1 and 0 Area 4 Wait Control 1 and ...

Page 122: ...ccessed 1 0 2 program wait states inserted when external space area 3 is accessed 1 3 program wait states inserted when external space area 3 is accessed Initial value Bits 5 and 4 Area 2 Wait Control 1 and 0 W21 W20 These bits select the number of program wait states when area 2 in external space is accessed while the AST2 bit in ASTCR is set to 1 Bit 5 W21 Bit 4 W20 Description 0 0 Program wait ...

Page 123: ...ea 1 is accessed 1 3 program wait states inserted when external space area 1 is accessed Initial value Bits 1 and 0 Area 0 Wait Control 1 and 0 W01 W00 These bits select the number of program wait states when area 0 in external space is accessed while the AST0 bit in ASTCR is set to 1 Bit 1 W01 Bit 0 W00 Description 0 0 Program wait not inserted when external space area 0 is accessed 1 1 program w...

Page 124: ...FE in modes 1 and 2 and to H EE in modes 3 and 4 by a reset and in hardware standby mode It is not initialized in software standby mode Bit 7 Address 23 Enable A23E Enables PA4 to be used as the A23 address output pin Writing 0 in this bit enables A23 output from PA4 In modes other than 3 and 4 this bit cannot be modified and PA4 has its ordinary port functions Bit 7 A23E Description 0 PA4 is the ...

Page 125: ...utput pin In mode 3 or 4 1 PA7 is an input output pin In mode 1 or 2 Bits 3 to 1 Reserved These bits cannot be modified and are always read as 1 Bit 0 Bus Release Enable BRLE Enables or disables release of the bus to an external device Bit 0 BRLE Description 0 The bus cannot be released to an external device BREQ and BACK can be used as input output pins Initial value 1 The bus can be released to ...

Page 126: ... 0 No idle cycle inserted in case of consecutive external read and write cycles 1 Idle cycle inserted in case of consecutive external read and write cycles Initial value Bits 5 to 3 Reserved must not be set to 1 These bits can be read and written but must not be set to 1 Normal operation cannot be guaranteed if 1 is written in these bits Bit 2 Reserved must not be set to 0 This bit can be read and...

Page 127: ...hip select signal CS7 to CS4 output regardless of any other settings 0 Initial value 0 0 0 1 1 1 1 Read Write R W R W R W R W 7 6 5 4 3 2 1 0 Reserved bits CS7E CS6E CS5E CS4E Chip select 7 to 4 enable These bits enable or disable chip select signal output Bit CSCR is initialized to H 0F by a reset and in hardware standby mode It is not initialized in software standby mode Bits 7 to 4 Chip Select ...

Page 128: ...4 3 2 1 0 Reserved bits Address control Selects address update mode 1 or address update mode 2 Bit ADRCR is initialized to H FF by a reset and in hardware standby mode It is not initialized in software standby mode Bits 7 to 1 Reserved Read only bits always read as 1 Bit 0 Address Control ADRCTL Selects the address output method Bit 0 ADRCTL Description 0 Address update mode 2 is selected 1 Addres...

Page 129: ...a 5 128 kbytes Area 6 128 kbytes Area 7 128 Mbytes H 000000 H 1FFFFF H 200000 H 3FFFFF H 400000 H 5FFFFF H 600000 H 7FFFFF H 800000 H 9FFFFF H A00000 H BFFFFF H C00000 H DFFFFF H E00000 H FFFFFF Area 0 2 Mbytes Area 1 2 Mbytes Area 2 2 Mbytes Area 3 2 Mbytes Area 4 2 Mbytes Area 5 2 Mbytes Area 6 2 Mbytes Area 7 2 Mbytes a 1 Mbyte modes modes 1 and 2 b 16 Mbyte modes modes 3 and 4 Figure 6 2 Acces...

Page 130: ...a 7 1 93 Mbytes Internal I O registers 1 Area 7 67 5 kbytes On chip RAM 4 kbytes Internal I O registers 2 Area 7 22 bytes Area 0 2 Mbytes Area 1 2 Mbytes Area 2 8 Mbytes Area 3 2 Mbytes Area 4 1 93 Mbytes Area 5 4 kbytes On chip RAM 4 kbytes Internal I O registers 2 Area 7 22 bytes Area 6 23 75 kbytes Internal I O registers 1 2 Mbytes 2 Mbytes 2 Mbytes 2 Mbytes 2 Mbytes 2 Mbytes 2 Mbytes 2 Mbytes ...

Page 131: ...s States Two or three access states can be selected with ASTCR An area for which two state access is selected functions as a two state access space and an area for which three state access is selected functions as a three state access space When two state access space is designated wait insertion is disabled Number of Program Wait States When three state access space is designated in ASTCR the num...

Page 132: ...put state and pins CS1 to CS3 in the input state To output chip select signals CS1 to CS3 the corresponding DDR bits must be set to 1 In the expanded modes with on chip ROM enabled a reset leaves pins CS0 to CS3 in the input state To output chip select signals CS0 to CS3 the corresponding DDR bits must be set to 1 For details see section 7 I O Ports Output of CS4 to CS7 Output of CS4 to CS7 is ena...

Page 133: ... Addresses are always updated between bus cycles Address Update Mode 2 In address update mode 2 address updating is performed only in external space accesses In this mode the address can be retained between an external space read cycle and an instruction fetch cycle on chip memory by placing the program in on chip memory Address update mode 2 is therefore useful when connecting a device that requi...

Page 134: ... is used an external space read access must be completed within a single access cycle For example in a word access to 8 bit access space the bus cycle is split into two as shown in figure 6 6 and so there is not a single access cycle In this case address holding is not guaranteed at the rise of RD between the first even address and second odd address access cycles area inside the ellipse in the fi...

Page 135: ...tes data alignment control for 8 bit access space With 8 bit access space the upper data bus D15 to D8 is always used for accesses The amount of data that can be accessed at one time is one byte a word access is performed as two byte accesses and a longword access as four byte accesses D15 D8 D7 D0 Upper data bus Lower data bus 1st bus cycle 2nd bus cycle 1st bus cycle 2nd bus cycle 3rd bus cycle ...

Page 136: ... RD signal is valid for both the upper and the lower half of the data bus In a write the HWR signal is valid for the upper half of the data bus and the LWR signal for the lower half Table 6 4 Data Buses Used and Valid Strobes Area Access Size Read Write Address Valid Strobe Upper Data Bus D15 to D8 Lower Data Bus D7 to D0 8 bit access Byte Read RD Valid Invalid area Write HWR Undetermined data 16 ...

Page 137: ...6 is 128 kbytes in modes 1 and 2 and 2 Mbytes in modes 3 and 4 Area 7 Area 7 includes the on chip RAM and internal I O registers In the H8 3008 the space excluding the on chip RAM and I O registers is external space The on chip RAM is enabled when the RAME bit in the system control register SYSCR is set to 1 when the RAME bit is cleared to 0 the on chip RAM is disabled and the corresponding space ...

Page 138: ...ta bus D15 to D8 is used in accesses to these areas The LWR pin is always high Wait states can be inserted Bus cycle External address in area n Valid Invalid Valid Undetermined data High φ Address bus CSn AS RD D15 to D8 D7 to D0 HWR LWR D15 to D8 D7 to D0 Read access Write access Note n 7 to 0 T1 T2 T3 Figure 6 9 Bus Control Signal Timing for 8 Bit Three State Access Area ...

Page 139: ...used in accesses to these areas The LWR pin is always high Wait states cannot be inserted Bus cycle External address in area n Valid Invalid Valid Undetermined data High φ Address bus CSn AS RD D15 to D8 D7 to D0 HWR LWR D15 to D8 D7 to D0 Read access Write access Note n 7 to 0 T1 T2 Figure 6 10 Bus Control Signal Timing for 8 Bit Two State Access Area ...

Page 140: ... addresses and the lower data bus D7 to D0 in accesses to odd addresses Wait states can be inserted Bus cycle Even external address in area n Valid Invalid Valid High φ Address bus CSn AS RD D15 to D8 D7 to D0 HWR LWR D15 to D8 D7 to D0 Read access Write access Note n 7 to 0 T1 T2 T3 Undetermined data Figure 6 11 Bus Control Signal Timing for 16 Bit Three State Access Area 1 Byte Access to Even Ad...

Page 141: ...valid Valid φ Address bus CSn AS RD D15 to D8 D7 to D0 HWR LWR D15 to D8 D7 to D0 Read access Write access Note n 7 to 0 T1 T2 T3 High Undetermined data Figure 6 12 Bus Control Signal Timing for 16 Bit Three State Access Area 2 Byte Access to Odd Address ...

Page 142: ...area n Valid Valid φ Address bus CSn AS RD D15 to D8 D7 to D0 HWR LWR D15 to D8 D7 to D0 Read access Write access Note n 7 to 0 T1 T2 T3 Valid Valid Figure 6 13 Bus Control Signal Timing for 16 Bit Three State Access Area 3 Word Access ...

Page 143: ...addresses and the lower data bus D7 to D0 in accesses to odd addresses Wait states cannot be inserted Bus cycle Even external address in area n Valid Invalid Valid High φ Address bus CSn AS RD D15 to D8 D7 to D0 HWR LWR D15 to D8 D7 to D0 Read access Write access Note n 7 to 0 T1 T2 Undetermined data Figure 6 14 Bus Control Signal Timing for 16 Bit Two State Access Area 1 Byte Access to Even Addre...

Page 144: ... Invalid Valid High φ Address bus CSn AS RD D15 to D8 D7 to D0 HWR LWR D15 to D8 D7 to D0 Read access Write access Note n 7 to 0 T1 T2 Undetermined data Figure 6 15 Bus Control Signal Timing for 16 Bit Two State Access Area 2 Byte Access to Odd Address ...

Page 145: ...ea 3 Word Access 6 4 6 Wait Control When accessing external space the H8 3008 can extend the bus cycle by inserting wait states Tw There are two ways of inserting wait states program wait insertion and pin wait insertion using the WAIT pin Program Wait Insertion From 0 to 3 wait states can be inserted automatically between the T2 state and T3 state on an individual area basis in three state access...

Page 146: ...til it goes high This is useful when inserting four or more TW states or when changing the number of TW states for different external devices The WAITE bit setting applies to all areas Figure 6 17 shows an example of the timing for insertion of one program wait state in 3 state space φ WAIT Address bus Data bus Read access Write access Data bus AS RD T1 T2 Tw Tw Tw T3 HWR LWR Note indicates the ti...

Page 147: ...a read cycle from ROM with a long output floating time and bus cycle B is a read cycle from SRAM each being located in a different area In a an idle cycle is not inserted and a collision occurs in bus cycle B between the read data from ROM and that from SRAM In b an idle cycle is inserted and a data collision is prevented φ T1 T2 T3 RD T1 T2 φ T1 T2 T3 Ti T2 T1 Address bus Data bus RD Address bus ...

Page 148: ...wed by a write cycle for a different external area while the ICIS0 bit is cleared to 0 negation of RD in the first read cycle and assertion of CSn in the following bus cycle will occur simultaneously Depending on the output delay time of each signal therefore it is possible that the RD low output in the previous read cycle and the CSn low output in the following bus cycle will overlap As long as R...

Page 149: ...grant the bus to a bus master which can the operate using the bus The bus arbiter checks whether the bus request signal from a bus master is active or inactive and returns an acknowledge signal to the bus master When two or more bus masters request the bus the highest priority bus master receives an acknowledge signal The bus master that receives an acknowledge signal can continue to use the bus u...

Page 150: ...d to an external bus master The external bus master has highest priority and requests the bus right from the bus arbiter driving the BREQ signal low Once the external bus master acquires the bus it keeps the bus until the BREQ signal goes high While the bus is released to an external bus master the H8 3008 chip holds the address bus data bus bus control signals AS RD HWR and LWR and chip select si...

Page 151: ...edance High impedance High impedance Figure 6 21 Example of External Bus Master Operation When making a transition to software standby mode if there is contention with a bus request from an external bus master the BACK and strobe states may be indefinite when the transition is made When using software standby mode clear the BRLE bit to 0 in BRCR before executing the SLEEP instruction ...

Page 152: ... DDR and CSCR Write Timing Data written to DDR or CSCR for the port corresponding to the CSn pin to switch between CSn output and generic input takes effect starting from the T3 state of the DDR write cycle Figure 6 23 shows the timing when the CS1 pin is changed from generic input to CS1 output φ T1 T2 T3 CS1 Address bus High impedance P8DDR address Figure 6 23 DDR Write Timing BRCR Write Timing ...

Page 153: ...After driving the BREQ pin low hold it low until BACK goes low If BREQ returns to the high level before BACK goes lows the bus arbiter may operate incorrectly To terminate the external bus released state hold the BREQ signal high for at least three states If BREQ is high for too short an interval the bus arbiter may operate incorrectly ...

Page 154: ...138 ...

Page 155: ... P80 PA7 to PA0 have Schmitt trigger input circuits For block diagrams of the ports see appendix C I O Port Block Diagrams Table 7 1 Port Functions Expanded Modes Port Description Pins Mode 1 Mode 2 Mode 3 Mode 4 Port 4 8 bit I O port Built in input pull up transistors P47 to P40 D7 to D0 Data input output D7 to D0 and 8 bit generic input output 8 bit bus mode generic input output 16 bit bus mode ...

Page 156: ...0 P93 RxD1 P92 RxD0 P91 TxD1 P90 TxD0 Input and output SCK1 SCK0 RxD1 RxD0 TxD1 TxD0 for serial communication interfaces 1 and 0 SCI1 0 IRQ5 and IRQ4 input and 6 bit generic input output Port A 8 bit I O port Schmitt inputs PA7 TP7 TIOCB2 A20 Output TP7 from pro grammable timing pattern controller TPC input or output TIOCB2 for 16 bit timer and generic input output Address output A20 PA6 TP6 TIOCA...

Page 157: ...utput PB3 TP11 TMIO3 CS4 PB2 TP10 TMO2 CS5 PB1 TP9 TMIO1 CS6 PB0 TP8 TMO0 CS7 TPC output TP11 to TP8 8 bit timer input and output TMIO3 TMO2 TMIO1 TMO0 CS7 to CS4 output and generic input output Legend SCI0 Serial communication interface channel 0 SCI1 Serial communication interface channel 1 TPC Programmable timing pattern controller 16TIM 16 bit timer 8TIM 8 bit timer ...

Page 158: ...he chip operates in 16 bit bus mode and port 4 becomes part of the data bus Port 4 has software programmable built in pull up transistors Pins in port 4 can drive one TTL load and a 90 pF capacitive load They can also drive a darlington transistor pair Port 4 P4 D P4 D P4 D P4 D P4 D P4 D P4 D P4 D 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 P4 input output D7 input output P4 input output D6 input output P4 i...

Page 159: ...WCR selecting 8 bit bus mode port 4 functions as an input output port In this case a pin in port 4 becomes an output port if the corresponding P4DDR bit is set to 1 and an input port if this bit is cleared to 0 When at least one area is designated as a 16 bit access area selecting 16 bit bus mode port 4 functions as part of the data bus regardless of the P4DDR settings P4DDR is a write only regist...

Page 160: ... MOS control 7 to 0 These bits control input pull up transistors built into port 4 7 6 P4 PCR 0 R W 6 5 P4 PCR 0 R W 5 4 P4 PCR 0 R W 4 3 P4 PCR 0 R W 3 2 P4 PCR 0 R W 2 1 P4 PCR 0 R W 1 0 P4 PCR 0 R W 0 In 8 bit bus mode in modes 1 to 4 expanded modes when a P4DDR bit is cleared to 0 selecting generic input if the corresponding P4PCR bit is set to 1 the input pull up transistor is turned on P4PCR...

Page 161: ...D AS BACK BREQ WAIT Port 6 pins Modes 1 to 4 expanded modes P67 input φ output LWR output HWR output RD output AS output P62 input output BACK output P61 input output BREQ input P60 input output WAIT input Figure 7 2 Port 6 Pin Configuration 7 3 2 Register Descriptions Table 7 4 summarizes the registers of port 6 Table 7 4 Port 6 Registers Address Name Abbreviation R W Initial Value H EE005 Port 6...

Page 162: ...omes an output port if the corresponding P6DDR bit is set to 1 and an input port if this bit is cleared to 0 Port 6 Data Register P6DR P6DR is an 8 bit readable writable register that stores output data for port 6 When port 6 functions as an output port the value of this register is output For bit 7 a value of 1 is returned if the bit is read while the PSTOP bit in MSTCRH is cleared to 0 and the P...

Page 163: ...he setting of bit P64DDR P64DDR 0 1 Pin function RD output AS Functions as AS regardless of the setting of bit P63DDR P63DDR 0 1 Pin function AS output P62 BACK Bit BRLE in BRCR and bit P62DDR select the pin function as follows BRLE 0 1 P62DDR 0 1 Pin function P62 input P62 output BACK output P61 BREQ Bit BRLE in BRCR and bit P61DDR select the pin function as follows BRLE 0 1 P61DDR 0 1 Pin functi...

Page 164: ... converter analog output pins Port 7 P7 input AN input DA output P7 input AN input DA output P7 input AN input P7 input AN input P7 input AN input P7 input AN input P7 input AN input P7 input AN input 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Port 7 pins 1 0 Figure 7 3 Port 7 Pin Configuration 7 4 2 Register Description Table 7 6 summarizes the port 7 register Port 7 is an input port and port 7 has no data ...

Page 165: ...f pin functions in expanded modes See section 14 A D Converter for a description of the A D converter s ADTRG input pin The IRQ3 to IRQ0 functions are selected by IER settings regardless of whether the pin is used for input or output Caution is therefore required For details see section 5 3 1 External Interrupts Pins in port 8 can drive one TTL load and a 90 pF capacitive load They can also drive ...

Page 166: ...output pins When bits in P8DDR are cleared to 0 the corresponding pins become input ports In the H8 3008 following a reset P84 functions as the CS0 output while CS1 to CS3 are input ports P8DDR is a write only register Its value cannot be read All bits return 1 when read P8DDR is initialized to H F0 by a reset and in hardware standby mode In software standby mode P8DDR retains its previous setting...

Page 167: ...lue Read Write 7 1 6 1 5 1 4 P8 0 R W 4 3 P8 0 R W 3 2 P8 0 R W 2 1 P8 0 R W 1 0 P8 0 R W 0 Reserved bits Port 8 data 4 to 0 These bits store data for port 8 pins P8DR is initialized to H E0 by a reset and in hardware standby mode In software standby mode it retains its previous setting ...

Page 168: ...ction as follows ADTRG P83DDR 0 1 Pin function P83 input CS1 output IRQ3 input ADTRG input P82 CS2 IRQ2 Bit P82DDR selects the pin function as follows P82DDR 0 1 Pin function P82 input CS2 output IRQ2 input P81 CS3 IRQ1 Bit P81DDR selects the pin function as follows P81DDR 0 1 Pin function P81 input CS3 output IRQ1 input P80 IRQ0 Bit P80DDR selects the pin function as follows P80DDR 0 1 Pin functi...

Page 169: ...odes Figure 7 5 shows the pin configuration of port 9 Pins in port 9 can drive one TTL load and a 30 pF capacitive load They can also drive a darlington transistor pair Port 9 P9 input output SCK P9 input output SCK P9 input output RxD input P9 input output RxD input P9 input output TxD output P9 input output TxD output 5 4 3 2 1 0 Port 9 pins 1 0 input output IRQ input input output IRQ input 5 4 ...

Page 170: ...ode In software standby mode it retains its previous setting Therefore if a transition is made to software standby mode while port 9 is functioning as an input output port and a P9DDR bit is set to 1 the corresponding pin maintains its output state Port 9 Data Register P9DR P9DR is an 8 bit readable writable register that stores output data for port 9 When port 9 functions as an output port the va...

Page 171: ...CKE0 and CKE1 in SCR and bit P94DDR select the pin function as follows CKE1 0 1 C A 0 1 CKE0 0 1 P94DDR 0 1 Pin function P94 input P94 output SCK0 output SCK0 output SCK0 input IRQ4 input P93 RxD1 Bit RE in SCR of SCI1 bit SMIF in SCMR and bit P93DDR select the pin function as follows SMIF 0 1 RE 0 1 P93DDR 0 1 Pin function P93 input P93 output RxD1 input RxD1 input P92 RxD0 Bit RE in SCR of SCI0 ...

Page 172: ... also used for output TP7 to TP0 from the programmable timing pattern controller TPC input and output TIOCB2 TIOCA2 TIOCB1 TIOCA1 TIOCB0 TIOCA0 TCLKD TCLKC TCLKB TCLKA by the 16 bit timer clock input TCLKD TCLKC TCLKB TCLKA to the 8 bit timer and address output A23 to A20 A reset or hardware standby transition leaves port A as an input port except that in modes 3 and 4 one pin is always used for A...

Page 173: ...CA input output A output PA input output TP output TIOCB input output A output PA input output TP output TIOCA input output A output PA input output TP output TIOCB input output TCLKD input PA input output TP output TIOCA input output TCLKC input PA input output TP output TCLKB input PA input output TP output TCLKA input 6 5 4 3 2 1 0 2 1 1 0 0 20 21 22 23 Figure 7 6 Port A Pin Configuration 7 7 2...

Page 174: ...ot be read All bits return 1 when read PADDR is initialized to H 00 by a reset and in hardware standby mode in modes 1 and 2 It is initialized to H 80 by a reset and in hardware standby mode in modes 3 and 4 In software standby mode it retains its previous setting Therefore if a transition is made to software standby mode while port A is functioning as an input output port and a PADDR bit is set t...

Page 175: ...ut PA7 output TP7 output TIOCB2 input Note TIOCB2 input when IOB2 1 and PWM2 0 16 bit timer channel 2 settings 2 1 2 IOB2 0 1 IOB1 0 0 1 IOB0 0 1 PA6 TP6 TIOCA2 Bit PWM2 in TMDR bits IOA2 to IOA0 in TIOR2 bit NDER6 in NDERA and bit PA6DDR select the pin function as follows 16 bit timer channel 2 settings 1 in table below 2 in table below PA6DDR 0 1 1 NDER6 0 1 Pin function TIOCA2 output PA6 input ...

Page 176: ...t TIOCB1 input Note TIOCB1 input when IOB2 1 and PWM1 0 16 bit timer channel 1 settings 2 1 2 IOB2 0 1 IOB1 0 0 1 IOB0 0 1 PA4 TP4 TIOCA1 Bit PWM1 in TMDR bits IOA2 to IOA0 in TIOR1 bit NDER4 in NDERA and bit PA4DDR select the pin function as follows 16 bit timer channel 1 settings 1 in table below 2 in table below PA4DDR 0 1 1 NDER4 0 1 Pin function TIOCA1 output PA4 input PA4 output TP4 output T...

Page 177: ...to IOA0 in TIOR2 bit NDER6 in NDERA bit A21E in BRCR and bit PA6DDR select the pin function as follows A21E 1 0 16 bit timer channel 2 settings 1 in table below 2 in table below PA6DDR 0 1 1 NDER6 0 1 Pin function TIOCA2 output PA6 input PA6 output TP6 output A21 output TIOCA2 input Note TIOCA2 input when IOA2 1 16 bit timer channel 2 settings 2 1 2 1 PWM2 0 1 IOA2 0 1 IOA1 0 0 1 IOA0 0 1 ...

Page 178: ...t TIOCB1 input Note TIOCB1 input when IOB2 1 and PWM1 0 16 bit timer channel 1 settings 2 1 2 IOB2 0 1 IOB1 0 0 1 IOB0 0 1 PA4 TP4 TIOCA1 A23 Bit PWM1 in TMDR bits IOA2 to IOA0 in TIOR1 bit NDER4 in NDERA bit A23E in BRCR and bit PA4DDR select the pin function as follows A23E 1 0 16 bit timer channel 1 settings 1 in table below 2 in table below PA4DDR 0 1 1 NDER4 0 1 Pin function TIOCA1 output PA4...

Page 179: ...pin function as follows 16 bit timer channel 0 settings 1 in table below 2 in table below PA3DDR 0 1 1 NDER3 0 1 Pin function TIOCB0 output PA3 input PA3 output TP3 output TIOCB0 input 1 TCLKD input 2 Notes 1 TIOCB0 input when IOB2 1 and PWM0 0 2 TCLKD input when TPSC2 TPSC1 TPSC0 1 in any of 16TCR2 to 16TCR0 or bits CKS2 to CKS0 in 8TCR2 are as shown in 3 in the table below 16 bit timer channel 0...

Page 180: ... bit timer channel 0 settings 1 in table below 2 in table below PA2DDR 0 1 1 NDER2 0 1 Pin function TIOCA0 output PA2 input PA2 output TP2 output TIOCA0 input 1 TCLKC input 2 Notes 1 TIOCA0 input when IOA2 1 2 TCLKC input when TPSC2 TPSC1 1 and TPSC0 0 in any of 16TCR2 to 16TCR0 or bits CKS2 to CKS0 in 8TCR0 are as shown in 3 in the table below 16 bit timer channel 0 settings 2 1 2 1 PWM0 0 1 IOA2...

Page 181: ...CKS2 to CKS0 in 8TCR3 are as shown in 1 in the table below 8 bit timer channel 3 settings 2 1 CKS2 0 1 CKS1 0 1 CKS0 0 1 PA0 TP0 TCLKA Bit MDF in TMDR bits TPSC2 to TPSC0 in 16TCR2 to 16TCR0 of the 16 bit timer bits CKS2 to CKS0 in 8TCR1 of the 8 bit timer bit NDER0 in NDERA and bit PA0DDR select the pin function as follows PA0DDR 0 1 NDER0 0 1 Pin function PA0 input PA0 output TP0 output TCLKA in...

Page 182: ...ic input output Figure 7 7 shows the pin configuration of port B Pins in port B can drive one TTL load and a 30 pF capacitive load They can also drive darlington transistor pair Port B PB7 TP15 PB6 TP14 PB5 TP13 PB4 TP12 PB3 TP TMIO3 CS4 11 PB2 TP TMO2 CS5 10 PB1 TP TMIO1 CS6 9 PB0 TP TMO0 CS7 8 Port B pins PB7 input output TP15 output PB6 input output TP14 output PB5 input output TP13 output PB4 ...

Page 183: ... bits select input or output for port B pins 7 6 PB DDR 0 W 6 5 PB DDR 0 W 5 4 PB DDR 0 W 4 3 PB DDR 0 W 3 2 PB DDR 0 W 2 1 PB DDR 0 W 1 0 PB DDR 0 W 0 For the method of selecting the pin functions see table 7 16 When port B functions as an input output port a pin in port B becomes an output port if the corresponding PBDDR bit is set to 1 and an input port if this bit is cleared to 0 PBDDR is a wr...

Page 184: ...of the corresponding PBDR bit is returned When a bit in PBDDR is cleared to 0 if port B is read the corresponding pin logic level is read Bit Initial value Read Write 0 PB 0 R W 0 1 PB 0 R W 1 2 PB 0 R W 2 3 PB 0 R W 3 4 PB 0 R W 4 5 PB 0 R W 5 6 PB 0 R W 6 7 PB 0 R W 7 Port B data 7 to 0 These bits store data for port B pins PBDR is initialized to H 00 by a reset and in hardware standby mode In s...

Page 185: ...nd bit PB5DDR select the pin function as follows PB5DDR 0 1 1 NDER13 0 1 Pin function PB5 input PB5 output TP13 output PB4 TP12 Bit NDER12 in NDERB and bit PB4DDR select the pin function as follows PB4DDR 0 1 1 NDER12 0 1 Pin function PB4 input PB4 output TP12 output PB3 TP11 TMIO3 CS4 Bits OIS3 2 and OS1 0 in 8TCSR3 bits CCLR1 0 in 8TCR3 bit CS4E in CSCR bit NDER11 in NDERB and bit PB3DDR select ...

Page 186: ...1 bits CCLR1 0 in 8TCR1 bit CS6E in CSCR bit NDER9 in NDERB and bit PB1DDR select the pin function as follows OIS3 2 and OS1 0 All 0 Not all 0 CS6E 0 1 PB1DDR 0 1 1 NDER9 0 1 Pin function PB1 input PB1 output TP9 output CS6 output TMIO1 output TMIO1 input Note TMIO1 input when bit ICE 1 in 8TCSR1 PB0 TP8 TMO0 CS7 Bits OIS3 2 and OS1 0 in 8TCSR0 bit CS7E in CSCR bit NDER8 in NDERB and bit PB0DDR se...

Page 187: ...g edge falling edge or both edges selectable Counter clearing function Counters can be cleared by compare match or input capture Synchronization Two or more timer counters 16TCNTs can be preset simultaneously or cleared simultaneously by compare match or input capture Counter synchronization enables synchronous register input and output PWM mode PWM output can be provided with an arbitrary duty cy...

Page 188: ...pare match or input capture GRA1 GRB1 compare match or input capture GRA2 GRB2 compare match or input capture Initial output value setting function Available Available Available Compare 0 Available Available Available match output 1 Available Available Available Toggle Available Available Not available Input capture function Available Available Available Synchronization Available Available Availab...

Page 189: ...TCLKA to TCLKD φ φ 2 φ 4 φ 8 Clock selector Control logic TIOCA0 to TIOCA2 TIOCB0 to TIOCB2 TSTR TSNR TMDR TOLR TISRA TISRB TISRC Legend TSTR Timer start register 8 bits TSNR Timer synchro register 8 bits TMDR Timer mode register 8 bits TOLR Timer output level setting register 8 bits TISRA Timer interrupt status register A 8 bits TISRB Timer interrupt status register B 8 bits TISRC Timer interrupt...

Page 190: ...arator Control logic TCLKA to TCLKD φ φ 2 φ 4 φ 8 TIOCA0 TIOCB0 IMIA0 IMIB0 OVI0 16TCNT GRA GRB 16TCR TIOR Module data bus Legend 16TCNT GRA GRB TCR TIOR Timer counter 16 bits General registers A and B input capture output compare registers 16 bits 2 Timer control register 8 bits Timer I O control register 8 bits Figure 8 2 Block Diagram of Channels 0 and 1 ...

Page 191: ...φ 2 φ 4 φ 8 TIOCA2 TIOCB2 IMIA2 IMIB2 OVI2 16TCNT2 GRA2 GRB2 16TCR2 TIOR2 Module data bus Legend 16TCNT2 GRA2 GRB2 TCR2 TIOR2 Timer counter 2 16 bits General registers A2 and B2 input capture output compare registers 16 bits 2 Timer control register 2 8 bits Timer I O control register 2 8 bits Figure 8 3 Block Diagram of Channel 2 ...

Page 192: ...in 0 Input capture output compare A0 TIOCA0 Input output GRA0 output compare or input capture pin PWM output pin in PWM mode Input capture output compare B0 TIOCB0 Input output GRB0 output compare or input capture pin 1 Input capture output compare A1 TIOCA1 Input output GRA1 output compare or input capture pin PWM output pin in PWM mode Input capture output compare B1 TIOCB1 Input output GRB1 out...

Page 193: ... H 88 0 H FFF68 Timer control register 0 16TCR0 R W H 80 H FFF69 Timer I O control register 0 TIOR0 R W H 88 H FFF6A Timer counter 0H 16TCNT0H R W H 00 H FFF6B Timer counter 0L 16TCNT0L R W H 00 H FFF6C General register A0H GRA0H R W H FF H FFF6D General register A0L GRA0L R W H FF H FFF6E General register B0H GRB0H R W H FF H FFF6F General register B0L GRB0L R W H FF 1 H FFF70 Timer control regis...

Page 194: ... indicated 2 Only 0 can be written in bits 3 to 0 to clear the flags 8 2 Register Descriptions 8 2 1 Timer Start Register TSTR TSTR is an 8 bit readable writable register that starts and stops the timer counter 16TCNT in channels 0 to 2 Bit Initial value Read Write 7 1 6 1 5 1 4 1 3 1 2 STR2 0 R W 1 STR1 0 R W 0 STR0 0 R W Reserved bits Counter start 2 to 0 These bits start and stop 16TCNT2 to 16T...

Page 195: ...nized by setting the corresponding bits to 1 Bit Initial value Read Write 7 1 6 1 5 1 4 1 3 1 2 SYNC2 0 R W 1 SYNC1 0 R W 0 SYNC0 0 R W Reserved bits Timer sync 2 to 0 These bits synchronize channels 2 to 0 TSNC is initialized to H F8 by a reset and in standby mode Bits 7 to 3 Reserved These bits cannot be modified and are always read as 1 Bit 2 Timer Sync 2 SYNC2 Selects whether channel 2 operate...

Page 196: ...et and cleared independently of other channels 1 Channel 0 operates synchronously 16TCNT0 can be synchronously preset and cleared 8 2 3 Timer Mode Register TMDR TMDR is an 8 bit readable writable register that selects PWM mode for channels 0 to 2 It also selects phase counting mode and the overflow flag OVF setting conditions for channel 2 Bit Initial value Read Write 7 1 6 MDF 0 R W 5 FDIR 0 R W ...

Page 197: ...n Low High High Low In phase counting mode external clock edge selection by bits CKEG1 and CKEG0 in 16TCR2 and counter clock selection by bits TPSC2 to TPSC0 are invalid and the above phase counting mode operations take precedence The counter clearing condition selected by the CCLR1 and CCLR0 bits in 16TCR2 and the compare match input capture settings and interrupt functions of TIOR2 TISRA TISRB T...

Page 198: ...n PWM mode Bit 1 PWM1 Description 0 Channel 1 operates normally Initial value 1 Channel 1 operates in PWM mode When bit PWM1 is set to 1 to select PWM mode pin TIOCA1 becomes a PWM output pin The output goes to 1 at compare match with GRA1 and to 0 at compare match with GRB1 Bit 0 PWM Mode 0 PWM0 Selects whether channel 0 operates normally or in PWM mode Bit 0 PWM0 Description 0 Channel 0 operates...

Page 199: ...A0 These bits enable or disable interrupts by the IMFA flags Input capture compare match flags A2 to A0 Status flags indicating GRA compare match or input capture Note Only 0 can be written to clear the flag TISRA is initialized to H 88 by a reset and in standby mode Bit 7 Reserved This bit cannot be modified and is always read as 1 Bit 6 Input Capture Compare Match Interrupt Enable A2 IMIEA2 Enab...

Page 200: ... Bit 4 IMIEA0 Description 0 IMIA0 interrupt requested by IMFA0 flag is disabled Initial value 1 IMIA0 interrupt requested by IMFA0 flag is enabled Bit 3 Reserved This bit cannot be modified and is always read as 1 Bit 2 Input Capture Compare Match Flag A2 IMFA2 This status flag indicates GRA2 compare match or input capture events Bit 2 IMFA2 Description 0 Clearing condition Initial value Read IMFA...

Page 201: ...lue is transferred to GRA1 by an input capture signal when GRA1 functions as an input capture register Bit 0 Input Capture Compare Match Flag A0 IMFA0 This status flag indicates GRA0 compare match or input capture events Bit 0 IMFA0 Description 0 Clearing condition Initial value Read IMFA0 flag when IMFA0 1 then write 0 in IMFA0 flag 1 Setting conditions 16TCNT0 GRA0 when GRA0 functions as an outp...

Page 202: ...B0 These bits enable or disable interrupts by the IMFB flags Input capture compare match flags B2 to B0 Status flags indicating GRB compare match or input capture Note Only 0 can be written to clear the flag TISRB is initialized to H 88 by a reset and in standby mode Bit 7 Reserved This bit cannot be modified and is always read as 1 Bit 6 Input Capture Compare Match Interrupt Enable B2 IMIEB2 Enab...

Page 203: ... Bit 4 IMIEB0 Description 0 IMIB0 interrupt requested by IMFB0 flag is disabled Initial value 1 IMIB0 interrupt requested by IMFB0 flag is enabled Bit 3 Reserved This bit cannot be modified and is always read as 1 Bit 2 Input Capture Compare Match Flag B2 IMFB2 This status flag indicates GRB2 compare match or input capture events Bit 2 IMFB2 Description 0 Clearing condition Initial value Read IMFB...

Page 204: ...lue is transferred to GRB1 by an input capture signal when GRB1 functions as an input capture register Bit 0 Input Capture Compare Match Flag B0 IMFB0 This status flag indicates GRB0 compare match or input capture events Bit 0 IMFB0 Description 0 Clearing condition Initial value Read IMFB0 flag when IMFB0 1 then write 0 in IMFB0 flag 1 Setting conditions 16TCNT0 GRB0 when GRB0 functions as an outp...

Page 205: ...ote Only 0 can be written to clear the flag TISRC is initialized to H 88 by a reset and in standby mode Bit 7 Reserved This bit cannot be modified and is always read as 1 Bit 6 Overflow Interrupt Enable 2 OVIE2 Enables or disables the interrupt requested by the OVF2 when OVF2 flag is set to 1 Bit 6 OVIE2 Description 0 OVI2 interrupt requested by OVF2 flag is disabled Initial value 1 OVI2 interrupt...

Page 206: ...condition 16TCNT2 overflowed from H FFFF to H 0000 or underflowed from H 0000 to H FFFF Note 16TCNT underflow occurs when 16TCNT operates as an up down counter Underflow occurs only when channel 2 operates in phase counting mode MDF 1 in TMDR Bit 1 Overflow Flag 1 OVF1 This status flag indicates 16TCNT1 overflow Bit 1 OVF1 Description 0 Clearing condition Initial value Read OVF1 flag when OVF1 1 t...

Page 207: ...urce is selected by bits TPSC2 to TPSC0 in 16TCR 16TCNT0 and 16TCNT1 are up counters 16TCNT2 is an up down counter in phase counting mode and an up counter in other modes 16TCNT can be cleared to H 0000 by compare match with GRA or GRB or by input capture to GRA or GRB counter clearing function When 16TCNT overflows changes from H FFFF to H 0000 the OVF flag is set to 1 in TISRC of the correspondi...

Page 208: ... as an output compare register its value is constantly compared with the 16TCNT value When the two values match compare match the IMFA or IMFB flag is set to 1 in TISRA TISRB Compare match output can be selected in TIOR When a general register is used as an input capture register an external input capture signal are detected and the current 16TCNT value is stored in the general register The corres...

Page 209: ...ad Write 7 1 6 CCLR1 0 R W 5 CCLR0 0 R W 4 CKEG1 0 R W 3 CKEG0 0 R W 0 TPSC0 0 R W 2 TPSC2 0 R W 1 TPSC1 0 R W Timer prescaler 2 to 0 These bits select the timer counter clock Reserved bit Clock edge 1 0 These bits select external clock edges Counter clear 1 0 These bits select the counter clear source Each 16TCR is an 8 bit readable writable register that selects the timer counter clock source se...

Page 210: ...ure register 2 Selected in TSNC Bits 4 and 3 Clock Edge 1 and 0 CKEG1 CKEG0 These bits select external clock input edges when an external clock source is used Bit 4 CKEG1 Bit 3 CKEG0 Description 0 0 Count rising edges Initial value 1 Count falling edges 1 Count both edges When channel 2 is set to phase counting mode bits CKEG1 and CKEG0 in 16TCR2 are ignored Phase counting takes precedence Bits 2 ...

Page 211: ...gisters Some functions differ in PWM 1 TIOR1 mode 2 TIOR2 Bit Initial value Read Write 7 1 6 IOB2 0 R W 5 IOB1 0 R W 4 IOB0 0 R W 3 1 0 IOA0 0 R W 2 IOA2 0 R W 1 IOA1 0 R W I O control A2 to A0 These bits select GRA functions Reserved bit I O control B2 to B0 These bits select GRB functions Reserved bit Each TIOR is an 8 bit readable writable register that selects the output compare or input captu...

Page 212: ...re match When this setting is made 1 output is selected automatically Bit 3 Reserved This bit cannot be modified and is always read as 1 Bits 2 to 0 I O Control A2 to A0 IOA2 to IOA0 These bits select the GRA function Bit 2 IOA2 Bit 1 IOA1 Bit 0 IOA0 Function 0 0 0 GRA is an output No output at compare match Initial value 1 compare register 0 output at GRA compare match 1 1 0 1 output at GRA compa...

Page 213: ...TIOCB2 to TIOCB0 A TOLR setting can only be made when the corresponding bit in TSTR is 0 TOLR is a write only register and cannot be read If it is read all bits will return a value of 1 TOLR is initialized to H C0 by a reset and in standby mode Bits 7 and 6 Reserved These bits cannot be modified Bit 5 Output Level Setting B2 TOB2 Sets the value of timer output TIOCB2 Bit 5 TOB2 Description 0 TIOCB...

Page 214: ...Sets the value of timer output TIOCA1 Bit 2 TOA1 Description 0 TIOCA1 is 0 Initial value 1 TIOCA1 is 1 Bit 1 Output Level Setting B0 TOB0 Sets the value of timer output TIOCB0 Bit 0 TOB0 Description 0 TIOCB0 is 0 Initial value 1 TIOCB0 is 1 Bit 0 Output Level Setting A0 TOA0 Sets the value of timer output TIOCA0 Bit 0 TOA0 Description 0 TIOCA0 is 0 Initial value 1 TIOCA0 is 1 ...

Page 215: ...a time or a byte at a time Figures 8 4 and 8 5 show examples of word read write access to a timer counter 16TCNT Figures 8 6 to 8 9 show examples of byte read write access to 16TCNTH and 16TCNTL On chip data bus CPU H L Bus interface H L Module data bus 16TCNTH 16TCNTL Figure 8 4 16TCNT Access Operation CPU 16TCNT Word On chip data bus CPU H L Bus interface H L Module data bus 16TCNTH 16TCNTL Figu...

Page 216: ...CPU Writes to 16TCNTH Upper Byte On chip data bus CPU H L Bus interface H L Module data bus 16TCNTH 16TCNTL Figure 8 7 Access to Timer Counter L CPU Writes to 16TCNTL Lower Byte On chip data bus CPU H L Bus interface H L Module data bus 16TCNTH 16TCNTL Figure 8 8 Access to Timer Counter H CPU Reads 16TCNTH Upper Byte ...

Page 217: ...registers These registers are linked to the CPU by an internal 8 bit data bus Figures 8 10 and 8 11 show examples of byte read and write access to a 16TCR If a word size data transfer instruction is executed two byte transfers are performed On chip data bus CPU H L Bus interface H L Module data bus 16TCR Figure 8 10 16TCR Access CPU Writes to 16TCR On chip data bus CPU H L Bus interface H L Module...

Page 218: ... A PWM waveform is output from the TIOCA pin The output goes to 1 at compare match A and to 0 at compare match B The duty cycle can be varied from 0 to 100 depending on the settings of GRA and GRB When a channel is set to PWM mode its GRA and GRB automatically become output compare registers Phase Counting Mode The phase relationship between two clock signals input at TCLKA and TCLKB is detected a...

Page 219: ...TPSC0 in 16TCR to select the counter clock source If an external clock source is selected set bits CKEG1 and CKEG0 in 16TCR to select the desired edge s of the external clock signal 2 For periodic counting set CCLR1 and CCLR0 in 16TCR to have 16TCNT cleared at GRA compare match or GRB compare match 3 Set TIOR to select the output compare function of GRA or GRB whichever was selected in step 2 4 Wr...

Page 220: ...at channel 16TCNT operates as a periodic counter Select the output compare function of GRA or GRB set bit CCLR1 or CCLR0 in 16TCR to have the counter cleared by compare match and set the count period in GRA or GRB After these settings the counter starts counting up as a periodic counter when the corresponding bit is set to 1 in TSTR When the count matches GRA or GRB the IMFA or IMFB flag is set to...

Page 221: ...A to TCLKD can be selected by bits TPSC2 to TPSC0 in 16TCR and the detected edge by bits CKEG1 and CKEG0 The rising edge falling edge or both edges can be selected The pulse width of the external clock signal must be at least 1 5 system clocks when a single edge is selected and at least 2 5 system clocks when both edges are selected Shorter pulses will not be counted correctly Figure 8 16 shows th...

Page 222: ...tup Select waveform output mode Set output timing Start counter Waveform output Select the compare match output mode 0 1 or toggle in TIOR When a waveform output mode is selected the pin switches from its generic input output function to the output compare function TIOCA or TIOCB An output compare pin outputs the value set in TOLR until the first compare match occurs Set a value in GRA or GRB to d...

Page 223: ...not change Time H FFFF GRB TIOCB TIOCA GRA No change No change No change No change 1 output 0 output 16TCNT value H 0000 Figure 8 18 0 and 1 Output TOA 1 TOB 0 Figure 8 19 shows examples of toggle output 16TCNT operates as a periodic counter cleared by compare match B Toggle output is selected for both compare match A and B GRB TIOCB TIOCA GRA 16TCNT value Time Counter cleared by compare match wit...

Page 224: ...ral register the compare match signal is not generated until the next counter clock pulse Figure 8 20 shows the output compare timing N 1 N N φ 16TCNT input clock 16TCNT GR Compare match signal TIOCA TIOCB Figure 8 20 Output Compare Output Timing Input Capture Function The 16TCNT value can be transferred to a general register when an input edge is detected at an input capture input output compare ...

Page 225: ... input capture signal Clear the DDR bit to 0 before making these TIOR settings Set the STR bit to 1 in TSTR to start the timer counter 1 2 1 2 Figure 8 21 Setup Procedure for Input Capture Example Examples of input capture Figure 8 22 illustrates input capture when the falling edge of TIOCB and both edges of TIOCA are selected as capture edges 16TCNT is cleared by input capture into GRB H 0005 H 0...

Page 226: ...T GRA GRB Figure 8 23 Input Capture Signal Timing 8 4 3 Synchronization The synchronization function enables two or more timer counters to be synchronized by writing the same data to them simultaneously synchronous preset With appropriate 16TCR settings two or more timer counters can also be cleared simultaneously synchronous clear Synchronization enables additional general registers to be associa...

Page 227: ... to 16TCNT Synchronous clear Clearing synchronized to this channel Select counter clear source Start counter Counter clear Synchronous clear Start counter Select counter clear source Yes No Figure 8 24 Setup Procedure for Synchronization Example Example of Synchronization Figure 8 25 shows an example of synchronization Channels 0 1 and 2 are synchronized and are set to operate in PWM mode Channel ...

Page 228: ...e time at which the PWM output changes to 0 If either GRA or GRB compare match is selected as the counter clear source a PWM waveform with a duty cycle from 0 to 100 is output at the TIOCA pin PWM mode can be selected in all channels 0 to 2 Table 8 4 summarizes the PWM output pins and corresponding registers If the same value is set in GRA and GRB the output does not change when compare match occu...

Page 229: ...ime at which the PWM waveform should go to 0 in GRB Set the PWM bit in TMDR to select PWM mode When PWM mode is selected regardless of the TIOR contents GRA and GRB become output compare registers specifying the times at which the PWM output goes to 1 and 0 The TIOCA pin automatically becomes the PWM output pin The TIOCB pin conforms to the settings of bits IOB1 and IOB0 in TIOR If TIOCB output is...

Page 230: ... with GRB In the examples shown 16TCNT is cleared by compare match with GRA or GRB Synchronized operation and free running counting are also possible 16TCNT value Counter cleared by compare match A Time GRA GRB TIOCA a Counter cleared by GRA TOA 1 16TCNT value Counter cleared by compare match B Time GRB GRA TIOCA b Counter cleared by GRB TOA 0 H 0000 H 0000 Figure 8 27 PWM Mode Example 1 ...

Page 231: ...cle is 0 If the counter is cleared by compare match with GRA and GRB is set to a higher value than GRA the duty cycle is 100 16TCNT value Counter cleared by compare match B Time GRB GRA TIOCA a 0 duty cycle TOA 0 16TCNT value Counter cleared by compare match A Time GRA GRB TIOCA b 100 duty cycle TOA 1 Write to GRA Write to GRA Write to GRB Write to GRB H 0000 H 0000 Figure 8 28 PWM Mode Example 2 ...

Page 232: ...SRB TISRC setting of STR2 bit in TSTR GRA2 and GRB2 are valid The input capture and output compare functions can be used and interrupts can be generated Phase counting is available only in channel 2 Sample Setup Procedure for Phase Counting Mode Figure 8 29 shows a sample procedure for setting up phase counting mode Phase counting mode Select phase counting mode Select flag setting condition Start...

Page 233: ...lso be at least 1 5 states and the pulse width must be at least 2 5 states 16TCNT2 value Counting up Counting down TCLKB TCLKA Figure 8 30 Operation in Phase Counting Mode Example Table 8 5 Up Down Counting Conditions Counting Direction Up Counting Down Counting TCLKB pin High Low HIgh Low TCLKA pin Low High Low HIgh TCLKA TCLKB Phase difference Phase difference Pulse width Pulse width Overlap Ove...

Page 234: ...fied arbitrarily by making a setting in TOLR Figure 8 32 shows the timing for setting the initial value with TOLR Only write to TOLR when the corresponding bit in TSTR is cleared to 0 T1 TOLR address N N T2 T3 Address bus φ TOLR 16 bit timer output pin Figure 8 32 Timing for Setting 16 Bit Timer Output Level by Writing to TOLR ...

Page 235: ...hes a general register GR The compare match signal is generated in the last state in which the values match when 16TCNT is updated from the matching count to the next count Therefore when 16TCNT matches a general register the compare match signal is not generated until the next 16TCNT clock input Figure 8 33 shows the timing of the setting of IMFA and IMFB φ 16TCNT GR IMF IMI 16TCNT input clock Co...

Page 236: ...FB are set to 1 by an input capture signal The 16TCNT contents are simultaneously transferred to the corresponding general register Figure 8 34 shows the timing Input capture signal N N φ IMF 16TCNT GR IMI Figure 8 34 Timing of Setting of IMFA and IMFB by Input Capture ...

Page 237: ...timing Overflow signal φ 16TCNT OVF OVI Figure 8 35 Timing of Setting of OVF 8 5 2 Timing of Clearing of Status Flags If the CPU reads a status flag while it is set to 1 then writes 0 in the status flag the status flag is cleared Figure 8 36 shows the timing φ Address IMF OVF TISR write cycle TISR address T1 T2 T3 Figure 8 36 Timing of Clearing of Status Flags ...

Page 238: ...riority registers A IPRA For details see section 5 Interrupt Controller Table 8 6 lists the interrupt sources Table 8 6 16 bit timer Interrupt Sources Channel Interrupt Source Description Priority 0 IMIA0 IMIB0 OVI0 Compare match input capture A0 Compare match input capture B0 Overflow 0 High 1 IMIA1 IMIB1 OVI1 Compare match input capture A1 Compare match input capture B1 Overflow 1 2 IMIA2 IMIB2 ...

Page 239: ...16TCNT Write and Clear If a counter clear signal occurs in the T3 state of a 16TCNT write cycle clearing of the counter takes priority and the write is not performed See figure 8 37 φ Address bus Internal write signal Counter clear signal 16TCNT 16TCNT write cycle 16TCNT address N H 0000 T1 T2 T3 Figure 8 37 Contention between 16TCNT Write and Clear ...

Page 240: ...CNT word write cycle writing takes priority and 16TCNT is not incremented Figure 8 38 shows the timing in this case φ Address bus Internal write signal 16TCNT input clock 16TCNT N 16TCNT address M 16TCNT write data 16TCNT word write cycle T1 T2 T3 Figure 8 38 Contention between 16TCNT Word Write and Increment ...

Page 241: ...a for which a write was not performed is not incremented and retains its pre write value See figure 8 39 which shows an increment pulse occurring in the T2 state of a byte write to 16TCNTH φ Address bus Internal write signal 16TCNT input clock 16TCNTH 16TCNTL 16TCNTH byte write cycle T1 T2 T3 N 16TCNTH address M 16TCNT write data X X X 1 Figure 8 39 Contention between 16TCNT Byte Write and Increme...

Page 242: ... write cycle writing takes priority and the compare match signal is inhibited See figure 8 40 φ Address bus Internal write signal 16TCNT GR Compare match signal General register write cycle T1 T2 T3 N GR address M N N 1 General register write data Inhibited Figure 8 40 Contention between General Register Write and Compare Match ...

Page 243: ...riting takes priority and the counter is not incremented OVF is set to 1 The same holds for underflow See figure 8 41 φ Address bus Internal write signal 16TCNT input clock Overflow signal 16TCNT OVF H FFFF 16TCNT address M 16TCNT write data 16TCNT write cycle T1 T2 T3 Figure 8 41 Contention between 16TCNT Write and Overflow ...

Page 244: ...g the T3 state of a general register read cycle the value before input capture is read See figure 8 42 φ Address bus Internal read signal Input capture signal GR Internal data bus GR address X General register read cycle T1 T2 T3 X M Figure 8 42 Contention between General Register Read and Input Capture ...

Page 245: ...is cleared according to the input capture signal The counter is not incremented by the increment signal The value before the counter is cleared is transferred to the general register See figure 8 43 φ Input capture signal Counter clear signal 16TCNT input clock 16TCNT GR N N H 0000 Figure 8 43 Contention between Counter Clearing by Input Capture and Counter Increment ...

Page 246: ...general register write cycle input capture takes priority and the write to the general register is not performed See figure 8 44 φ Address bus Internal write signal Input capture signal 16TCNT GR M GR address General register write cycle T1 T2 T3 M Figure 8 44 Contention between General Register Write and Input Capture ...

Page 247: ...n channels are synchronized if a 16TCNT value is modified by byte write access all 16 bits of all synchronized counters assume the same value as the counter that was addressed Example When channels 1 and 2 are synchronized Byte write to channel 1 or byte write to channel 2 16TCNT1 16TCNT2 W Y X Z 16TCNT1 16TCNT2 A A X X 16TCNT1 16TCNT2 Y Y A A 16TCNT1 16TCNT2 W Y X Z 16TCNT1 16TCNT2 A A B B Word w...

Page 248: ... IOB2 0 Other bits unrestricted Input capture A PWM0 0 IOA2 1 Other bits unrestricted Input capture B PWM0 0 IOB2 1 Other bits unrestricted Counter By compare CCLR1 0 clearing match input CCLR0 1 capture A By compare CCLR1 1 match input CCLR0 0 capture B Syn SYNC0 1 CCLR1 1 chronous CCLR0 1 clear Legend Setting available valid Setting does not affect this mode Note The input capture function canno...

Page 249: ...bits unrestricted Input capture A PWM1 0 IOA2 1 Other bits unrestricted Input capture B PWM1 0 IOB2 1 Other bits unrestricted Counter By compare CCLR1 0 clearing match input CCLR0 1 capture A By compare CCLR1 1 match input CCLR0 0 capture B Syn SYNC1 1 CCLR1 1 chronous CCLR0 1 clear Legend Setting available valid Setting does not affect this mode Note The input capture function cannot be used in P...

Page 250: ...cted Input capture A PWM2 0 IOA2 1 Other bits unrestricted Input capture B PWM2 0 IOB2 1 Other bits unrestricted Counter By compare CCLR1 0 clearing match input CCLR0 1 capture A By compare CCLR1 1 match input CCLR0 0 capture B Syn SYNC2 1 CCLR1 1 chronous CCLR0 1 clear Phase counting MDF 1 mode Legend Setting available valid Setting does not affect this mode Note The input capture function cannot...

Page 251: ...nabling use as an external event counter Selection of three ways to clear the counters The counters can be cleared on compare match A or B or input capture B Timer output controlled by two compare match signals The timer output signal in each channel is controlled by two independent compare match signals enabling the timer to generate output waveforms with an arbitrary duty cycle or PWM output A D...

Page 252: ...ure sources four overflow sources Two of the compare match sources and two of the combined compare match input capture sources each have an independent interrupt vector The remaining compare match interrupts combined compare match input capture interrupts and overflow interrupts have one interrupt vector for two sources ...

Page 253: ...RA1 8TCNT1 TCORB1 8TCSR1 8TCR1 TCLKA TCLKC 8TCNT0 Legend TCORA Time constant register A TCORB Time constant register B 8TCNT Timer counter 8TCSR Timer control status register 8TCR Timer control register External clock sources Internal clock sources Clock select Control logic Clock 1 Clock 0 Compare match A1 Compare match A0 Overflow 1 Overflow 0 Compare match B1 Compare match B0 Input capture B1 C...

Page 254: ...r clock input TCLKC Input Counter external clock input 1 Timer input output TMIO1 I O Compare match output input capture input Timer clock input TCLKA Input Counter external clock input 1 2 Timer output TMO2 Output Compare match output Timer clock input TCLKD Input Counter external clock input 3 Timer input output TMIO3 I O Compare match output input capture input Timer clock input TCLKB Input Cou...

Page 255: ... 2 H 10 H FFF94 Time constant register A2 TCORA2 R W H FF H FFF96 Time constant register B2 TCORB2 R W H FF H FFF98 Timer counter 2 8TCNT2 R W H 00 3 H FFF91 Timer control register 3 8TCR3 R W H 00 H FFF93 Timer control status register 3 8TCSR3 R W 2 H 00 H FFF95 Time constant register A3 TCORA3 R W H FF H FFF97 Time constant register B3 TCORB3 R W H FF H FFF99 Timer counter 3 8TCNT3 R W H 00 Note...

Page 256: ... increment on pulses generated from an internal or external clock source The clock source is selected by clock select bits 2 to 0 CKS2 to CKS0 in the timer control register 8TCR The CPU can always read or write to the timer counters The 8TCNT0 and 8TCNT1 pair and the 8TCNT2 and 8TCNT3 pair can each be accessed as a 16 bit register by word access 8TCNT can be cleared by an input capture signal or c...

Page 257: ... 1 1 R W 0 1 R W TCORA2 TCORA3 Bit Initial value Read Write Bit Initial value Read Write The TCORA0 and TCORA1 pair and the TCORA2 and TCORA3 pair can each be accessed as a 16 bit register by word access The TCORA value is constantly compared with the 8TCNT value When a match is detected the corresponding compare match flag A CMFA is set to 1 in 8TCSR The timer output can be freely controlled by t...

Page 258: ...e TCORB value is constantly compared with the 8TCNT value When a match is detected the corresponding compare match flag B CMFB is set to 1 in 8TCSR The timer output can be freely controlled by these compare match signals and the settings of output input capture edge select bits 3 and 2 OIS3 OIS2 in 8TCSR When TCORB is used for input capture it stores the 8TCNT value on detection of an external inp...

Page 259: ...errupt request when the CMFB flag is set to 1 in 8TCSR Bit 7 CMIEB Description 0 CMIB interrupt requested by CMFB is disabled Initial value 1 CMIB interrupt requested by CMFB is enabled Bit 6 Compare Match Interrupt Enable A CMIEA Enables or disables the CMIA interrupt request when the CMFA flag is set to 1 in 8TCSR Bit 6 CMIEA Description 0 CMIA interrupt requested by CMFA is disabled Initial val...

Page 260: ...are not cleared by compare match B Bits 2 to 0 Clock Select 2 to 0 CSK2 to CSK0 These bits select whether the clock input to 8TCNT is an internal or external clock Three internal clocks can be selected all divided from the system clock φ φ 8 φ 64 and φ 8192 The rising edge of the selected internal clock triggers the count When use of an external clock is selected three types of count can be select...

Page 261: ...ount on 8TCNT3 overflow signal 2 Channel 3 compare match count mode Count on 8TCNT2 compare match A 2 1 External clock counted on rising edge 1 0 External clock counted on falling edge 1 External clock counted on both rising and falling edges Notes 1 If the clock input of channel 0 is the 8TCNT1 overflow signal and that of channel 1 is the 8TCNT0 compare match signal no incrementing clock is gener...

Page 262: ... Read Write 7 CMFB 0 R W 6 CMFA 0 R W 5 OVF 0 R W 4 ICE 0 R W 3 OIS3 0 R W 0 OS0 0 R W 2 OIS2 0 R W 1 OS1 0 R W 8TCSR1 8TCSR3 Note Only 0 can be written to bits 7 to 5 to clear these flags Bit Initial value Read Write The timer control status registers 8TCSR are 8 bit registers that indicate compare match input capture and overflow statuses and control compare match output input capture edge selec...

Page 263: ...hen bit ICE is set to 1 in 8TCSR1 and 8TCSR3 the CMFB flag is not set when 8TCNT0 TCORB0 or 8TCNT2 TCORB2 Bit 6 Compare Match Flag A CMFA Status flag that indicates the occurrence of a TCORA compare match Bit 6 CMFA Description 0 Clearing condition Initial value Read CMFA when CMFA 1 then write 0 in CMFA 1 Setting condition 8TCNT TCORA Bit 5 Timer Overflow Flag OVF Status flag that indicates that ...

Page 264: ...led and A D converter start requests by compare match A are disabled 1 A D converter start requests by compare match A are enabled and A D converter start requests by external trigger pin ADTRG input are disabled Note TRGE is bit 7 of the A D control register ADCR Bit 4 Reserved In 8TCSR1 This bit is a reserved bit but can be read and written Bit 4 Input Capture Enable ICE In 8TCSR1 and 8TCSR3 Sel...

Page 265: ... input capture TMIO1 is dedicated input capture pin CMIB1 interrupt request generated by input capture Table 9 4 Operation of Channels 2 and 3 when Bit ICE is Set to 1 in 8TCSR3 Register Register Register Function Status Flag Change Timer Output Capture Input Interrupt Request TCORA2 Compare match operation CMFA changed from 0 to 1 in 8TCSR2 by compare match TMO2 output controllable CMIA2 interrup...

Page 266: ...r function is used the timer output priority order is toggle output 1 output 0 output If compare match A and B occur simultaneously the output changes in accordance with the higher priority compare match When bits OIS3 OIS2 OS1 and OS0 are all cleared to 0 timer output is disabled Bits 1 and 0 Output Select A1 and A0 OS1 OS0 These bits select the compare match A output level Bit 1 OS1 Bit 0 OS0 De...

Page 267: ... 8TCNT Figures 9 4 to 9 7 show the operation in byte read and write accesses to 8TCNT0 and 8TCNT1 8TCNT0 8TCNT1 H L H L C P U Internal data bus Bus interface Module data bus Figure 9 2 8TCNT Access Operation CPU Writes to 8TCNT Word 8TCNT0 8TCNT1 H L H L C P U Internal data bus Bus interface Module data bus Figure 9 3 8TCNT Access Operation CPU Reads 8TCNT Word 8TCNTH0 8TCNTL1 H L H L C P U Intern...

Page 268: ...tion CPU Writes to 8TCNT1 Lower Byte 8TCNT0 8TCNT1 H L H L C P U Internal data bus Bus interface Module data bus Figure 9 6 8TCNT0 Access Operation CPU Reads 8TCNT0 Upper Byte 8TCNT0 8TCNT1 H L H L C P U Internal data bus Bus interface Module data bus Figure 9 7 8TCNT1 Access Operation CPU Reads 8TCNT1 Lower Byte ...

Page 269: ...the 8 bit timer the same operation will not be performed since the incrementing edge is different in each case Figure 9 8 Count Timing for Internal Clock Input External Clock Three incrementation methods can be selected by setting bits CKS2 to CKS0 in 8TCR on the rising edge the falling edge and both rising and falling edges The pulse width of the external clock signal must be at least 1 5 system ...

Page 270: ...re Match Timing Timer Output Timing When compare match A or B occurs the timer output is as specified by the OIS3 OIS2 OS1 and OS0 bits in 8TCSR unchanged 0 output 1 output or toggle output Figure 9 10 shows the timing when the output is set to toggle on compare match A φ Compare match A signal Timer output Figure 9 10 Timing of Timer Output ...

Page 271: ... can be cleared when input capture B occurs Figure 9 12 shows the timing of this operation φ Input capture signal Input capture input 8TCNT N H 00 Figure 9 12 Timing of Clear by Input Capture 9 4 3 Input Capture Signal Timing Input capture on the rising edge falling edge or both edges can be selected by settings in 8TCSR Figure 9 13 shows the timing when the rising edge is selected The pulse width...

Page 272: ...te of the match when the matched 8TCNT count value is updated Therefore after the 8TCNT and TCORA or TCORB values match the compare match signal is not generated until an incrementing clock pulse signal is generated Figure 9 14 shows the timing in this case φ CMF Compare match signal 8TCNT N N 1 N TCOR Figure 9 14 CMF Flag Setting Timing when Compare Match Occurs Timing of CMFB Flag Setting when I...

Page 273: ...0 are set to 100 in either 8TCR0 or 8TCR1 the 8 bit timers of channels 0 and 1 are cascaded With this configuration the two timers can be used as a single 16 bit timer 16 bit timer mode or channel 0 8 bit timer compare matches can be counted in channel 1 compare match count mode Similarly if bits CKS2 to CKS0 are set to 100 in either 8TCR2 or 8TCR3 the 8 bit timers of channels 2 and 3 are cascaded...

Page 274: ...counter clear on compare match or input capture has been selected by the CCLR1 and CCLR0 bits in 8TCR0 the 16 bit counter both 8TCNT0 and 8TCNT1 is cleared The settings of the CCLR1 and CCLR0 bits in 8TCR1 are ignored The lower 8 bits cannot be cleared independently OVF Flag Operation The OVF flag is set to 1 in 8TCSR0 when the 16 bit counter 8TCNT0 and 8TCNT1 overflows from H FFFF to H 0000 The O...

Page 275: ...from H FF to H 00 Compare Match Count Mode Channels 0 and 1 When bits CKS2 to CKS0 are set to 100 in 8TCR1 8TCNT1 counts channel 0 compare match A events CMF flag setting interrupt generation TMO pin output counter clearing and so on is in accordance with the settings for each channel Note When bit ICE 1 in 8TCSR1 the compare match register function of TCORB0 in channel 0 cannot be used Channels 2...

Page 276: ...en TCORB1 in channel 1 is used for input capture TCORB0 in channel 0 cannot be used as a compare match register Similarly when TCORB3 in channel 3 is used for input capture TCORB2 in channel 2 cannot be used as a compare match register Setting Input Capture Operation in 16 Bit Count Mode Channels 0 and 1 In 16 bit count mode TCORB0 and TCORB1 function as a 16 bit input capture register when the IC...

Page 277: ... CMIA Interrupt by CMFA CMIB Interrupt by CMFB TOVI Interrupt by OVF Low For compare match interrupts CMIA1 CMIB1 and CMIA3 CMIB3 and the overflow interrupts TOVI0 TOVI1 and TOVI2 TOVI3 one vector is shared by two interrupts Table 9 6 lists the interrupt sources Table 9 6 8 Bit Timer Interrupt Sources Channel Interrupt Source Description 0 CMIA0 TCORA0 compare match CMIB0 TCORB0 compare match inpu...

Page 278: ...8 Bit Timer Application Example Figure 9 17 shows how the 8 bit timer module can be used to output pulses with any desired duty cycle The settings for this example are as follows Clear the CCLR1 bit to 0 and set the CCLR0 bit to 1 in 8TCR so that 8TCNT is cleared by a TCORA compare match Set bits OIS3 OIS2 OS1 and OS0 to 0110 in 8TCSR so that 1 is output on a TCORA compare match and 0 is output on...

Page 279: ...a timer counter clear signal occurs in the T3 state of a 8TCNT write cycle clearing of the counter takes priority and the write is not performed Figure 9 18 shows the timing in this case φ Address bus 8TCNT address Internal write signal Counter clear signal 8TCNT N H 00 T1 T3 T2 8TCNT write cycle Figure 9 18 Contention between 8TCNT Write and Clear ...

Page 280: ...te of a 8TCNT write cycle writing takes priority and 8TCNT is not incremented Figure 9 19 shows the timing in this case φ Address bus 8 TCNT address Internal write signal 8TCNT input clock 8TCNT N M T1 T3 T2 8TCNT write cycle 8TCNT write data Figure 9 19 Contention between 8TCNT Write and Increment ...

Page 281: ... cycle writing takes priority and the compare match signal is inhibited Figure 9 20 shows the timing in this case φ Address bus TCOR address Internal write signal 8TCNT TCOR N M T1 T3 T2 TCOR write cycle TCOR write data N N 1 Compare match signal Inhibited Figure 9 20 Contention between TCOR Write and Compare Match ...

Page 282: ...e T3 state of a TCOR read cycle the value before input capture is read Figure 9 21 shows the timing in this case φ Address bus TCORB address Internal read signal Input capture signal TCORB N M T1 T3 T2 TCORB read cycle Internal data bus N Figure 9 21 Contention between TCOR Read and Input Capture ...

Page 283: ...earing by the input capture signal takes priority and the counter is not incremented The value before the counter is cleared is transferred to TCORB Figure 9 22 shows the timing in this case φ Counter clear signal 8TCNT internal clock 8TCNT N X H 00 T1 T3 T2 Input capture signal TCORB N Figure 9 22 Contention between Counter Clearing by Input Capture and Counter Increment ...

Page 284: ...te of a TCOR write cycle input capture takes priority and the write to TCOR is not performed Figure 9 23 shows the timing in this case φ Address bus TCOR address Internal write signal Input capture signal 8TCNT M T1 T3 T2 TCOR write cycle TCOR M X Figure 9 23 Contention between TCOR Write and Input Capture ...

Page 285: ...a for which a write was not performed is incremented Figure 9 24 shows the timing when an increment pulse occurs in the T2 state of a byte write to 8TCNT upper byte If an increment pulse occurs in the T2 state on the other hand the increment takes priority φ Address bus 8TCNTH address Internal write signal 8TCNT input clock 8TCNT upper byte N N 1 8TCNT write data T1 T3 T2 8TCNT upper byte byte wri...

Page 286: ...ng internal clock sources may cause 8TCNT to increment depending on the switchover timing Table 9 8 shows the relation between the time of the switchover by writing to bits CKS1 and CKS0 and the operation of 8TCNT The 8TCNT input clock is generated from the internal clock source by detecting the rising edge of the internal clock If a switchover is made from a low clock source to a high clock sourc...

Page 287: ...igh high switchover 1 Old clock source New clock source 8TCNT clock 8TCNT CKS bits rewritten N N 1 2 High low switchover 2 Old clock source New clock source 8TCNT clock 8TCNT CKS bits rewritten N N 1 N 2 3 Low high switchover 3 Old clock source New clock source 8TCNT clock 8TCNT CKS bits rewritten N N 1 N 2 4 ...

Page 288: ...ts rewritten N N 1 N 2 Notes 1 Including switchovers from the high level to the halted state and from the halted state to the high level 2 Including switchover from the halted state to the low level 3 Including switchover from the low level to the halted state 4 The switchover is regarded as a rising edge causing 8TCNT to increment ...

Page 289: ...ly and independently 10 1 1 Features TPC features are listed below 16 bit output data Maximum 16 bit data can be output TPC output can be enabled on a bit by bit basis Four output groups Output trigger signals can be selected in 4 bit groups to provide up to four different 4 bit outputs Selectable output trigger signals Output trigger signals can be selected for each group from the compare match s...

Page 290: ... Legend TPMR TPCR NDERB NDERA PBDDR PADDR NDRB NDRA PBDR PADR Pulse output pins group 2 Pulse output pins group 1 Pulse output pins group 0 TPC output mode register TPC output control register Next data enable register B Next data enable register A Port B data direction register Port A data direction register Next data register B Next data register A Port B data register Port A data register NDRB ...

Page 291: ... TP2 Output TPC output 3 TP3 Output TPC output 4 TP4 Output Group 1 pulse output TPC output 5 TP5 Output TPC output 6 TP6 Output TPC output 7 TP7 Output TPC output 8 TP8 Output Group 2 pulse output TPC output 9 TP9 Output TPC output 10 TP10 Output TPC output 11 TP11 Output TPC output 12 TP12 Output Group 3 pulse output TPC output 13 TP13 Output TPC output 14 TP14 Output TPC output 15 TP15 Output ...

Page 292: ...data enable register A NDERA R W H 00 H FFFA5 H FFFA7 3 Next data register A NDRA R W H 00 H FFFA4 H FFFA6 3 Next data register B NDRB R W H 00 Notes 1 Lower 20 bits of the address in advanced mode 2 Bits used for TPC output cannot be written 3 The NDRA address is H FFFA5 when the same output trigger is selected for TPC output groups 0 and 1 by settings in TPCR When the output triggers are differe...

Page 293: ...TP0 Bits corresponding to pins used for TPC output must be set to 1 For further information about PADDR see section 7 11 Port A 10 2 2 Port A Data Register PADR PADR is an 8 bit readable writable register that stores TPC output data for groups 0 and 1 when these TPC output groups are used Bit Initial value Read Write 0 PA 0 R W 0 1 PA 0 R W 1 2 PA 0 R W 2 3 PA 0 R W 3 4 PA 0 R W 4 5 PA 0 R W 5 6 P...

Page 294: ...esponding to pins used for TPC output must be set to 1 For further information about PBDDR see section 7 12 Port B 10 2 4 Port B Data Register PBDR PBDR is an 8 bit readable writable register that stores TPC output data for groups 2 and 3 when these TPC output groups are used Bit Initial value Read Write 0 PB 0 R W 0 1 PB 0 R W 1 2 PB 0 R W 2 3 PB 0 R W 3 4 PB 0 R W 4 5 PB 0 R W 5 6 PB 0 R W 6 7 P...

Page 295: ...ed in software standby mode Same Trigger for TPC Output Groups 0 and 1 If TPC output groups 0 and 1 are triggered by the same compare match event the NDRA address is H FFFA5 The upper 4 bits belong to group 1 and the lower 4 bits to group 0 Address H FFFA7 consists entirely of reserved bits that cannot be modified and always read 1 Address H FFFA5 Bit Initial value Read Write 0 NDR0 0 R W 1 NDR1 0...

Page 296: ...4 of address H FFFA7 are reserved bits that cannot be modified and always read 1 Address H FFFA5 Bit Initial value Read Write 0 1 1 1 2 1 3 1 4 NDR4 0 R W 5 NDR5 0 R W 6 NDR6 0 R W 7 NDR7 0 R W Next data 7 to 4 These bits store the next output data for TPC output group 1 Reserved bits Address H FFFA7 Bit Initial value Read Write 0 NDR0 0 R W 1 NDR1 0 R W 2 NDR2 0 R W 3 NDR3 0 R W 4 1 5 1 6 1 7 1 R...

Page 297: ...n software standby mode Same Trigger for TPC Output Groups 2 and 3 If TPC output groups 2 and 3 are triggered by the same compare match event the NDRB address is H FFFA4 The upper 4 bits belong to group 3 and the lower 4 bits to group 2 Address H FFFA6 consists entirely of reserved bits that cannot be modified and always read 1 Address H FFFA4 Bit Initial value Read Write 0 NDR8 0 R W 1 NDR9 0 R W...

Page 298: ... address H FFFA6 are reserved bits that cannot be modified and always read 1 Address H FFFA4 Bit Initial value Read Write 0 1 1 1 2 1 3 1 4 NDR12 0 R W 5 NDR13 0 R W 6 NDR14 0 R W 7 NDR15 0 R W Next data 15 to 12 These bits store the next output data for TPC output group 3 Reserved bits Address H FFFA6 Bit Initial value Read Write 0 NDR8 0 R W 1 NDR9 0 R W 2 NDR10 0 R W 3 NDR11 0 R W 4 1 5 1 6 1 7...

Page 299: ...ontrol register TPCR occurs the NDRA value is automatically transferred to the corresponding PADR bit updating the output value If TPC output is disabled the bit value is not transferred from NDRA to PADR and the output value does not change NDERA is initialized to H 00 by a reset and in hardware standby mode It is not initialized in software standby mode Bits 7 to 0 Next Data Enable 7 to 0 NDER7 ...

Page 300: ...ontrol register TPCR occurs the NDRB value is automatically transferred to the corresponding PBDR bit updating the output value If TPC output is disabled the bit value is not transferred from NDRB to PBDR and the output value does not change NDERB is initialized to H 00 by a reset and in hardware standby mode It is not initialized in software standby mode Bits 7 to 0 Next Data Enable 15 to 8 NDER1...

Page 301: ...at triggers TPC output group 1 TP7 to TP4 Group 0 compare match select 1 and 0 These bits select the compare match event that triggers TPC output group 0 TP3 to TP0 TPCR is initialized to H FF by a reset and in hardware standby mode It is not initialized in software standby mode Bits 7 and 6 Group 3 Compare Match Select 1 and 0 G3CMS1 G3CMS0 These bits select the compare match event that triggers ...

Page 302: ...S0 Description 0 0 TPC output group 1 TP7 to TP4 is triggered by compare match in 16 bit timer channel 0 1 TPC output group 1 TP7 to TP4 is triggered by compare match in 16 bit timer channel 1 1 0 TPC output group 1 TP7 to TP4 is triggered by compare match in 16 bit timer channel 2 1 TPC output group 1 TP7 to TP4 is triggered by compare match in 16 bit timer channel 2 Initial value Bits 1 and 0 Gr...

Page 303: ...overlapping TPC output for group 1 TP to TP Group 0 non overlap Selects non overlapping TPC output for group 0 TP to TP 15 12 11 8 7 4 3 0 The output trigger period of a non overlapping TPC output waveform is set in general register B GRB in the 16 bit timer channel selected for output triggering The non overlap margin is set in general register A GRA The output values change at compare match A an...

Page 304: ...tput in group 2 independent 1 and 0 output at compare match A and B in the selected 16 bit timer channel Bit 1 Group 1 Non Overlap G1NOV Selects normal or non overlapping TPC output for group 1 TP7 to TP4 Bit 1 G1NOV Description 0 Normal TPC output in group 1 output values change at compare match A in the selected 16 bit timer channel Initial value 1 Non overlapping TPC output in group 1 independe...

Page 305: ...arizes the TPC operating conditions DDR NDER Q Q TPC output pin DR NDR C Q D Q D Internal data bus Output trigger signal Figure 10 2 TPC Output Operation Table 10 3 TPC Operating Conditions NDER DDR Pin Function 0 0 Generic input port 1 Generic output port 1 0 Generic input port but the DR bit is a read only bit and when compare match occurs the NDR bit value is transferred to the DR bit 1 TPC pul...

Page 306: ... selected compare match event occurs Figure 10 3 shows the timing of these operations for the case of normal output in groups 2 and 3 triggered by compare match A φ TCNT GRA Compare match A signal NDRB PBDR TP to TP 8 15 N N n m m N 1 n n Figure 10 3 Timing of Transfer of Next Data Register Contents and Output Example ...

Page 307: ...rupt in TISRA Set the initial output values in the DR bits of the input output port pins to be used for TPC output Set the DDR bits of the input output port pins to be used for TPC output to 1 Set the NDER bits of the pins to be used for TPC output to 1 Select the 16 bit timer compare match event to be used as the TPC output trigger in TPCR Set the next TPC output values in the NDR bits Set the ST...

Page 308: ... A interrupt H F8 is written in PBDDR and NDERB and bits G3CMS1 G3CMS0 G2CMS1 and G2CMS0 are set in TPCR to select compare match in the 16 bit timer channel set up in step 1 as the output trigger Output data H 80 is written in NDRB The timer counter in this 16 bit timer channel is started When compare match A occurs the NDRB contents are transferred to PBDR and output The compare match input captu...

Page 309: ...lect the counter clock source with bits TPSC2 to TPSC0 in TCR Select the counter clear source with bits CCLR1 and CCLR0 Enable the IMFA interrupt in TISRA Set the initial output values in the DR bits of the input output port pins to be used for TPC output Set the DDR bits of the input output port pins to be used for TPC output to 1 Set the NDER bits of the pins to be used for TPC output to 1 In TP...

Page 310: ...OV are set to 1 in TPMR to select non overlapping output Output data H 95 is written in NDRB TCNT value Non overlap margin The 16 bit timer channel to be used as the output trigger channel is set up so that GRA and GRB are output compare registers and the counter will be cleared by compare match B The TPC output trigger 1 2 3 4 The timer counter in this 16 bit timer channel is started When compare...

Page 311: ... as well as by compare match If GRA functions as an input capture register in the 16 bit timer channel selected in TPCR TPC output will be triggered by the input capture signal Figure 10 8 shows the timing φ TIOC pin Input capture signal NDR DR N N M Figure 10 8 TPC Output Triggering by Input Capture Example ...

Page 312: ...ged only under conditions in which the output trigger event will not occur 10 4 2 Note on Non Overlapping Output During non overlapping operation the transfer of NDR bit values to DR bits takes place as follows 1 NDR bits are always transferred to DR bits at compare match A 2 At compare match B NDR bits are transferred only if their value is 0 Bits are not transferred if their value is 1 Figure 10...

Page 313: ...he IMFA interrupt service routine write the next data in NDR The next data must be written before the next compare match B occurs Figure 10 10 shows the timing relationships Compare match A Compare match B NDR write NDR NDR write DR 0 1 output 0 1 output 0 output 0 output Do not write to NDR in this interval Do not write to NDR in this interval Write to NDR in this interval Write to NDR in this in...

Page 314: ...298 ...

Page 315: ...low 11 1 1 Features WDT features are listed below Selection of eight counter clock sources φ 2 φ 32 φ 64 φ 128 φ 256 φ 512 φ 2048 or φ 4096 Interval timer option Timer counter overflow generates a reset signal or interrupt The reset signal is generated in watchdog timer operation An interval timer interrupt is generated in interval timer operation Watchdog timer reset signal resets the entire H8 3...

Page 316: ...flow Clock Clock selector Read write control Internal data bus Internal clock sources Legend TCNT TCSR RSTCSR Timer counter Timer control status register Reset control status register Figure 11 1 WDT Block Diagram 11 1 3 Pin Configuration Table 11 1 describes the WDT output pin Table 11 1 WDT Pin Name Abbreviation I O Function Reset output RESO Output External output of the watchdog timer reset si...

Page 317: ...11 2 Register Descriptions 11 2 1 Timer Counter TCNT TCNT is an 8 bit readable and writable up counter Bit Initial value Read Write 7 0 R W 6 0 R W 5 0 R W 4 0 R W 3 0 R W 0 0 R W 2 0 R W 1 0 R W Note The method for writing to TCNT is different from that for general registers to prevent inadvertent overwriting For details see section 11 2 4 Notes on Register Access When the TME bit is set to 1 in ...

Page 318: ...method for writing to TCSR is different from that for general registers to prevent inadvertent overwriting For details see section 11 2 4 Notes on Register Access Only 0 can be written to clear the flag Bits 7 to 5 are initialized to 0 by a reset and in standby mode Bits 2 to 0 are initialized to 0 by a reset In software standby mode bits 2 to 0 are not initialized but retain their previous values...

Page 319: ...TME Selects whether TCNT runs or is halted When WT IT 1 clear the software standby bit SSBY to 0 in SYSCR before setting TME When setting SSBY to 1 TME should be cleared to 0 Bit 5 TME Description 0 TCNT is initialized to H 00 and halted Initial value 1 TCNT is counting Bits 4 and 3 Reserved These bits cannot be modified and are always read as 1 Bits 2 to 0 Clock Select 2 to 0 CKS2 to CKS0 These b...

Page 320: ... Register Access Only 0 can be written in bit 7 to clear the flag Bits 7 and 6 are initialized by input of a reset signal at the RES pin They are not initialized by reset signals generated by watchdog timer overflow Bit 7 Watchdog Timer Reset WRST During watchdog timer operation this bit indicates that TCNT has overflowed and generated a reset signal This reset signal resets the entire H8 3008 chi...

Page 321: ...ore difficult to write The procedures for writing and reading these registers are given below Writing to TCNT and TCSR These registers must be written by a word transfer instruction They cannot be written by byte instructions Figure 11 2 shows the format of data written to TCNT and TCSR TCNT and TCSR both have the same write address The write data must be contained in the lower byte of the written...

Page 322: ...ue into the RSTOE bit 15 8 7 0 H A5 H 00 Address H FFF8E 15 8 7 0 H 5A Write data Address H FFF8E Writing 0 in WRST bit Writing to RSTOE bit Note Lower 20 bits of the address in advanced mode Figure 11 3 Format of Data Written to RSTCSR Reading TCNT TCSR and RSTCSR For reads of TCNT TCSR and RSTCSR address H FFF8C is assigned to TCSR address H FFF8D to TCNT and address H FFF8F to RSTCSR These regi...

Page 323: ... 518 states The watchdog reset signal can be externally output from the RESO pin to reset external system devices The reset signal is output externally for 132 states External output can be enabled or disabled by the RSTOE bit in RSTCSR A watchdog reset has the same vector as a reset generated by input at the RES pin Software can distinguish a RES reset from a watchdog reset by checking the WRST b...

Page 324: ...value Time t Interval timer interrupt Interval timer interrupt Interval timer interrupt Interval timer interrupt WT 0 TME 1 IT H FF H 00 Figure 11 5 Interval Timer Operation 11 3 3 Timing of Setting of Overflow Flag OVF Figure 11 6 shows the timing of setting of the OVF flag The OVF flag is set to 1 when TCNT overflows At the same time a reset signal is generated in watchdog timer operation or an ...

Page 325: ...reset timing The WRST bit is set to 1 when TCNT overflows and OVF is set to 1 At the same time an internal reset signal is generated for the entire H8 3008 chip This internal reset signal clears OVF to 0 but the WRST bit remains set to 1 The reset routine must therefore clear the WRST bit φ TCNT Overflow signal OVF WRST H FF H 00 WDT internal reset Figure 11 7 Timing of Setting of WRST Bit and Int...

Page 326: ... If a timer counter clock pulse is generated during the T3 state of a write cycle to TCNT the write takes priority and the timer count is not incremented See figure 11 8 φ TCNT TCNT N M Counter write data T 3 T 2 T 1 CPU TCNT write cycle Internal write signal TCNT input clock Figure 11 8 Contention between TCNT Write and Count up Changing CKS2 to CKS0 Bit Halt TCNT by clearing the TME bit to 0 in ...

Page 327: ...features are listed below Selection of synchronous or asynchronous mode for serial communication Asynchronous mode Serial data communication is synchronized one character at a time The SCI can communicate with a universal asynchronous receiver transmitter UART asynchronous communication interface adapter ACIA or other chip that employs standard asynchronous communication It can also communicate wi...

Page 328: ...nternal clock from baud rate generator or external clock from the SCK pin Four types of interrupts Transmit data empty transmit end receive data full and receive error interrupts are requested independently Features of the smart card interface are listed below Asynchronous communication Data length 8 bits Parity bits generated and checked Error signal output in receive mode parity error Error sign...

Page 329: ...er RDR Receive data register TSR Transmit shift register TDR Transmit data register SMR Serial mode register SCR Serial control register SSR Serial status register BRR Bit rate register SCMR Smart card mode register Module data bus Bus interface Internal data bus Parity generate Parity check Transmit receive control Baud rate generator Clock External clock φ Figure 12 1 SCI Block Diagram ...

Page 330: ...Function 0 Serial clock pin SCK0 Input output SCI0 clock input output Receive data pin RxD0 Input SCI0 receive data input Transmit data pin TxD0 Output SCI0 transmit data output 1 Serial clock pin SCK1 Input output SCI1 clock input output Receive data pin RxD1 Input SCI1 receive data input Transmit data pin TxD1 Output SCI1 transmit data output ...

Page 331: ... register BRR R W H FF H FFFB2 Serial control register SCR R W H 00 H FFFB3 Transmit data register TDR R W H FF H FFFB4 Serial status register SSR R W 2 H 84 H FFFB5 Receive data register RDR R H 00 H FFFB6 Smart card mode register SCMR R W H F2 1 H FFFB8 Serial mode register SMR R W H 00 H FFFB9 Bit rate register BRR R W H FF H FFFBA Serial control register SCR R W H 00 H FFFBB Transmit data regi...

Page 332: ...nnot read or write RSR directly 12 2 2 Receive Data Register RDR RDR is the register that stores received serial data Bit 7 6 5 4 3 2 1 0 Initial value Read Write R 0 0 0 0 0 0 0 0 R R R R R R R When the SCI has received one byte of serial data it transfers the received data from RSR into RDR for storage completing the receive operation RSR is then ready to receive the next data This double buffer...

Page 333: ...s not load the TDR contents into TSR The CPU cannot read or write RSR directly 12 2 4 Transmit Data Register TDR TDR is an 8 bit register that stores data for serial transmission Bit 7 6 5 4 3 2 1 0 Initial value Read Write R W 1 1 1 1 1 1 1 1 R W R W R W R W R W R W R W When the SCI detects that TSR is empty it moves transmit data written in TDR from TDR into TSR and starts serial transmission Co...

Page 334: ...aracter length in asynchronous mode Parity enable Selects whether a parity bit is added Parity mode Selects even or odd parity Stop bit length Selects the stop bit length Multiprocessor mode Selects the multiprocessor function The CPU can always read and write SMR SMR is initialized to H 00 by a reset and in standby mode Bit 7 Communication Mode C A GSM Mode GM The function of this bit differs for...

Page 335: ... enables or disables the addition of a parity bit to transmit data and the checking of the parity bit in receive data In synchronous mode the parity bit is neither added nor checked regardless of the PE bit setting Bit 5 PE Description 0 Parity bit not added or checked Initial value 1 Parity bit added and checked Note When PE bit is set to 1 an even or odd parity bit is added to transmit data acco...

Page 336: ...top bit with value 1 is added to the end of each transmitted character 2 Two stop bits with value 1 are added to the end of each transmitted character In receiving only the first stop bit is checked regardless of the STOP bit setting If the second stop bit is 1 it is treated as a stop bit If the second stop bit is 0 it is treated as the start bit of the next incoming character Bit 2 Multiprocessor...

Page 337: ...ock source Bit 7 6 5 4 3 2 1 0 TIE RIE TE RE MPIE TEIE CKE1 CKE0 Initial value Read Write R W 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W Transmit end interrupt enable Enables or disables transmit end interrupts TEI Multiprocessor interrupt enable Enables or disables multiprocessor interrupts Receive enable Enables or disables the receiver Transmit enable Enables or disables the transmitter Receiv...

Page 338: ...eceive data from RSR to RDR also enables or disables the receive error interrupt ERI Bit 6 RIE Description 0 Receive data full RXI and receive error ERI interrupt requests are disabled Initial value 1 Receive data full RXI and receive error ERI interrupt requests are enabled Note RXI and ERI interrupt requests can be cleared by reading the value 1 from the RDRF FER PER or ORER flag then clearing t...

Page 339: ...R and ORER status flags in SSR are disabled until data with the multiprocessor bit set to 1 is received Note The SCI does not transfer receive data from RSR to RDR does not detect receive errors and does not set the RDRF FER and ORER flags in SSR When it receives data in which MPB 1 the SCI sets the MPB bit to 1 in SSR automatically clears the MPIE bit to 0 enables RXI and ERI interrupts if the TI...

Page 340: ...for serial clock output 1 0 1 Asynchronous mode Internal clock SCK pin used for clock output 2 Synchronous mode Internal clock SCK pin used for serial clock output 1 0 Asynchronous mode External clock SCK pin used for clock input 3 Synchronous mode External clock SCK pin used for serial clock input 1 1 Asynchronous mode External clock SCK pin used for clock input 3 Synchronous mode External clock ...

Page 341: ...mission Parity error Status flag indicating detection of a receive parity error Framing error FER Error signal status ERS 2 Status flag indicating detection of a receive framing error or flag indicating detection of an error signal Overrun error Status flag indicating detection of a receive overrun error Receive data register full Status flag indicating that data has been received and stored in RD...

Page 342: ...Setting conditions The chip is reset or enters standby mode The TE bit in SCR is cleared to 0 TDR contents are loaded into TSR so new data can be written in TDR Bit 6 Receive Data Register Full RDRF Indicates that RDR contains new receive data Bit 6 RDRF Description 0 RDR does not contain new receive data Initial value Clearing conditions The chip is reset or enters standby mode Read RDRF when RDR...

Page 343: ...cation interface and for the smart card interface Its function is switched with the SMIF bit in SCMR For serial communication interface SMIF bit in SCMR cleared to 0 Indicates that data reception ended abnormally due to a framing error in asynchronous mode Bit 4 FER Description 0 Receiving is in progress or has ended normally 1 Initial value Clearing conditions The chip is reset or enters standby ...

Page 344: ...value Clearing conditions The chip is reset or enters standby mode Read PER when PER 1 then write 0 in PER 1 A receive parity error occurred 2 Setting condition The number of 1s in receive data including the parity bit does not match the even or odd parity setting of O E in SMR Notes 1 Clearing the RE bit to 0 in SCR does not affect the PER flag which retains its previous value 2 When a parity err...

Page 345: ...ad TDRE when TDRE 1 then write 0 in TDRE 1 End of transmission Initial value Setting conditions The chip is reset or enters standby mode The TE bit is cleared to 0 in SCR and the FER ERS bit is also cleared to 0 TDRE is 1 and FER ERS is 0 normal transmission 2 5 etu when GM 0 or 1 0 etu when GM 1 after a 1 byte serial character is transmitted Note etu Elementary time unit time required to transmit...

Page 346: ... 1 12 2 8 Bit Rate Register BRR BRR is an 8 bit register that sets the serial transmit receive bit rate in accordance with the baud rate generator operating clock selected by bits CKS0 and CKS1 in SMR Bit Initial value Read Write 7 R W R W R W R W R W R W R W R W 6 1 1 1 1 1 1 1 1 5 4 3 2 1 0 BRR can be read or written to by the CPU at all times BRR is initialized to H FF by a reset and in standby...

Page 347: ...8 0 7 0 00 0 9 2 34 19200 0 2 8 51 0 2 13 78 0 3 0 00 0 4 2 34 31250 0 1 0 00 0 1 4 86 0 1 22 88 0 2 0 00 38400 0 1 18 62 0 1 14 67 0 1 0 00 φ MHz Bit Rate 3 6864 4 4 9152 5 bit s n N Error n N Error n N Error n N Error 110 2 64 0 70 2 70 0 03 2 86 0 31 2 88 0 25 150 1 191 0 00 1 207 0 16 1 255 0 00 2 64 0 16 300 1 95 0 00 1 103 0 16 1 127 0 00 1 129 0 16 600 0 191 0 00 0 207 0 16 0 255 0 00 1 64 ...

Page 348: ... 00 0 12 0 16 31250 0 5 0 00 0 5 2 40 0 6 5 33 0 7 0 00 38400 0 4 2 34 0 4 0 00 0 5 0 00 0 6 6 99 φ MHz Bit Rate 9 8304 10 12 12 288 bit s n N Error n N Error n N Error n N Error 110 2 174 0 26 2 177 0 25 2 212 0 03 2 217 0 08 150 2 127 0 00 2 129 0 16 2 155 0 16 2 159 0 00 300 1 255 0 00 2 64 0 16 2 77 0 16 2 79 0 00 600 1 127 0 00 1 129 0 16 1 155 0 16 1 159 0 00 1200 0 255 0 00 1 64 0 16 1 77 0...

Page 349: ... 0 45 0 93 0 47 0 00 0 51 0 16 19200 0 20 0 76 0 22 0 93 0 23 0 00 0 25 0 16 31250 0 12 0 00 0 13 0 00 0 14 1 70 0 15 0 00 38400 0 10 3 82 0 10 3 57 0 11 0 00 0 12 0 16 φ MHz Bit Rate 18 20 25 bit s n N Error n N Error n N Error 110 3 79 0 12 3 88 0 25 3 110 0 02 150 2 233 0 16 3 64 0 16 3 80 0 47 300 2 116 0 16 2 129 0 16 2 162 0 15 600 1 233 0 16 2 64 0 16 2 80 0 47 1200 1 116 0 16 1 129 0 16 1 ...

Page 350: ... 0 99 0 199 1 99 1 124 1 162 1 199 1 224 1 249 2 77 10k 0 49 0 99 0 199 0 249 1 80 1 99 1 112 1 124 1 155 25k 0 19 0 39 0 79 0 99 0 129 0 159 0 179 0 199 0 249 50k 0 9 0 19 0 39 0 49 0 64 0 79 0 89 0 99 0 124 100k 0 4 0 9 0 19 0 24 0 39 0 44 0 49 0 62 250k 0 1 0 3 0 7 0 9 0 12 0 15 0 17 0 19 0 24 500k 0 0 0 1 0 3 0 4 0 7 0 8 0 9 1M 0 0 0 1 0 3 0 4 0 4 2M 0 0 0 1 2 5M 0 0 4M 0 0 Note Settings with ...

Page 351: ...tting for baud rate generator 0 N 255 φ System clock frequency MHz n Baud rate generator input clock n 0 1 2 3 For the clock sources and values of n see the following table SMR Settings n Clock Source CKS1 CKS0 0 φ 0 0 1 φ 4 0 1 2 φ 16 1 0 3 φ 64 1 1 The bit rate error in asynchronous mode is calculated as follows Error N 1 B 64 22n 1 1 100 φ 106 ...

Page 352: ...uencies Asynchronous Mode Settings φ MHz Maximum Bit Rate bit s n N 2 62500 0 0 2 097152 65536 0 0 2 4576 76800 0 0 3 93750 0 0 3 6864 115200 0 0 4 125000 0 0 4 9152 153600 0 0 5 156250 0 0 6 187500 0 0 6 144 192000 0 0 7 3728 230400 0 0 8 250000 0 0 9 8304 307200 0 0 10 312500 0 0 12 375000 0 0 12 288 384000 0 0 14 437500 0 0 14 7456 460800 0 0 16 500000 0 0 17 2032 537600 0 0 18 562500 0 0 20 62...

Page 353: ...6 0 6144 38400 3 0 7500 46875 3 6864 0 9216 57600 4 1 0000 62500 4 9152 1 2288 76800 5 1 2500 78125 6 1 5000 93750 6 144 1 5360 96000 7 3728 1 8432 115200 8 2 0000 125000 9 8304 2 4576 153600 10 2 5000 156250 12 3 0000 187500 12 288 3 0720 192000 14 3 5000 218750 14 7456 3 6864 230400 16 4 0000 250000 17 2032 4 3008 268800 18 4 5000 281250 20 5 0000 312500 25 6 2500 390625 ...

Page 354: ...character and synchronous mode in which synchronization is achieved with clock pulses A smart card interface is also supported as a serial communication function for an IC card interface Selection of asynchronous or synchronous mode and the transmission format for the normal serial communication interface is made in SMR as shown in table 12 8 The SCI clock source is selected by the C A bit in SMR ...

Page 355: ...nternal or external clock can be selected as the SCI clock source When an internal clock is selected the SCI operates using the on chip baud rate generator and can output a serial clock signal to external devices When an external clock is selected the SCI operates on the input serial clock The on chip baud rate generator is not used Smart Card Interface One frame consists of 8 bit data and a parit...

Page 356: ...s 8 bit data Present Absent 1 bit 1 mode multi 2 bits 1 0 processor 7 bit data 1 bit 1 format 2 bits 1 Syn chronous mode 8 bit data Absent None Table 12 9 SMR and SCR Settings and SCI Clock Source Selection SMR SCR Setting SCI Transmit Receive clock Bit 7 C A Bit 1 CKE1 Bit 0 CKE0 Mode Clock Source SCK Pin Function 0 0 0 Asynchronous Internal SCI does not use the SCK pin 1 mode Outputs clock with ...

Page 357: ...s serial communication when the line goes to the space low state indicating a start bit One serial character consists of a start bit low data LSB first parity bit high or low and one or two stop bits high in that order When receiving in asynchronous mode the SCI synchronizes at the falling edge of the start bit The SCI samples each data bit on the eighth pulse of a clock with a frequency 16 times ...

Page 358: ...1 0 0 1 1 1 0 0 1 1 0 1 0 1 0 0 1 1 1 1 0 1 1 1 Serial Communication Format and Frame Length 1 2 3 4 5 6 7 8 9 10 11 12 STOP 8 bit data S 8 bit data S STOP P 8 bit data S 8 bit data S STOP 7 bit data S 7 bit data S 7 bit data S S 8 bit data S STOP STOP MPB 8 bit data S 7 bit data S 7 bit data S P STOP STOP STOP STOP STOP MPB Legend S Start bit STOP Stop bit P Parity bit MPB Multiprocessor bit ...

Page 359: ... the clock occurs at the center of each transmit data bit D0 D1 D2 D3 D4 D5 D6 D7 0 1 1 1 0 1frame Figure 12 3 Phase Relationship between Output Clock and Serial Data Asynchronous Mode Transmitting and Receiving Data SCI Initialization Asynchronous Mode Before transmitting or receiving data clear the TE and RE bits to 0 in SCR then initialize the SCI as follows When changing the communication mode...

Page 360: ...ce in SCR Clear the RIE TIE TEIE MPIE TE and RE bits to 0 If clock output is selected in asynchronous mode clock output starts immediately after the setting is made in SCR Select the communication format in SMR Write the value corresponding to the bit rate in BRR This step is not necessary when an external clock is used Wait for at least the interval required to transmit or receive one bit then se...

Page 361: ... the transmit data output function of the TxD pin is selected automatically After the TE bit is set to 1 one frame of 1s is output then transmission is possible SCI status check and transmit data write read SSR and check that the TDRE flag is set to 1 then write transmit data in TDR and clear the TDRE flag to 0 To continue transmitting serial data after checking that the TDRE flag is 1 indicating ...

Page 362: ...bits stop bits are output Mark state Output of 1 bits continues until the start bit of the next transmit data The SCI checks the TDRE flag when it outputs the stop bit If the TDRE flag is 0 the SCI loads new data from TDR into TSR outputs the stop bit then begins serial transmission of the next frame If the TDRE flag is 1 the SCI sets the TEND flag to 1 in SSR outputs the stop bit then continues o...

Page 363: ...or occurs read the ORER PER and FER flags in SSR to identify the error After executing the necessary error handling clear the ORER PER and FER flags all to 0 Receiving cannot resume if any of these flags remains set to 1 When a framing error occurs the RxD pin can be read to detect the break state SCI status check and receive data read read SSR check that the RDRF flag is set to 1 then read receiv...

Page 364: ...es Yes No No No ORER 1 Overrun error handling FER 1 Break Framing error handling Clear RE bit to 0 in SCR PER 1 Parity error handling Clear ORER PER and FER flags to 0 in SSR 3 Figure 12 7 Sample Flowchart for Receiving Serial Data cont ...

Page 365: ...eceived data is stored in RDR If one of the checks fails receive error the SCI operates as shown in table 12 11 Note When a receive error occurs further receiving is disabled In receiving the RDRF flag is not set to 1 Be sure to clear the error flags to 0 When the RDRF flag is set to 1 if the RIE bit is set to 1 in SCR a receive data full interrupt RXI is requested If the ORER PER or FER flag is s...

Page 366: ...D A serial communication cycle consists of an ID sending cycle that identifies the receiving processor and a data sending cycle The multiprocessor bit distinguishes ID sending cycles from data sending cycles The transmitting processor starts by sending the ID of the receiving processor with which it wants to communicate as data with the multiprocessor bit set to 1 Next the transmitting processor s...

Page 367: ...cessor D H 01 MPB 1 Serial data H AA MPB 0 Serial communication line ID sending cycle receiving processor address Data sending cycle data sent to receiving processor specified by ID Legend MPB Multiprocessor bit Figure 12 9 Example of Communication among Processors using Multiprocessor Format Sending Data H AA to Receiving Processor A Transmitting and Receiving Data Transmitting Multiprocessor Ser...

Page 368: ...s selected automatically SCI status check and transmit data write read SSR check that the TDRE flag is 1 then write transmit data in TDR Also set the MPBT flag to 0 or 1 in SSR Finally clear the TDRE flag to 0 To continue transmitting serial data after checking that the TDRE flag is 1 indicating that data can be written write data in TDR then clear the TDRE flag to 0 To output a break signal at th...

Page 369: ...puts the stop bit If the TDRE flag is 0 the SCI loads new data from TDR into TSR outputs the stop bit then begins serial transmission of the next frame If the TDRE flag is 1 the SCI sets the TEND flag to 1 in SSR outputs the stop bit then continues output of 1 bits in the mark state If the TEIE bit is set to 1 in SCR a transmit end interrupt TEI is requested at this time Figure 12 11 shows an exam...

Page 370: ...rocessor s own ID If the ID does not match set the MPIE bit to 1 again and clear the RDRF flag to 0 If the ID matches clear the RDRF flag to 0 SCI status check and data receiving read SSR check that the RDRF flag is set to 1 then read data from RDR Receive error handling and break detection if a receive error occurs read the ORER and FER flags in SSR to identify the error After executing the neces...

Page 371: ...ar ORER PER and FER flags to 0 in SSR Clear RE bit to 0 in SCR 5 Error handling ORER 1 FER 1 No Break Overrun error handling Framing error handling Yes Figure 12 12 Sample Flowchart for Receiving Multiprocessor Serial Data cont ...

Page 372: ...ue RXI interrupt request multiprocessor interrupt RXI interrupt handler reads RDR data and clears RDRF flag to 0 No RXI interrupt request RDR not updated ID1 MPB D0 D1 D7 1 1 0 Start bit 0 D0 D1 D7 0 1 1 Data ID2 MPIE 1 MPB RDRF RXI interrupt request multiprocessor interrupt MPB detection MPIE 0 RXI interrupt handler reads RDR data and clears RDRF flag to 0 Own ID so receiving continues with data ...

Page 373: ... on the communication line from one falling edge of the serial clock to the next Data is guaranteed valid at the rise of the serial clock In each character the serial data bits are transferred in order from LSB first to MSB last After output of the MSB the communication line remains in the state of the MSB In synchronous mode the SCI receives data by synchronizing with the rise of the serial clock...

Page 374: ...ld be cleared to 0 or set to 1 simultaneously 4 3 2 1 Start of initialization Yes Wait Yes 1 bit interval elapsed Set value in BRR Clear TE and RE bits to 0 in SCR Select communication format in SMR Set RIE TIE MPIE CKE1 and CKE0 bits in SCR leaving TE and RE bits cleared to 0 Set TE or RE bit to 1 in SCR Set RIE TIE TEIE and MPIE bits as necessary 1 2 3 4 Set the clock source in SCR Clear the RIE...

Page 375: ...ite transmit data in TDR and clear TDRE flag to 0 in SSR TEND 1 No SCI initialization the transmit data output function of the TxD pin is selected automatically SCI status check and transmit data write read SSR check that the TDRE flag is 1 then write transmit data in TDR and clear the TDRE flag to 0 To continue transmitting serial data after checking that the TDRE flag is 1 indicating that data c...

Page 376: ...t frame If the TDRE flag is 1 the SCI sets the TEND flag to 1 in SSR and after transmitting the MSB holds the TxD pin in the MSB state If the TEIE bit is set to 1 in SCR a transmit end interrupt TEI is requested at this time After the end of serial transmission the SCK pin is held in a constant state Figure 12 17 shows an example of SCI transmit operation Bit 0 Bit 1 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 ...

Page 377: ...ad the ORER flag in SSR then after executing the necessary error handling clear the ORER flag to 0 Neither transmitting nor receiving can resume while the ORER flag remains set to 1 SCI status check and receive data read read SSR check that the RDRF flag is set to 1 then read receive data from RDR and clear the RDRF flag to 0 Notification that the RDRF flag has changed from 0 to 1 can also be give...

Page 378: ...flag is 0 so that receive data can be transferred from RSR to RDR If this check passes the RDRF flag is set to 1 and the received data is stored in RDR If the checks fails receive error the SCI operates as shown in table 12 11 When a receive error has been identified in the error check subsequent transmit and receive operations are disabled When the RDRF flag is set to 1 if the RIE bit is set to 1...

Page 379: ...lock Serial data RXI interrupt handler reads data in RDR and clears RDRF flag to 0 RXI interrupt request RXI interrupt request Overrun error ERI interrupt request ORER RDRF Bit 7 Bit 0 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 1 frame Figure 12 19 Example of SCI Receive Operation ...

Page 380: ...flag has changed from 0 to 1 can also be given by the TXI interrupt Receive error handling if a receive error occurs read the ORER flag in SSR then after executing the necessary error handling clear the ORER flag to 0 Neither transmitting nor receiving can resume while the ORER flag remains set to 1 SCI status check and receive data read read SSR check that the RDRF flag is 1 then read receive dat...

Page 381: ...est is sent separately to the interrupt controller A TXI interrupt is requested when the TDRE flag is set to 1 in SSR A TEI interrupt is requested when the TEND flag is set to 1 in SSR An RXI interrupt is requested when the RDRF flag is set to 1 in SSR An ERI interrupt is requested when the ORER PER or FER flag is set to 1 in SSR Table 12 12 SCI Interrupt Sources Priority Interrupt Source Descript...

Page 382: ...be sure to check that the TDRE flag is set to 1 Simultaneous Multiple Receive Errors Table 12 13 shows the state of the SSR status flags when multiple receive errors occur simultaneously When an overrun error occurs the RSR contents are not transferred to RDR so receive data is lost Table 12 13 SSR Status Flags and Transfer of Receive Data SSR Status Flags Receive Data Transfer RDRF ORER FER PER R...

Page 383: ...bit to 0 When the TE bit is cleared to 0 the transmitter is initialized regardless of its current state so the TxD pin becomes an input output outputting the value 0 Receive Error Flags and Transmitter Operation Synchronous Mode Only When a receive error flag ORER PER or FER is set to 1 the SCI will not start transmitting even if the TDRE flag is cleared to 0 Be sure to clear the receive error fla...

Page 384: ... 100 1 46 875 2 This is a theoretical value A reasonable margin to allow in system designs is 20 to 30 Restrictions on Use of an External Clock Source When an external clock source is used for the serial clock after updates TDR allow an inversion of at least five system clock φ cycles before input of the serial clock to start transmitting If the serial clock is input within four states of the TDR ...

Page 385: ...1 0 CKE0 0 and TE 1 synchronous mode low level output occurs for one half cycle 1 End of serial data transmission 2 TE bit 0 3 C A bit 0 switchover to port output 4 Occurrence of low level output see figure 12 23 SCK port Data TE C A CKE1 CKE0 Bit 7 Bit 6 1 End of transmission 4 Low level output 3 C A 0 2 TE 0 Half cycle low level output Figure 12 23 Operation when Switching from SCK Pin Function ...

Page 386: ... 1 CKE1 0 CKE0 0 and TE 1 make the following settings in the order shown 1 End of serial data transmission 2 TE bit 0 3 CKE1 bit 1 4 C A bit 0 switchover to port output 5 CKE1 bit 0 SCK port Data TE C A CKE1 CKE0 Bit 7 Bit 6 1 End of transmission 3 CKE1 1 5 CKE1 0 4 C A 0 2 TE 0 High level outputTE Figure 12 24 Operation when Switching from SCK Pin Function to Port Pin Function Example of Preventi...

Page 387: ...ures of the smart card interface supported by the H8 3008 are listed below Asynchronous communication Data length 8 bits Parity bit generation and checking Transmission of error signal parity error in receive mode Error signal detection and automatic data retransmission in transmit mode Direct convention and inverse convention both supported Built in baud rate generator allows any bit rate to be s...

Page 388: ...ster RSR Receive shift register RDR Receive data register TSR Transmit shift register TDR Transmit data register SMR Serial mode register SCR Serial control register SSR Serial status register BRR Bit rate register Figure 13 1 Block Diagram of Smart Card Interface 13 1 3 Pin Configuration Table 13 1 shows the smart card interface pins Table 13 1 Smart Card Interface Pins Pin Name Abbreviation I O ...

Page 389: ...FFB2 Serial control register SCR R W H 00 H FFFB3 Transmit data register TDR R W H FF H FFFB4 Serial status register SSR R W 2 H 84 H FFFB5 Receive data register RDR R H 00 H FFFB6 Smart card mode register SCMR R W H F2 1 H FFFB8 Serial mode register SMR R W H 00 H FFFB9 Bit rate register BRR R W H FF H FFFBA Serial control register SCR R W H 00 H FFFBB Transmit data register TDR R W H FF H FFFBC ...

Page 390: ... select Enables or disables the smart card interface function Smart card data invert Inverts data logic levels Smart card data transfer direction Selects the serial parallel conversion format SCMR is initialized to H F2 by a reset and in standby mode Bits 7 to 4 Reserved Read only bits always read as 1 Bit 3 Smart Card Data Transfer Direction SDIR Selects the serial parallel conversion format 1 Bi...

Page 391: ...art card interface function Bit 0 SMIF Description 0 Smart card interface function is disabled Initial value 1 Smart card interface function is enabled Notes 1 The function for switching between LSB first and MSB first mode can also be used with the normal serial communication interface Note that when the communication format data length is set to 7 bits and MSB first mode is selected for the seri...

Page 392: ...ication For details see section 12 2 7 Serial Status Register SSR Bit 4 Error Signal Status ERS In smart card interface mode this flag indicates the status of the error signal sent from the receiving device to the transmitting device The smart card interface does not detection framing errors Bit 4 ERS Description 0 Indicates normal transmission with no error signal returned Initial value Clearing ...

Page 393: ...l transmission Note An etu elementary time unit is the time needed to transmit one bit 13 2 3 Serial Mode Register SMR The function of SMR bit 7 is modified in smart card interface mode This change also causes a modification to the function of bits 1 and 0 in the serial control register SCR 7 GM 0 R W 6 CHR 0 R W 5 PE 0 R W 4 O E 0 R W 3 STOP 0 R W 0 CKS0 0 R W 2 MP 0 R W 1 CKS1 0 R W Bit Initial ...

Page 394: ...KE0 0 R W 2 TEIE 0 R W 1 CKE1 0 R W Bit Initial value Read Write Bits 7 to 2 These bits operate as in normal serial communication For details see section 12 2 6 Serial Control Register SCR Bits 1 and 0 Clock Enable 1 and 0 CKE1 CKE0 These bits select the SCI clock source and enable or disable clock output from the SCK pin In smart card interface mode it is possible to specify a fixed high level or...

Page 395: ... communication is supported there is no synchronous communication function 13 3 2 Pin Connections Figure 13 2 shows a pin connection diagram for the smart card interface In communication with a smart card since both transmission and reception are carried out on a single data transmission line the TxD pin and RxD pin should both be connected to this line The data transmission line should be pulled ...

Page 396: ...t card enables closed transmission reception allowing self diagnosis to be carried out 13 3 3 Data Format Figure 13 3 shows the smart card interface data format In reception in this mode a parity check is carried out on each frame and if an error is detected an error signal is sent back to the transmitting device to request retransmission of the data In transmission the error signal is sampled and...

Page 397: ...smart card interface the data line then returns to the high impedance state The data line is pulled high with a pull up resistor 4 The receiving device carries out a parity check If there is no parity error and the data is received normally the receiving device waits for reception of the next data If a parity error occurs however the receiving device outputs an error signal DE low level to request...

Page 398: ...ard interface mode or set to 1 when using GSM mode Clear the O E bit to 0 if the smart card is of the direct convention type or set to 1 if of the inverse convention type Bits CKS1 and CKS0 select the clock source of the built in baud rate generator See section 13 3 5 Clock Bit Rate Register BRR Settings BRR is used to set the bit rate See section 13 3 5 Clock for the method of calculating the val...

Page 399: ... bit is 1 following the even parity rule designated for smart cards 2 Inverse Convention SDIR SINV O E 1 Ds D7 D6 D5 D4 D3 D2 D1 D0 Dp A Z Z A A A A A A Z Z Z State With the inverse convention type the logic 1 level corresponds to state A and the logic 0 level to state Z and transfer is performed in MSB first order In the example above the first character data is H 3F The parity bit is 0 correspon...

Page 400: ...6 φ where N BRR setting 0 N 255 B Bit rate bit s φ Operating frequency MHz n See table 13 4 Table 13 4 n Values of CKS1 and CKS0 Settings n CKS1 CKS0 0 0 0 1 1 2 1 0 3 1 Note If the gear function is used to divide the clock frequency use the divided frequency to calculate the bit rate The equation above applies directly to 1 1 frequency division Table 13 5 Bit Rates bits s for Various BRR Settings...

Page 401: ...0 14 2848 16 00 18 00 25 0 bit s N Error N Error N Error N Error N Error N Error N Error N Error 9600 0 0 00 1 30 1 25 1 8 99 1 0 00 1 12 01 2 15 99 3 12 49 Table 13 7 Maximum Bit Rates for Various Frequencies Smart Card Interface Mode φ MHz Maximum Bit Rate bits s N n 7 1424 9600 0 0 10 00 13441 0 0 10 7136 14400 0 0 13 00 17473 0 0 14 2848 19200 0 0 16 00 21505 0 0 18 00 24194 0 0 20 00 26882 0 ...

Page 402: ... not set the TE bit and RE bit at the same time except for self diagnosis Transmitting Serial Data As data transmission in smart card mode involves error signal sampling and retransmission processing the processing procedure is different from that for the normal SCI Figure 13 5 shows a sample transmission processing flowchart 1 Perform smart card interface mode initialization as described in Initi...

Page 403: ...387 For details see Interrupt Operations in this section Serial data 1 GM 0 TEND 2 GM 1 TEND Ds Dp DE Guard time 11 0 etu 12 5 etu Figure 13 4 Timing of TEND Flag Setting ...

Page 404: ...t transmitting Start No No No Yes Yes Yes Yes No End Write transmit data in TDR and clear TDRE flag to 0 in SSR Error handling Error handling TEND 1 All data transmitted TEND 1 FER ERS 0 FER ERS 0 Figure 13 5 Sample Transmission Processing Flowchart ...

Page 405: ...n GM 0 Guard time DE Ds Da Db Dc Dd De Df Dg Dh Dp 12 5 etu 11 0 etu When GM 1 TXI TEND interrupt Figure 13 7 Timing of TEND Flag Setting Receiving Serial Data Data reception in smart card mode uses the same processing procedure as for the normal SCI Figure 13 8 shows a sample reception processing flowchart 1 Perform smart card interface mode initialization as described in Initialization above 2 C...

Page 406: ...requested If an error occurs in reception and either the ORER flag or the PER flag is set to 1 a transmit receive error interrupt ERI will be requested For details see Interrupt Operations in this section If a parity error occurs during reception and the PER flag is set to 1 the received data is transferred to RDR so the erroneous data can be read Switching Modes When switching from receive mode t...

Page 407: ... pulse width SCR write CKE0 1 SCR write CKE0 0 Figure 13 9 Timing for Fixing Cock Output Interrupt Operations The smart card interface has three interrupt sources transmit data empty TXI transmit receive error ERI and receive data full RXI The transmit end interrupt request TEI is not available in smart card mode A TXI interrupt is requested when the TEND flag is set to 1 in SSR An RXI interrupt i...

Page 408: ...ite H 00 in the serial mode register SMR and smart card mode register SCMR 6 Make the transition to the software standby state Returning from software standby mode to smart card interface mode 1 Clear the software standby state 2 Set the CKE1 bit in SCR to the value for the fixed output state at the start of software standby the current P94 pin state 3 Set smart card interface mode and output the ...

Page 409: ...2 times the transfer rate In reception the SCI synchronizes internally with the fall of the start bit which it samples on the base clock Receive data is latched at the rising edge of the 186th base clock pulse The timing is shown in figure 13 11 Internal base clock 372 clocks 186 clocks Receive data RxD Synchronization sampling timing D0 D1 Data sampling timing 185 371 0 371 185 0 0 Start bit Figu...

Page 410: ...receive mode 1 If an error is found when the received parity bit is checked the PER bit is automatically set to 1 If the RIE bit in SCR is set to the enable state an ERI interrupt is requested The PER bit should be cleared to 0 in SSR before the next parity bit sampling timing 2 The RDRF bit in SSR is not set for the frame in which the error has occurred 3 If an error is found when the received pa...

Page 411: ...ent back from the receiving device the ERS flag is not set in SSR 9 If an error signal is not sent back from the receiving device transmission of one frame including retransmission is assumed to have been completed and the TEND bit is set to 1 in SSR If the TIE bit in SCR is set to the enable state a TXI interrupt is requested D0 D1 D2 D3 D4 D5 D6 D7 Dp DE Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE Ds D0 D1...

Page 412: ...396 ...

Page 413: ...onversion voltage range The analog voltage conversion range can be programmed by input of an analog reference voltage at the VREF pin High speed conversion Conversion time minimum 3 5 µs per channel with 20 MHz system clock minimum 2 8 µs per channel with 25 MHz system clock Two conversion modes Single mode A D conversion of one channel Scan mode continuous A D conversion on one to four channels F...

Page 414: ...alog multi plexer Sample and hold circuit Comparator Control circuit ø 4 ø 8 ADI interrupt signal AV V AV CC REF SS AN AN AN AN AN AN AN AN 0 1 2 3 4 5 6 7 Legend ADCR ADCSR ADDRA ADDRB ADDRC ADDRD A D control register A D control status register A D data register A A D data register B A D data register C A D data register D ADTRG ADTE Compare match A0 8TCSR0 8 bit timer Figure 14 1 A D Converter ...

Page 415: ...I O Function Analog power supply pin AVCC Input Analog power supply Analog ground pin AVSS Input Analog ground and reference voltage Reference voltage pin VREF Input Analog reference voltage Analog input pin 0 AN0 Input Group 0 analog inputs Analog input pin 1 AN1 Input Analog input pin 2 AN2 Input Analog input pin 3 AN3 Input Analog input pin 4 AN4 Input Group 1 analog inputs Analog input pin 5 A...

Page 416: ... bits of the address in advanced mode 2 Only 0 can be written in bit 7 to clear the flag 14 2 Register Descriptions 14 2 1 A D Data Registers A to D ADDRA to ADDRD Bit ADDRn Initial value 14 AD8 0 R 12 AD6 0 R 10 AD4 0 R 8 AD2 0 R 6 AD0 0 R 0 0 R 4 0 R 2 0 R 15 AD9 0 R 13 AD7 0 R 11 AD5 0 R 9 AD3 0 R 7 AD1 0 R 1 0 R 5 0 R 3 0 R A D conversion data 10 bit data giving an A D conversion result Reserv...

Page 417: ...d A D Data Registers ADDRA to ADDRD Analog Input Channel Group 0 Group 1 A D Data Register AN0 AN4 ADDRA AN1 AN5 ADDRB AN2 AN6 ADDRC AN3 AN7 ADDRD 14 2 2 A D Control Status Register ADCSR Bit Initial value Read Write 7 ADF 0 R W 6 ADIE 0 R W 5 ADST 0 R W 4 SCAN 0 R W 3 CKS 0 R W 0 CH0 0 R W 2 CH2 0 R W 1 CH1 0 R W Note Only 0 can be written to clear the flag A D end flag Indicates end of A D conve...

Page 418: ...end interrupt request ADI is enabled Bit 5 A D Start ADST Starts or stops A D conversion The ADST bit remains set to 1 during A D conversion It can also be set to 1 by external trigger input at the ADTRG pin or by an 8 bit timer compare match Bit 5 ADST Description 0 A D conversion is stopped Initial value 1 Single mode A D conversion starts ADST is automatically cleared to 0 when conversion ends ...

Page 419: ...iption CH2 CH1 CH0 Single Mode Scan Mode 0 0 0 AN0 Initial value AN0 1 AN1 AN0 AN1 1 0 AN2 AN0 to AN2 1 AN3 AN0 to AN3 1 0 0 AN4 AN4 1 AN5 AN4 AN5 1 0 AN6 AN4 to AN6 1 AN7 AN4 to AN7 14 2 3 A D Control Register ADCR Bit Initial value Read Write 7 TRGE 0 R W 6 1 5 1 4 1 3 1 0 0 R W 2 1 1 1 Trigger enable Enables or disables starting of A D conversion by an external trigger or 8 bit timer compare ma...

Page 420: ... be read or written but must not be set to 1 14 3 CPU Interface ADDRA to ADDRD are 16 bit registers but they are connected to the CPU by an 8 bit data bus Therefore although the upper byte can be be accessed directly by the CPU the lower byte is read through an 8 bit temporary register TEMP An A D data register is read as follows When the upper byte is read the upper byte value is transferred dire...

Page 421: ...ace Module data bus CPU H AA ADDRnH H AA ADDRnL H 40 Lower byte read Bus interface Module data bus CPU H 40 ADDRnH H AA ADDRnL H 40 TEMP H 40 TEMP H 40 n A to D n A to D Figure 14 2 A D Data Register Access Operation Reading H AA40 ...

Page 422: ... D conversion After making the necessary changes set the ADST bit to 1 to start A D conversion again The ADST bit can be set at the same time as the mode or channel is changed Typical operations when channel 1 AN1 is selected in single mode are described next Figure 14 3 shows a timing diagram for this example 1 Single mode is selected SCAN 0 input channel AN1 is selected CH2 CH1 0 CH0 1 the A D i...

Page 423: ...sult A D conversion result 1 Read conversion result A D conversion result 2 Note Vertical arrows indicate instructions executed by software 0 1 2 3 A D conversion starts ADDRA ADDRB ADDRC ADDRD State of channel 1 AN State of channel 2 AN State of channel 3 AN Idle Figure 14 3 Example of A D Converter Operation Single Mode Channel 1 Selected ...

Page 424: ...irst channel in the group The ADST bit can be set at the same time as the mode or channel selection is changed Typical operations when three channels in group 0 AN0 to AN2 are selected in scan mode are described next Figure 14 4 shows a timing diagram for this example 1 Scan mode is selected SCAN 1 scan group 0 is selected CH2 0 analog input channels AN0 to AN2 are selected CH1 1 CH0 0 and A D con...

Page 425: ...le Transfer A D conversion result 1 A D conversion result 4 A D conversion result 2 A D conversion result 3 1 2 A D conversion time Notes 2 1 ADDRA ADDRB ADDRC ADDRD State of channel 1 AN State of channel 2 AN State of channel 3 AN Vertical arrows indicate instructions executed by software Data currently being converted is ignored Figure 14 4 Example of A D Converter Operation Scan Mode Channels A...

Page 426: ...ing time The length of tD varies depending on the timing of the write access to ADCSR The total conversion time therefore varies within the ranges indicated in table 14 4 In scan mode the values given in table 14 4 apply to the first conversion In the second and subsequent conversions the conversion time is fixed at 128 states when CKS 0 or 66 states when CKS 1 φ Address bus Write signal Input sam...

Page 427: ... can be externally triggered When the TRGE bit is set to 1 in ADCR and the 8 bit timer s ADTE bit is cleared to 0 external trigger input is enabled at the ADTRG pin A high to low transition at the ADTRG pin sets the ADST bit to 1 in ADCSR starting A D conversion Other operations in both single and scan modes are the same as if the ADST bit had been set to 1 by software Figure 14 6 shows the timing...

Page 428: ...incorrectly or may adversely affect the accuracy of A D conversion The analog input signals AN0 to AN7 analog reference voltage VREF and analog supply voltage AVCC must be separated from digital circuits by the analog ground AVSS The analog ground AVSS should be connected to a stable digital ground VSS at one point on the board 5 Note on Noise To prevent damage from surges and other abnormal volta...

Page 429: ...nput Pin Ratings Item Min Max Unit Analog input capacitance 20 pF Allowable signal source impedance 10 kΩ Note When conversion time 134 states VCC 4 0 V to 5 5 V and φ 13 MHz For details see section 19 Electrical Characteristics 20 pF To A D converter AN0 to AN7 10 kΩ Figure 14 8 Analog Input Pin Equivalent Circuit Note Numeric values are approximate except in table 14 5 ...

Page 430: ...ital output from 1111111110 to 1111111111 figure 14 10 Quantization error Intrinsic error of the A D converter 1 2 LSB figure 14 9 Nonlinearity error Deviation from ideal A D conversion characteristic in range from zero volts to full scale exclusive of offset error full scale error and quantization error Absolute accuracy Deviation of digital value from analog input value including offset error fu...

Page 431: ...guaranteed If a large external capacitor is provided in single mode then the internal 10 kΩ input resistance becomes the only significant load on the input In this case the impedance of the signal source is not a problem A large external capacitor however acts as a low pass filter This may make it impossible to track analog signals with high dv dt e g a variation of 5 mV µs figure 14 11 To convert...

Page 432: ...416 Equivalent circuit of A D converter H8 3008 20 pF Cin 15 pF 10 kΩ Up to 10 kΩ Low pass filter C up to 0 1 µF Sensor output impedance Sensor input Figure 14 11 Analog Input Circuit Example ...

Page 433: ... D A converter with two channels 15 1 1 Features D A converter features are listed below Eight bit resolution Two output channels Conversion time maximum 10 µs with 20 pF capacitive load Output voltage 0 V to VREF D A outputs can be sustained in software standby mode ...

Page 434: ...DR0 DADR1 DACR DASTCR V AV DA DA AV REF CC SS 0 1 Legend DACR DADR0 DADR1 DASTCR 8 bit D A Module data bus Bus interface Internal data bus Control circuit D A control register D A data register 0 D A data register 1 D A standby control register Figure 15 1 D A Converter Block Diagram ...

Page 435: ...alog output channel 0 Analog output pin 1 DA1 Output Analog output channel 1 Reference voltage input pin VREF Input Analog reference voltage 15 1 4 Register Configuration Table 15 2 summarizes the D A converter s registers Table 15 2 D A Converter Registers Address Name Abbreviation R W Initial Value H FFF9C D A data register 0 DADR0 R W H 00 H FFF9D D A data register 1 DADR1 R W H 00 H FFF9E D A ...

Page 436: ...STE bit is set to 1 in the D A standby control register DASTCR the D A registers are not initialized in software standby mode 15 2 2 D A Control Register DACR Bit Initial value Read Write 7 DAOE1 0 R W 6 DAOE0 0 R W 5 DAE 0 R W 4 1 3 1 2 1 1 1 0 1 D A output enable 1 D A output enable 0 D A enable Controls D A conversion and analog output Controls D A conversion and analog output Controls D A conv...

Page 437: ...ntrolled together in channels 0 and 1 Output of the conversion results is always controlled independently by DAOE0 and DAOE1 Bit 7 DAOE1 Bit 6 DAOE0 Bit 5 DAE Description 0 0 D A conversion is disabled in channels 0 and 1 0 1 0 D A conversion is enabled in channel 0 D A conversion is disabled in channel 1 0 1 1 D A conversion is enabled in channels 0 and 1 1 0 0 D A conversion is disabled in chann...

Page 438: ...its 7 to 1 Reserved These bits cannot be modified and are always read as 1 Bit 0 D A Standby Enable DASTE Enables or disables D A output in software standby mode Bit 0 DASTE Description 0 D A output is disabled in software standby mode Initial value 1 D A output is enabled in software standby mode 15 3 Operation The D A converter has two built in D A conversion circuits that can perform conversion...

Page 439: ...esult continues until the value in DADR0 is modified or the DAOE0 bit is cleared to 0 3 If the DADR0 value is modified conversion starts immediately and the result is output after the conversion time 4 When the DAOE0 bit is cleared to 0 DA0 becomes an input pin DADR0 write cycle DACR write cycle DADR0 write cycle DACR write cycle Address DADR0 DAOE0 DA φ 0 Conversion data 1 Conversion data 2 High ...

Page 440: ...en the DASTE bit is set to 1 in DASTCR D A converter output is enabled in software standby mode The D A converter registers retain the values they held prior to the transition to software standby mode When D A output is enabled in software standby mode the reference supply current is the same as during normal operation ...

Page 441: ...a transfer The on chip RAM can be enabled or disabled with the RAM enable bit RAME in the system control register SYSCR When the on chip RAM is disabled that area is assigned to external space in the expanded modes The on chip RAM specifications for the H8 3008 are shown in table 16 1 Table 16 1 H8 3008 On Chip RAM Specifications RAM size 4 kbytes Address assignment Modes 1 2 H FEF20 to H FFF1F Mo...

Page 442: ...es Odd addresses Legend SYSCR System control register Note The lower 20 bits of the address are shown Figure 16 1 RAM Block Diagram 16 1 2 Register Configuration The on chip RAM is controlled by SYSCR Table 16 2 gives the address and initial value of SYSCR Table 16 2 System Control Register Address Name Abbreviation R W Initial Value H EE012 System control register SYSCR R W H 09 Note Lower 20 bit...

Page 443: ... or disables on chip RAM One function of SYSCR is to enable or disable access to the on chip RAM The on chip RAM is enabled or disabled by the RAME bit in SYSCR For details about the other bits see section 3 3 System Control Register SYSCR Bit 0 RAM Enable RAME Enables or disables the on chip RAM The RAME bit is initialized at the rising edge of the input at the RES pin It is not initialized in so...

Page 444: ...E bit is cleared to 0 the off chip address space is accessed Since the on chip RAM is connected to the CPU by an internal 16 bit data bus it can be written and read by word access It can also be written and read by byte access Byte data is accessed in two states using the upper 8 bits of the data bus Word data starting at an even address is accessed in two states using all 16 bits of the data bus ...

Page 445: ...e frequency division ratio Notes 1 Usage of the φ pin differs depending on the chip operating mode and the PSTOP bit setting in the module standby control register MSTCR For details see section 18 7 System Clock Output Disabling Function 2 The division ratio of the frequency divider can be changed dynamically during operation The clock output at the φ pin also changes when the division ratio is ch...

Page 446: ...rnal load capacitance values in table 17 1 2 should not exceed 10 pF Also in order to improve the accuracy of the oscillation frequency a thorough study of oscillation matching evaluation etc should be carried out when deciding the circuit constants Table 17 1 1 Damping Resistance Value Damping Resistance Frequency f MHz Value 2 2 f 4 4 f 8 8 f 10 10 f 13 13 f 16 16 f 18 18 f 25 Rd Ω 1 k 500 200 0...

Page 447: ...pF 7 pF max Use a crystal resonator with a frequency equal to the system clock frequency φ Notes on Board Design When a crystal resonator is connected the following points should be noted Other signal lines should be routed away from the oscillator circuit to prevent induction from interfering with correct oscillation See figure 17 4 When the board is designed the crystal resonator and its load ca...

Page 448: ...ck frequency should be equal to the system clock frequency when not divided by the on chip frequency divider Table 17 3 shows the clock timing figure 17 6 shows the external clock input timing and figure 17 7 shows the external clock output settling delay timing When the appropriate external clock is input via the EXTAL pin its waveform is corrected by the on chip oscillator and duty adjustment ci...

Page 449: ...nal clock rise time tEXr 8 5 ns External clock fall time tEXf 8 5 ns Clock low pulse width tCL 0 4 0 6 0 4 0 6 tcyc φ 5 MHz Figure 80 80 ns φ 5 MHz 19 17 Clock high pulse width tCH 0 4 0 6 0 4 0 6 tcyc φ 5 MHz 80 80 ns φ 5 MHz External clock output settling delay time tDEXT 500 500 µs Figure 17 7 Note tDEXT includes a RES pulse width tRESW tRESW 20 tcyc EXTAL tEXr tEXf VCC 0 7 0 3 V tEXH tEXL VCC ...

Page 450: ... 4 Prescalers The prescalers divide the system clock φ to generate internal clocks φ 2 to φ 4096 17 5 Frequency Divider The frequency divider divides the duty adjusted clock signal to generate the system clock φ The frequency division ratio can be changed dynamically by modifying the value in DIVCR as described below Power consumption in the chip is reduced in almost direct proportion to the frequ...

Page 451: ... division ratio of the frequency divider Bit Initial value Read Write 7 1 6 1 5 1 4 1 3 1 0 DIV0 0 R W 2 1 1 DIV1 0 R W Reserved bits Divide bits 1 and 0 These bits select the frequency division ratio DIVCR is initialized to H FC by a reset and in hardware standby mode It is not initialized in software standby mode Bits 7 to 2 Reserved These bits cannot be modified and are always read as 1 Bits 1 ...

Page 452: ...mit of the operating frequency range Ensure that ø is not below this lower limit All on chip module operations are based on φ Note that the timing of timer operations serial communication and other time dependent processing differs before and after any change in the division ratio The waiting time for exit from software standby mode also changes when the division ratio is changed For details see s...

Page 453: ...includes the following three modes Sleep mode Software standby mode Hardware standby mode The module standby function can halt on chip supporting modules independently of the power down state The modules that can be halted are the 16 bit timer 8 bit timer SCI0 SCI1 and A D converter Table 18 1 indicates the methods of entering and exiting the power down modes and module standby mode and gives the ...

Page 454: ...ware standby mode Hardware standby mode Module standby State Entering Conditions SLEEP instruc tion executed while SSBY 0 in SYSCR SLEEP instruc tion executed while SSBY 1 in SYSCR Low input at STBY pin Corresponding bit set to 1 in MSTCRH and MSTCRL Clock Active Halted Halted Active CPU Halted Halted Halted Active CPU Registers Held Held Undeter mined 16 Bit Timer Active Halted and reset Halted a...

Page 455: ... R W H 00 Note Lower 20 bits of the address in advanced mode 18 2 1 System Control Register SYSCR Bit Initial value Read Write 7 SSBY 0 R W 6 STS2 0 R W 5 STS1 0 R W 4 STS0 0 R W 3 UE 1 R W 0 RAME 1 R W 2 NMIEG 0 R W 1 SSOE 0 R W Software standby Enables transition to software standby mode RAM enable Standby timer select 2 to 0 These bits select the waiting time of the CPU and peripheral functions...

Page 456: ...cy so that the waiting time will be at least 7 ms See table 18 3 If an external clock is used any setting can be selected Bit 6 STS2 Bit 5 STS1 Bit 4 STS0 Description 0 0 0 Waiting time 8 192 states Initial value 1 Waiting time 16 384 states 1 0 Waiting time 32 768 states 1 Waiting time 65 536 states 1 0 0 Waiting time 131 072 states 1 0 1 Waiting time 262 144 states 1 1 0 Waiting time 1 024 state...

Page 457: ...ule standby H1 to 0 These bits select modules to be placed in standby Reserved bits MSTCRH is initialized to H 78 by a reset and in hardware standby mode It is not initialized in software standby mode Bit 7 φ Clock Stop PSTOP Enables or disables output of the system clock φ Bit 7 PSTOP Description 0 System clock output is enabled Initial value 1 System clock output is disabled Bits 6 to 3 Reserved...

Page 458: ...bit timer 8 bit timer and A D converter modules 2 MSTPL2 0 R W 1 0 R W 0 MSTPL0 0 R W Reserved bits Module standby L4 to L2 L0 These bits select modules to be placed in standby Bit Initial value Read Write 7 0 R W 6 0 R W 5 0 R W 4 MSTPL4 0 R W 3 MSTPL3 0 R W MSTCRL is initialized to H 00 by a reset and in hardware standby mode It is not initialized in software standby mode Bits 7 to 5 Reserved Th...

Page 459: ...by L2 MSTPL2 Selects whether to place 8 bit timer channels 2 and 3 in standby Bit 2 MSTPL2 Description 0 8 bit timer channels 2 and 3 operate normally Initial value 1 8 bit timer channels 2 and 3 are in standby state Bit 1 Reserved This bit can be written and read Bit 0 Module Standby L0 MSTPL0 Selects whether to place the A D converter in standby Bit 0 MSTPL0 Description 0 A D converter operates ...

Page 460: ...other than NMI if the interrupt is masked by interrupt priority settings and the settings of the I and UI bits in CCR IPR Exit by RES Input Low input at the RES pin exits from sleep mode to the reset state Exit by STBY Input Low input at the STBY pin exits from sleep mode to hardware standby mode 18 4 Software Standby Mode 18 4 1 Transition to Software Standby Mode To enter software standby mode e...

Page 461: ... masked in the CPU Exit by RES Input When the RES input goes low the clock oscillator starts and clock pulses are supplied immediately to the entire chip The RES signal must be held low long enough for the clock oscillator to stabilize When RES goes high the CPU starts reset exception handling Exit by STBY Input Low input at the STBY pin causes a transition to hardware standby mode 18 4 3 Selectio...

Page 462: ...0 08 0 10 0 11 0 13 0 17 0 20 0 26 0 34 0 51 1 0 1 1 1 Illegal setting 1 0 0 0 0 8192 states 1 3 1 6 1 8 2 0 2 7 3 3 4 1 5 5 8 2 16 4 0 0 1 16384 states 2 6 3 3 3 6 4 1 5 5 6 6 8 2 10 9 16 4 32 8 0 1 0 32768 states 5 2 6 6 7 3 8 2 10 9 13 1 16 4 21 8 32 8 65 5 0 1 1 65536 states 10 5 13 1 14 6 16 4 21 8 26 2 32 8 43 7 65 5 131 1 1 0 0 131072 states 21 0 26 2 29 1 32 8 43 7 52 4 65 5 87 4 131 1 262...

Page 463: ...Y bit is set to 1 then the SLEEP instruction is executed to enter software standby mode Software standby mode is exited at the next rising edge of the NMI signal φ NMI NMIEG SSBY NMI interrupt handler NMIEG 1 SSBY 1 Software standby mode power down state Oscillator settling time tosc2 SLEEP instruction NMI exception handling Clock oscillator Figure 18 1 NMI Timing for Software Standby Mode Example...

Page 464: ...e changed during hardware standby mode 18 5 2 Exit from Hardware Standby Mode Hardware standby mode is exited by inputs at the STBY and RES pins While RES is low when STBY goes high the clock oscillator starts running RES should be held low long enough for the clock oscillator to settle When RES goes high reset exception handling begins followed by a transition to the program execution state 18 5 ...

Page 465: ...module When an on chip supporting module is placed in standby by the module standby function its registers are initialized including registers with interrupt request flags Pin States Pins used by an on chip supporting module lose their module functions when the module is placed in module standby What happens after that depends on the particular pin For details see section 7 I O Ports Pins that cha...

Page 466: ...leared to 0 output of the system clock is enabled Table 18 4 indicates the state of the φ pin in various operating states T1 T2 PSTOP 1 T3 T1 T2 PSTOP 0 MSTCRH write cycle MSTCRH write cycle High impedance φ pin T3 Figure 18 3 Starting and Stopping of System Clock Output Table 18 4 φ Pin State in Various Operating States Operating State PSTOP 0 PSTOP 1 Hardware standby High impedance High impedanc...

Page 467: ...age except for port 7 Vin 0 3 to VCC 0 3 V Input voltage port 7 Vin 0 3 to AVCC 0 3 V Reference voltage VREF 0 3 to AVCC 0 3 V Analog power supply voltage AVCC 0 3 to 7 0 V Analog input voltage VAN 0 3 to AVCC 0 3 V Operating temperature Topr Regular specifications 20 to 75 C Wide range specifications 40 to 85 C Storage temperature Tstg 55 to 125 C Caution Permanent damage to the chip may result i...

Page 468: ... 0 4 VCC 0 7 V V V Input high voltage RES STBY NMI MD2 to MD0 VIH VCC 0 7 VCC 0 3 V EXTAL VCC 0 7 VCC 0 3 V Port 7 2 0 AVCC 0 3 V Ports 4 to 6 P83 P84 P90 to P95 port B 2 0 VCC 0 3 V Input low voltage RES STBY MD2 to MD0 VIL 0 3 0 5 V NMI EXTAL ports 4 to 7 P83 P84 P90 to P95 port B 0 3 0 8 V Output high voltage All output pins except RESO VOH VCC 0 5 3 5 V V IOH 200 µA IOH 1 mA Output low voltage...

Page 469: ...73 mA f 20 MHz TBD mA f 25 MHz Module standby mode 19 5 0 V 51 mA f 20 MHz TBD mA f 25 MHz Standby mode 0 01 5 0 µA Ta 50 C 20 0 µA 50 C Ta Analog power supply current During A D conversion AICC 0 6 1 5 mA During A D and D A conversion 0 6 1 5 mA Idle 0 01 5 0 µA DASTE 0 Reference current During A D conversion AICC 0 5 0 8 mA During A D and D A conversion 2 0 3 0 mA Idle 0 01 5 0 µA DASTE 0 RAM st...

Page 470: ... VIL max 0 5 V Also the aforesaid current consumption values are when VIH min VCC 0 9 and VIL max 0 3 V under the condition of VRAM VCC 4 5 V 3 ICC max under normal operations 1 0 mA 0 90 mA MHz V VCC f ICC max when using the sleeve 1 0 mA 0 65 mA MHz V VCC f ICC max when the sleeve module are standing by 1 0 mA 0 45 mA MHz V VCC f Also the typ values for current dissipation are reference values ...

Page 471: ... 0 7 VCC 0 3 V Port 7 VCC 0 7 AVCC 0 3 V Ports 4 to 6 P83 P84 P90 to P95 port B VCC 0 7 VCC 0 3 V Input low voltage RES STBY MD2 to MD0 VIL 0 3 VCC 0 1 V NMI EXTAL ports 4 to 7 P83 P84 P90 to P95 port B 0 3 VCC 0 2 0 8 V V VCC 4 0 V VCC 4 0 to 5 5 V Output high voltage All output pins except RESO VOH VCC 0 5 V IOH 200 µA VCC 1 0 V IOH 1 mA Output low voltage All output pins except RESO VOL 0 4 V I...

Page 472: ...0 V During A D and D A conversion 0 2 0 5 mA AVCC 3 0 V Idle 0 01 5 0 µA DASTE 0 Reference current During A D conversion AICC 0 3 0 5 mA VREF 3 0 V During A D and D A conversion 1 2 2 0 mA VREF 3 0 V Idle 0 01 5 0 µA DASTE 0 RAM standby voltage VRAM 2 0 V Notes 1 Do not open the pin connections of the AVCC VREF and AVSS pins while the A D converter is not in use Connect the AVCC and VREF pins to t...

Page 473: ...erations 1 0 mA 0 90 mA MHz V VCC f ICC max when using the sleeve 1 0 mA 0 65 mA MHz V VCC f ICC max when the sleeve module are standing by 1 0 mA 0 45 mA MHz V VCC f Also the typ values for current dissipation are reference values ...

Page 474: ... 0 7 VCC 0 3 V Port 7 VCC 0 7 AVCC 0 3 V Ports 4 to 6 P83 P84 P90 to P95 port B VCC 0 7 VCC 0 3 V Input low voltage RES STBY MD2 to MD0 VIL 0 3 VCC 0 1 V NMI EXTAL ports 4 to 7 P83 P84 P90 to P95 port B 0 3 VCC 0 2 0 8 V V VCC 4 0 V VCC 4 0 to 5 5 V Output high voltage All output pins except RESO VOH VCC 0 5 V IOH 200 µA VCC 1 0 V IOH 1 mA Output low voltage All output pins except RESO VOL 0 4 V I...

Page 475: ... V During A D and D A conversion 0 2 0 5 mA AVCC 3 0 V Idle 0 01 5 0 µA DASTE 0 Reference current During A D conversion AICC 0 3 0 5 mA VREF 3 0 V During A D and D A conversion 1 2 2 0 mA VREF 3 0 V Idle 0 01 5 0 µA DASTE 0 RAM standby voltage VRAM 2 0 V Notes 1 Do not open the pin connections of the AVCC VREF and AVSS pins while the A D converter is not in use Connect the AVCC and VREF pins to th...

Page 476: ...rations 1 0 mA 0 90 mA MHz V VCC f ICC max when using the sleeve 1 0 mA 0 65 mA MHz V VCC x f ICC max when the sleeve module are standing by 1 0 mA 0 45 mA MHz V VCC f Also the typ values for current dissipation are reference values ...

Page 477: ...t total Total of 20 pins in A19 to A0 ΣIOL 80 mA Total of all output pins including the above 120 mA Permissible output high current per pin All output pins IOH 2 0 mA Permissible output high current total Total of all output pins ΣIOH 40 mA Notes 1 To protect chip reliability do not exceed the output current values in table 19 3 2 When directly driving a darlington pair or LED always insert a cur...

Page 478: ... 7 to AVCC VSS AVSS 0 V Condition B VCC 3 0 to 5 5 V AVCC 3 0 to 5 5 V VREF 3 0 to AVCC VSS AVSS 0 V Condition C VCC 5 0 V 10 AVCC 5 0 V 10 VREF 4 5 to AVCC VSS AVSS 0 V Condition A B C Test Item Symbol Min Max Min Max Min Max Unit Conditions Clock cycle time Clock pulse low width tcyc tCL 100 30 1000 76 9 18 1000 50 15 1000 ns ns Figure 19 3 to figure 19 15 Clock pulse high width tCH 30 18 15 ns ...

Page 479: ...5 0 V 10 VREF 4 5 to AVCC VSS AVSS 0 V Condition A B C Test Item Symbol Min Max Min Max Min Max Unit Conditions RES setup time tRESS 200 200 150 ns Figure 19 4 RES pulse width tRESW 10 10 10 tcyc Mode programming setup time tMDS 200 200 200 ns RESO output delay time tRESD 100 100 50 ns Figure 19 5 RESO output pulse width tRESOW 132 132 132 tcyc NMI IRQ setup time tNMIS 200 200 150 ns Figure 19 6 N...

Page 480: ...ess delay time Address hold time Read strobe delay time tAD tAH tRSD 0 5 tcyc 45 50 60 0 5 tcyc 35 40 50 0 5 tcyc 20 25 25 ns ns ns Figure 19 7 figure 19 8 Address strobe delay time tASD 60 50 25 ns Write strobe delay time tWSD 60 50 25 ns Strobe delay time tSD 60 50 25 ns Write strobe pulse width 1 tWSW1 1 0 tcyc 50 1 0 tcyc 40 1 0 tcyc 25 ns Write strobe pulse width 2 tWSW2 1 5 tcyc 50 1 5 tcyc ...

Page 481: ...data access time 3 tACC3 1 5 tcyc 100 1 5 tcyc 80 1 5 tcyc 45 ns Read data access time 4 tACC4 2 5 tcyc 100 2 5 tcyc 80 2 5 tcyc 45 ns Precharge time 1 tPCH1 1 0 tcyc 40 1 0 tcyc 30 1 0 tcyc 20 ns Precharge time 2 tPCH2 0 5 tcyc 40 0 5 tcyc 30 0 5 tcyc 20 ns Wait setup time tWTS 40 40 25 ns Figure 19 9 Wait hold time tWTH 5 5 5 ns Bus request setup time tBRQS 40 40 25 ns Figure 19 10 Bus acknowled...

Page 482: ...Output data delay time Input data setup time tPWD tPRS 50 100 50 100 50 50 ns ns Figure 19 11 Input data hold time tPRH 50 50 50 ns 16 bit timer Timer output delay time tTOCD 100 100 50 ns Figure 19 12 Timer input setup time tTICS 50 50 50 ns Timer clock input setup time tTCKS 50 50 50 ns Figure 19 13 Timer clock pulse width Single edge Both edges tTCKWH tTCKWL 1 5 2 5 1 5 2 5 1 5 2 5 tcyc tcyc 8 ...

Page 483: ...nput clock pulse width tSCKW 0 4 0 6 0 4 0 6 0 4 0 6 tScyc Transmit data delay time tTXD 100 100 100 ns Figure 19 15 Receive data setup time synchronous tRXS 100 100 100 ns Receive data hold Clock input tRXH 100 100 100 ns time syn chronous Clock output 0 0 0 ns C RH RL Chip output pin C 90 pF ports 4 6 8 A19 to A0 D15 to D8 C 30 pF ports 9 A B RESO Input output timing measurement levels Low 0 8 V...

Page 484: ...V fmax 13 MHz Condition C VCC 5 0 V 10 AVCC 5 0 V 10 VREF 4 5 to AVCC VSS AVSS 0 V fmax 25 MHz Condition A B C Item Min Typ Max Min Typ Max Min Typ Max Unit Conver sion time 134 states Resolution Conversion time single mode 10 10 10 134 10 10 10 134 10 10 10 134 bits tcyc Analog input capacitance 20 20 20 pF Permissible signal source impedance φ 13 MHz φ 13 MHz 4 0 V AVCC 5 5 V 10 10 10 5 kΩ kΩ kΩ...

Page 485: ...10 10 70 10 10 10 70 bits tcyc Analog input capacitance 20 20 20 pF Permissible signal source impedance φ 13 MHz φ 13 MHz 4 0 V AVCC 5 5 V 5 5 5 3 kΩ kΩ kΩ 2 7 V AVCC 4 0 V 3 3 kΩ Nonlinearity error 15 5 15 5 7 5 LSB Offset error 15 5 15 5 7 5 LSB Full scale error 15 5 15 5 7 5 LSB Quantization error 0 5 0 5 0 5 LSB Absolute accuracy 16 16 8 0 LSB ...

Page 486: ...7 to AVCC VSS AVSS 0 V fmax 10 MHz Condition B VCC 3 0 to 5 5 V AVCC 3 0 to 5 5 V VREF 3 0 to AVCC VSS AVSS 0 V fmax 13 MHz Condition C VCC 5 0 V 10 AVCC 5 0 V 10 VREF 4 5 to AVCC VSS AVSS 0 V fmax 25 MHz Condition A B C Test Item Min Typ Max Min Typ Max Min Typ Max Unit Conditions Resolution 8 8 8 8 8 8 8 8 8 bits Conversion time setting time 10 10 10 µs 20 pF capacitive load Absolute accuracy 2 ...

Page 487: ...This section shows timing diagrams 19 6 1 Clock Timing Clock timing is shown as follows Oscillator settling timing Figure 19 3 shows the oscillator settling timing φ VCC STBY RES tOSC1 tOSC1 Figure 19 3 Oscillator Settling Timing ...

Page 488: ...s the reset input timing Reset output timing Figure 19 5 shows the reset output timing Interrupt input timing Figure 19 6 shows the interrupt input timing for NMI and IRQ5 to IRQ0 φ tRESS tRESS tRESW tMDS RES FWE MD2 to MD0 Figure 19 4 Reset Input Timing φ RESO tRESD tRESOW tRESD Figure 19 5 Reset Output Timing ...

Page 489: ...473 φ NMI IRQ IRQ E L tNMIS tNMIH tNMIS tNMIH tNMIS tNMIW NMI IRQ j IRQ Edge sensitive IRQ Level sensitive IRQ i 0 to 5 E L i i IRQ j 0 to 5 Figure 19 6 Interrupt Input Timing ...

Page 490: ...access cycle Basic bus cycle three state access Figure 19 8 shows the timing of the external three state access cycle Basic bus cycle three state access with one wait state Figure 19 9 shows the timing of the external three state access cycle with one wait state inserted Bus release mode timing Figure 19 10 shows the bus release mode timing ...

Page 491: ...tPCH2 tRDH tPCH1 tSD tAH tASD tACC3 tAS1 tACC1 tASD tAS1 tWSW1 tWDS1 tWDH tWDD φ A23 to A0 CSn AS RD read D15 to D0 read HWR LWR write D15 to D0 write Note Specification from the earliest negation timing of A23 to A0 CSn and RD tRSD Figure 19 7 Basic Bus Cycle Two State Access ...

Page 492: ...476 T1 T2 T3 tACC4 tACC4 tAS2 tWDS2 tWSW2 tWSD tWDD tACC2 tRDS φ A23 to A0 CSn AS RD read D15 to D0 read HWR LWR write D15 to D0 write Figure 19 8 Basic Bus Cycle Three State Access ...

Page 493: ... D15 to D0 read HWR LWR write D15 to D0 write WAIT tWTH A23 to A0 CSn Figure 19 9 Basic Bus Cycle Three State Access with One Wait State BREQ BACK φ A23 to A0 AS RD HWR LWR tBRQS tBRQS tBACD1 tBZD tBACD2 tBZD Figure 19 10 Bus Release Mode Timing ...

Page 494: ... Output Timing 16 bit timer and 8 bit timer timing is shown below Timer input output timing Figure 19 12 shows the timer input output timing Timer external clock input timing Figure 19 13 shows the timer external clock input timing φ Output compare 1 Input capture 2 tTOCD tTICS Notes 1 TIOCA0 to TIOCA2 TIOCB0 to TIOCB2 TMO0 TMO2 TMIO1 TMIO3 2 TIOCA0 to TIOCA2 TIOCB0 to TIOCB2 TMIO1 TMIO3 Figure 19...

Page 495: ...ock timing Figure 19 14 shows the SCI input clock timing SCI input output timing synchronous mode Figure 19 15 shows the SCI input output timing in synchronous mode SCK0 SCK1 tSCKW tScyc tSCKr tSCKf Figure 19 14 SCI Input Clock Timing tScyc tTXD tRXS tRXH SCK0 SCK1 TxD0 TxD1 transmit data RxD0 RxD1 receive data Figure 19 15 SCI Input Output Timing in Synchronous Mode ...

Page 496: ...480 ...

Page 497: ...flow flag in CCR C C carry flag in CCR disp Displacement Transfer from the operand on the left to the operand on the right or transition from the state on the left to the state on the right Addition of the operands on both sides Subtraction of the operand on the right from the operand on the left Multiplication of the operands on both sides Division of the operand on the left by the operand on the...

Page 498: ... Notation Symbol Description Changed according to execution result Undetermined no guaranteed value 0 Cleared to 0 1 Set to 1 Not affected by execution of the instruction Varies depending on conditions described in notes ...

Page 499: ...s ERd MOV B Rs aa 8 MOV B Rs aa 16 MOV B Rs aa 24 MOV W xx 16 Rd MOV W Rs Rd MOV W ERs Rd MOV W d 16 ERs Rd MOV W d 24 ERs Rd MOV W ERs Rd MOV W aa 16 Rd B B B B B B B B B B B B B B B B W W W W W W W 2 2 2 4 8 2 2 4 6 2 4 8 2 2 4 6 4 2 2 4 8 2 4 xx 8 Rd8 Rs8 Rd8 ERs Rd8 d 16 ERs Rd8 d 24 ERs Rd8 ERs Rd8 ERs32 1 ERs32 aa 8 Rd8 aa 16 Rd8 aa 24 Rd8 Rs8 ERd Rs8 d 16 ERd Rs8 d 24 ERd ERd32 1 ERd32 Rs8 ...

Page 500: ...OV L ERs d 16 ERd MOV L ERs d 24 ERd MOV L ERs ERd MOV L ERs aa 16 MOV L ERs aa 24 POP W Rn POP L ERn W W W W W W W L L L L L L L L L L L L L L W L 6 2 4 8 2 4 6 6 2 4 6 10 4 6 8 4 6 10 4 6 8 2 4 aa 24 Rd16 Rs16 ERd Rs16 d 16 ERd Rs16 d 24 ERd ERd32 2 ERd32 Rs16 ERd Rs16 aa 16 Rs16 aa 24 xx 32 Rd32 ERs32 ERd32 ERs ERd32 d 16 ERs ERd32 d 24 ERs ERd32 ERs ERd32 ERs32 4 ERs32 aa 16 ERd32 aa 24 ERd32 ...

Page 501: ...nic Operation Condition Code Operand Size xx Rn ERn d ERn ERn ERn aa d PC aa Addressing Mode and Instruction Length bytes Normal Advanced No of States 1 I H N Z V C ADD B xx 8 Rd ADD B Rs Rd ADD W xx 16 Rd ADD W Rs Rd ADD L xx 32 ERd ADD L ERs ERd ADDX B xx 8 Rd ADDX B Rs Rd ADDS L 1 ERd ADDS L 2 ERd ADDS L 4 ERd INC B Rd INC W 1 Rd INC W 2 Rd B B W W L L B B L L L B W W 2 2 4 2 6 2 2 2 2 2 2 2 2 ...

Page 502: ... B Rs Rd L L B B W W L L B B L L L B W W L L B B W B W B 2 2 2 2 4 2 6 2 2 2 2 2 2 2 2 2 2 2 2 2 2 4 4 2 ERd32 1 ERd32 ERd32 2 ERd32 Rd8 decimal adjust Rd8 Rd8 Rs8 Rd8 Rd16 xx 16 Rd16 Rd16 Rs16 Rd16 ERd32 xx 32 ERd32 ERd32 ERs32 ERd32 Rd8 xx 8 C Rd8 Rd8 Rs8 C Rd8 ERd32 1 ERd32 ERd32 2 ERd32 ERd32 4 ERd32 Rd8 1 Rd8 Rd16 1 Rd16 Rd16 2 Rd16 ERd32 1 ERd32 ERd32 2 ERd32 Rd8 decimal adjust Rd8 Rd8 Rs8 R...

Page 503: ...Rd EXTS W Rd EXTS L ERd W B W B B W W L L B W L W L W L 2 4 4 2 2 4 2 6 2 2 2 2 2 2 2 2 ERd32 Rs16 ERd32 Ed remainder Rd quotient unsigned division Rd16 Rs8 Rd16 RdH remainder RdL quotient signed division ERd32 Rs16 ERd32 Ed remainder Rd quotient signed division Rd8 xx 8 Rd8 Rs8 Rd16 xx 16 Rd16 Rs16 ERd32 xx 32 ERd32 ERs32 0 Rd8 Rd8 0 Rd16 Rd16 0 ERd32 ERd32 0 bits 15 to 8 of Rd16 0 bits 31 to 16 ...

Page 504: ... XOR B Rs Rd XOR W xx 16 Rd XOR W Rs Rd XOR L xx 32 ERd XOR L ERs ERd NOT B Rd NOT W Rd NOT L ERd B B W W L L B B W W L L B B W W L L B W L 2 2 4 2 6 4 2 2 4 2 6 4 2 2 4 2 6 4 2 2 2 Rd8 xx 8 Rd8 Rd8 Rs8 Rd8 Rd16 xx 16 Rd16 Rd16 Rs16 Rd16 ERd32 xx 32 ERd32 ERd32 ERs32 ERd32 Rd8 xx 8 Rd8 Rd8 Rs8 Rd8 Rd16 xx 16 Rd16 Rd16 Rs16 Rd16 ERd32 xx 32 ERd32 ERd32 ERs32 ERd32 Rd8 xx 8 Rd8 Rd8 Rs8 Rd8 Rd16 xx 1...

Page 505: ...LL B Rd SHLL W Rd SHLL L ERd SHLR B Rd SHLR W Rd SHLR L ERd ROTXL B Rd ROTXL W Rd ROTXL L ERd ROTXR B Rd ROTXR W Rd ROTXR L ERd ROTL B Rd ROTL W Rd ROTL L ERd ROTR B Rd ROTR W Rd ROTR L ERd B W L B W L B W L B W L B W L B W L B W L B W L 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C MSB LSB C MSB LSB C MS...

Page 506: ...TST xx 3 Rd BTST xx 3 ERd BTST xx 3 aa 8 BTST Rn Rd BTST Rn ERd BTST Rn aa 8 BLD xx 3 Rd B B B B B B B B B B B B B B B B B B B B B B B B B 2 4 4 2 4 4 2 4 4 2 4 4 2 4 4 2 4 4 2 4 4 2 4 4 2 xx 3 of Rd8 1 xx 3 of ERd 1 xx 3 of aa 8 1 Rn8 of Rd8 1 Rn8 of ERd 1 Rn8 of aa 8 1 xx 3 of Rd8 0 xx 3 of ERd 0 xx 3 of aa 8 0 Rn8 of Rd8 0 Rn8 of ERd 0 Rn8 of aa 8 0 xx 3 of Rd8 xx 3 of Rd8 xx 3 of ERd xx 3 of E...

Page 507: ... xx 3 ERd BXOR xx 3 aa 8 BIXOR xx 3 Rd BIXOR xx 3 ERd BIXOR xx 3 aa 8 B B B B B B B B B B B B B B B B B B B B B B B B B B B B B 4 4 2 4 4 2 4 4 2 4 4 2 4 4 2 4 4 2 4 4 2 4 4 2 4 4 2 4 4 xx 3 of ERd C xx 3 of aa 8 C xx 3 of Rd8 C xx 3 of ERd C xx 3 of aa 8 C C xx 3 of Rd8 C xx 3 of ERd24 C xx 3 of aa 8 C xx 3 of Rd8 C xx 3 of ERd24 C xx 3 of aa 8 C xx 3 of Rd8 C C xx 3 of ERd24 C C xx 3 of aa 8 C C...

Page 508: ... BHI d 16 BLS d 8 BLS d 16 BCC d 8 BHS d 8 BCC d 16 BHS d 16 BCS d 8 BLO d 8 BCS d 16 BLO d 16 BNE d 8 BNE d 16 BEQ d 8 BEQ d 16 BVC d 8 BVC d 16 BVS d 8 BVS d 16 BPL d 8 BPL d 16 BMI d 8 BMI d 16 BGE d 8 BGE d 16 BLT d 8 BLT d 16 BGT d 8 BGT d 16 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 If condition is true then PC PC d else next 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 ...

Page 509: ...ced No of States 1 I H N Z V C BLE d 8 BLE d 16 JMP ERn JMP aa 24 JMP aa 8 BSR d 8 BSR d 16 JSR ERn JSR aa 24 JSR aa 8 2 4 2 4 2 2 4 2 4 2 2 PC ERn PC aa 24 PC aa 8 PC SP PC PC d 8 PC SP PC PC d 16 PC SP PC ERn PC SP PC aa 24 PC SP PC aa 8 PC SP 4 6 4 6 8 6 8 6 8 8 8 10 8 10 8 10 12 10 Branch Condition If condition is true then PC PC d else next Z N V 1 ...

Page 510: ... CCR ERd STC CCR d 16 ERd STC CCR d 24 ERd STC CCR ERd STC CCR aa 16 STC CCR aa 24 ANDC xx 8 CCR ORC xx 8 CCR XORC xx 8 CCR NOP B B W W W W W W B W W W W W W B B B 2 2 2 4 6 10 4 6 8 2 4 6 10 4 6 8 2 2 2 2 PC SP CCR SP vector PC CCR SP PC SP Transition to powerdown state xx 8 CCR Rs8 CCR ERs CCR d 16 ERs CCR d 24 ERs CCR ERs CCR ERs32 2 ERs32 aa 16 CCR aa 24 CCR CCR Rd8 CCR ERd CCR d 16 ERd CCR d ...

Page 511: ... cases see section A 3 Number of States Required for Execution 2 n is the value set in register R4L or R4 1 Set to 1 when a carry or borrow occurs at bit 11 otherwise cleared to 0 2 Set to 1 when a carry or borrow occurs at bit 27 otherwise cleared to 0 3 Retains its previous value when the result is zero otherwise cleared to 0 4 Set to 1 when the adjustment produces a carry otherwise retains its ...

Page 512: ...AND LDC BNQ TRAPA BLD BILD BST BIST BVC MOV BPL JMP BMI ADDX SUBX BGT JSR BLE MOV ADD ADDX CMP SUBX OR XOR AND MOV Instruction when most significant bit of BH is 0 Instruction when most significant bit of BH is 1 Instruction code Table A 2 2 Table A 2 2 Table A 2 2 Table A 2 2 Table A 2 2 BVS BLT BGE BSR Table A 2 2 Table A 2 2 Table A 2 2 Table A 2 2 Table A 2 2 Table A 2 2 Table A 2 2 Table A 2 ...

Page 513: ...CMP LDC STC BCC OR OR BPL BGT Instruction code BVS SLEEP BVC BGE Table A 2 3 Table A 2 3 Table A 2 3 BNE AND AND INC EXTU DEC BEQ INC EXTU DEC BCS XOR XOR SHLL SHLR ROTXL ROTXR NOT BLS SUB SUB BRN ADD ADD INC EXTS DEC BLT INC EXTS DEC BLE SHAL SHAR ROTL ROTR NEG BMI 1st byte 2nd byte AH BH AL BL SUBS ADDS ADD MOV SUB CMP SHLL SHLR ROTXL ROTXR NOT SHAL SHAR ROTL ROTR NEG ...

Page 514: ...DIVXS BTST BTST BTST BTST OR XOR BOR BIOR BXOR BIXOR BAND BIAND AND BLD BILD BST BIST Instruction when most significant bit of DH is 0 Instruction when most significant bit of DH is 1 Instruction code 1 1 1 1 2 2 2 2 BOR BIOR BXOR BIXOR BAND BIAND BLD BILD BST BIST Notes 1 2 r is the register designation field aa is the absolute address field 1st byte 2nd byte AH BH AL BL 3rd byte CH DH CL DL 4th ...

Page 515: ...for execution of an instruction can be calculated from these two tables as follows Number of states I SI J SJ K SK L SL M SM N SN Examples of Calculation of Number of States Required for Execution Examples Advanced mode stack located in external address space on chip supporting modules accessed with 8 bit bus width external devices accessed in three states with one wait state and 16 bit bus width ...

Page 516: ...e On Chip Memory 8 Bit Bus 16 Bit Bus 2 State Access 3 State Access 2 State Access 3 State Access Instruction fetch SI 2 6 3 4 6 2m 2 3 m Branch address read SJ Stack operation SK Byte data access SL 3 2 3 m Word data access SM 6 4 6 2m Internal operation SN 1 Legend m Number of wait states inserted into external device access ...

Page 517: ...ERd ADD L ERs ERd 1 1 2 1 3 1 ADDS ADDS 1 2 4 ERd 1 ADDX ADDX xx 8 Rd ADDX Rs Rd 1 1 AND AND B xx 8 Rd AND B Rs Rd AND W xx 16 Rd AND W Rs Rd AND L xx 32 ERd AND L ERs ERd 1 1 2 1 3 2 ANDC ANDC xx 8 CCR 1 BAND BAND xx 3 Rd BAND xx 3 ERd BAND xx 3 aa 8 1 2 2 1 1 Bcc BRA d 8 BT d 8 BRN d 8 BF d 8 BHI d 8 BLS d 8 BCC d 8 BHS d 8 BCS d 8 BLO d 8 BNE d 8 BEQ d 8 BVC d 8 BVS d 8 BPL d 8 BMI d 8 BGE d 8 ...

Page 518: ... d 16 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 BCLR BCLR xx 3 Rd BCLR xx 3 ERd BCLR xx 3 aa 8 BCLR Rn Rd BCLR Rn ERd BCLR Rn aa 8 1 2 2 1 2 2 2 2 2 2 BIAND BIAND xx 3 Rd BIAND xx 3 ERd BIAND xx 3 aa 8 1 2 2 1 1 BILD BILD xx 3 Rd BILD xx 3 ERd BILD xx 3 aa 8 1 2 2 1 1 BIOR BIOR xx 8 Rd BIOR xx 8 ERd BIOR xx 8 aa 8 1 2 2 1 1 BIST BIST xx 3 Rd BIST xx 3 ERd BIST xx 3 aa 8 1 2 2...

Page 519: ...ET xx 3 Rd BSET xx 3 ERd BSET xx 3 aa 8 BSET Rn Rd BSET Rn ERd BSET Rn aa 8 1 2 2 1 2 2 2 2 2 2 BSR BSR d 8 Normal 2 1 Advanced 2 2 BSR d 16 Normal 2 1 2 Advanced 2 2 2 BST BST xx 3 Rd BST xx 3 ERd BST xx 3 aa 8 1 2 2 2 2 BTST BTST xx 3 Rd BTST xx 3 ERd BTST xx 3 aa 8 BTST Rn Rd BTST Rn ERd BTST Rn aa 8 1 2 2 1 2 2 1 1 1 1 BXOR BXOR xx 3 Rd BXOR xx 3 ERd BXOR xx 3 aa 8 1 2 2 1 1 CMP CMP B xx 8 Rd ...

Page 520: ...12 20 EEPMOV EEPMOV B EEPMOV W 2 2 2n 2 1 2n 2 1 EXTS EXTS W Rd EXTS L ERd 1 1 EXTU EXTU W Rd EXTU L ERd 1 1 INC INC B Rd INC W 1 2 Rd INC L 1 2 ERd 1 1 1 JMP JMP ERn 2 JMP aa 24 2 2 JMP aa 8Normal 2 1 2 Advanced 2 2 2 JSR JSR ERn Normal 2 1 Advanced 2 2 JSR aa 24 Normal 2 1 2 Advanced 2 2 2 JSR aa 8 Normal 2 1 1 Advanced 2 2 2 LDC LDC xx 8 CCR LDC Rs CCR LDC ERs CCR LDC d 16 ERs CCR LDC d 24 ERs ...

Page 521: ...d MOV W Rs Rd MOV W ERs Rd MOV W d 16 ERs Rd MOV W d 24 ERs Rd MOV W ERs Rd MOV W aa 16 Rd MOV W aa 24 Rd MOV W Rs ERd MOV W Rs d 16 ERd MOV W Rs d 24 ERd MOV W Rs ERd MOV W Rs aa 16 MOV W Rs aa 24 1 1 1 2 4 1 1 2 3 1 2 4 1 1 2 3 2 1 1 2 4 1 2 3 1 2 4 1 2 3 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 MOV L xx 32 ERd MOV L ERs ERd MOV L ERs ERd MOV L d 16 ERs ERd MOV L d 24 ERs ERd ...

Page 522: ...s ERd 1 1 12 20 NEG NEG B Rd NEG W Rd NEG L ERd 1 1 1 NOP NOP 1 NOT NOT B Rd NOT W Rd NOT L ERd 1 1 1 OR OR B xx 8 Rd OR B Rs Rd OR W xx 16 Rd OR W Rs Rd OR L xx 32 ERd OR L ERs ERd 1 1 2 1 3 2 ORC ORC xx 8 CCR 1 POP POP W Rn POP L ERn 1 2 1 2 2 2 PUSH PUSH W Rn PUSH L ERn 1 2 1 2 2 2 ROTL ROTL B Rd ROTL W Rd ROTL L ERd 1 1 1 ROTR ROTR B Rd ROTR W Rd ROTR L ERd 1 1 1 ROTXL ROTXL B Rd ROTXL W Rd RO...

Page 523: ...STC CCR Rd STC CCR ERd STC CCR d 16 ERd STC CCR d 24 ERd STC CCR ERd STC CCR aa 16 STC CCR aa 24 1 2 3 5 2 3 4 1 1 1 1 1 1 2 SUB SUB B Rs Rd SUB W xx 16 Rd SUB W Rs Rd SUB L xx 32 ERd SUB L ERs ERd 1 2 1 3 1 SUBS SUBS 1 2 4 ERd 1 SUBX SUBX xx 8 Rd SUBX Rs Rd 1 1 TRAPA TRAPA x 2 Normal 2 1 2 4 Advanced 2 2 2 4 XOR XOR B xx 8 Rd XOR B Rs Rd XOR W xx 16 Rd XOR W Rs Rd XOR L xx 32 ERd XOR L ERs ERd 1 ...

Page 524: ...PBDDR 8 PB7 DDR PB6 DDR PB5 DDR PB4 DDR PB3 DDR PB2 DDR PB1 DDR PB0 DDR Port B H EE00B H EE00C H EE00D H EE00E H EE00F H EE010 H EE011 MDCR 8 MDS2 MDS1 MDS0 System control H EE012 SYSCR 8 SSBY STS2 STS1 STS0 UE NMIEG SSOE RAME H EE013 BRCR 8 A23E A22E A21E A20E BRLE Bus controller H EE014 ISCR 8 IRQ5SC IRQ4SC IRQ3SC IRQ2SC IRQ1SC IRQ0SC Interrupt H EE015 IER 8 IRQ5E IRQ4E IRQ3E IRQ2E IRQ1E IRQ0E c...

Page 525: ...W60 W51 W50 W41 W40 H EE023 WCRL 8 W31 W30 W21 W20 W11 W10 W01 W00 H EE024 BCR 8 ICIS1 ICIS0 1 1 1 1 RDEA WAITE H EE025 H EE026 Reserved area access prohibited H EE027 H EE028 H EE029 H EE02A H EE02B H EE02C H EE02D H EE02E H EE02F H EE030 Reserved area access prohibited H EE031 H EE032 H EE033 H EE034 H EE035 H EE036 H EE037 H EE038 H EE039 H EE03A H EE03B H EE03C H EE03D H EE03E P4PCR 8 P47 PCR ...

Page 526: ... EE040 Reserved area access prohibited H EE041 H EE042 H EE043 H EE044 H EE045 H EE046 H EE047 H EE048 H EE049 H EE04A H EE04B H EE04C H EE04D H EE04E H EE04F H EE050 Reserved area access prohibited H EE051 H EE052 H EE053 H EE054 H EE055 H EE056 H EE057 H EE058 H EE059 H EE05A H EE05B H EE05C H EE05D H EE05E H EE05F ...

Page 527: ... EE060 Reserved area access prohibited H EE061 H EE062 H EE063 H EE064 H EE065 H EE066 H EE067 H EE068 H EE069 H EE06A H EE06B H EE06C H EE06D H EE06E H EE06F H EE070 Reserved area access prohibited H EE071 H EE072 H EE073 H EE074 H EE075 H EE076 H EE077 H EE078 H EE079 H EE07A H EE07B H EE07C H EE07D H EE07E H EE07F ...

Page 528: ... EE080 Reserved area access prohibited H EE081 H EE082 H EE083 H EE084 H EE085 H EE086 H EE087 H EE088 H EE089 H EE08A H EE08B H EE08C H EE08D H EE08E H EE08F H EE090 Reserved area access prohibited H EE091 H EE092 H EE093 H EE094 H EE095 H EE096 H EE097 H EE098 H EE099 H EE09A H EE09B H EE09C H EE09D H EE09E H EE09F ...

Page 529: ... EE0A0 Reserved area access prohibited H EE0A1 H EE0A2 H EE0A3 H EE0A4 H EE0A5 H EE0A6 H EE0A7 H EE0A8 H EE0A9 H EE0AA H EE0AB H EE0AC H EE0AD H EE0AE H EE0AF H EE0B0 Reserved area access prohibited H EE0B1 H EE0B2 H EE0B3 H EE0B4 H EE0B5 H EE0B6 H EE0B7 H EE0B8 H EE0B9 H EE0BA H EE0BB H EE0BC H EE0BD H EE0BE H EE0BF ...

Page 530: ... EE0C0 Reserved area access prohibited H EE0C1 H EE0C2 H EE0C3 H EE0C4 H EE0C5 H EE0C6 H EE0C7 H EE0C8 H EE0C9 H EE0CA H EE0CB H EE0CC H EE0CD H EE0CE H EE0CF H EE0D0 Reserved area access prohibited H EE0D1 H EE0D2 H EE0D3 H EE0D4 H EE0D5 H EE0D6 H EE0D7 H EE0D8 H EE0D9 H EE0DA H EE0DB H EE0DC H EE0DD H EE0DE H EE0DF ...

Page 531: ... EE0E0 Reserved area access prohibited H EE0E1 H EE0E2 H EE0E3 H EE0E4 H EE0E5 H EE0E6 H EE0E7 H EE0E8 H EE0E9 H EE0EA H EE0EB H EE0EC H EE0ED H EE0EE H EE0EF H EE0F0 Reserved area access prohibited H EE0F1 H EE0F2 H EE0F3 H EE0F4 H EE0F5 H EE0F6 H EE0F7 H EE0F8 H EE0F9 H EE0FA H EE0FB H EE0FC H EE0FD H EE0FE H EE0FF ...

Page 532: ... FFF20 Reserved area access prohibited H FFF21 H FFF22 H FFF23 H FFF24 H FFF25 H FFF26 H FFF27 H FFF28 H FFF29 H FFF2A H FFF2B H FFF2C H FFF2D H FFF2E H FFF2F H FFF30 Reserved area access prohibited H FFF31 H FFF32 H FFF33 H FFF34 H FFF35 H FFF36 H FFF37 H FFF38 H FFF39 H FFF3A H FFF3B H FFF3C H FFF3D H FFF3E H FFF3F ...

Page 533: ... Bit 2 Bit 1 Bit 0 Module Name H FFF40 H FFF41 H FFF42 H FFF43 H FFF44 H FFF45 H FFF46 H FFF47 H FFF48 H FFF49 H FFF4A H FFF4B H FFF4C H FFF4D H FFF4E H FFF4F H FFF50 H FFF51 H FFF52 H FFF53 H FFF54 H FFF55 H FFF56 H FFF57 H FFF58 H FFF59 H FFF5A H FFF5B H FFF5C H FFF5D H FFF5E H FFF5F ...

Page 534: ...R0 8 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 16 bit timer H FFF69 TIOR0 8 IOB2 IOB1 IOB0 IOA2 IOA1 IOA0 channel 0 H FFF6A 16TCNT0H 16 H FFF6B 16TCNT0L H FFF6C GRA0H 16 H FFF6D GRA0L H FFF6E GRB0H 16 H FFF6F GRB0L H FFF70 16TCR1 8 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 16 bit timer H FFF71 TIOR1 8 IOB2 IOB1 IOB0 IOA2 IOA1 IOA0 channel 1 H FFF72 16TCNT1H 16 H FFF73 16TCNT1L H FFF74 GRA1H 16 H F...

Page 535: ...87 TCORB1 16 H FFF88 8TCNT0 16 H FFF89 8TCNT1 16 H FFF8A H FFF8B H FFF8C TCSR 2 8 OVF WT IT TME CKS2 CKS1 CKS0 WDT H FFF8D TCNT 2 8 H FFF8E H FFF8F RSTCSR 2 8 WRST RSTOE H FFF90 8TCR2 16 CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0 8 bit timer H FFF91 8TCR3 16 CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0 channels 2 and 3 H FFF92 8TCSR2 16 CMFB CMFA OVF OIS3 OIS2 OS1 OS0 H FFF93 8TCSR3 16 CMFB CMFA O...

Page 536: ...NDR7 NDR6 NDR5 NDR4 H FFFA6 NDRB 3 8 NDR11 NDR10 NDR9 NDR8 H FFFA7 NDRA 3 8 NDR3 NDR2 NDR1 NDR0 H FFFA8 H FFFA9 H FFFAA H FFFAB H FFFAC H FFFAD H FFFAE H FFFAF H FFFB0 SMR 8 C A CHR PE O E STOP MP CKS1 CKS0 SCI channel 0 H FFFB1 BRR 8 H FFFB2 SCR 8 TIE RIE TE RE MPIE TEIE CKE1 CKE0 H FFFB3 TDR 8 H FFFB4 SSR 8 TDRE RDRF ORER FER ERSPER TEND MPB MPBT H FFFB5 RDR 8 H FFFB6 SCMR 8 SDIR SINV SMIF H FFF...

Page 537: ...H FFFCD H FFFCE H FFFCF H FFFD0 H FFFD1 H FFFD2 H FFFD3 P4DR 8 P47 P46 P45 P44 P43 P42 P41 P40 Port 4 H FFFD4 H FFFD5 P6DR 8 P67 P66 P65 P64 P63 P62 P61 P60 Port 6 H FFFD6 P7DR 8 P77 P76 P75 P74 P73 P72 P71 P70 Port 7 H FFFD7 P8DR 8 P84 P83 P82 P81 P80 Port 8 H FFFD8 P9DR 8 P95 P94 P93 P92 P91 P90 Port 9 H FFFD9 PADR 8 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 Port A H FFFDA PBDR 8 PB7 PB6 PB5 PB4 PB3 PB2 P...

Page 538: ...AD7 AD6 AD5 AD4 AD3 AD2 H FFFE5 ADDRCL 8 AD1 AD0 H FFFE6 ADDRDH 8 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 H FFFE7 ADDRDL 8 AD1 AD0 H FFFE8 ADCSR 8 ADF ADIE ADST SCAN CKS CH2 CH1 CH0 H FFFE9 ADCR 8 TRGE Notes 1 Writing to bits 5 to 2 of BCR is prohibited 2 For the procedure for writing to TCSR TCNT and RSTCSR see section 11 2 4 Notes on Register Rewriting 3 The address depends on the output trigger setting...

Page 539: ...put compare interrupt A enable 0 1 Interrupt requested by OCFA flag is disabled Interrupt requested by OCFA flag is enabled Input capture interrupt D enable 0 1 Interrupt requested by ICFD flag is disabled Interrupt requested by ICFD flag is enabled TIER Timer Interrupt Enable Register H 90 FRT Register abbreviation Register name Address to which register is mapped Name of on chip supporting modul...

Page 540: ...3 P43DDR 0 W 2 P42DDR 0 W 1 P41DDR 0 W 0 P40DDR Port 4 input output select 0 1 Generic input Generic output P6DDR Port 6 Data Direction Register H EE005 Port 6 Bit 7 6 P66DDR 5 P65DDR 4 P64DDR 3 P63DDR 2 P62DDR 1 P61DDR 0 P60DDR Initial value Read Write 1 0 W 0 W 0 W 0 W 0 W 0 W 0 W Port 6 input output select 0 1 Generic input Generic output ...

Page 541: ...ut output select 0 1 Generic input Generic output Initial value Read Write 1 1 1 0 W 0 W 0 W 0 W Modes 1 to 4 Modes 5 to 7 1 1 1 0 W 1 W P9DDR Port 9 Data Direction Register H EE008 Port 9 Bit Initial value Read Write 7 1 6 0 W 5 P95DDR 0 W 4 P94DDR 0 W 3 P93DDR 0 W 2 P92DDR 0 W 1 P91DDR 0 W 0 P90DDR Port 9 input output select 0 1 Generic input Generic output 1 ...

Page 542: ...Read Write 1 0 W 0 W 0 W 0 W Modes 3 and 4 Modes 1 and 2 0 W 0 W Port A input output select 0 1 Generic input Generic output 0 W 0 W 0 W 0 W 0 W PBDDR Port B Data Direction Register H EE00A Port B Bit Initial value Read Write 7 PB7DDR 0 W 6 PB6DDR 0 W 5 PB5DDR 0 W 4 PB4DDR 0 W 3 PB3DDR 0 W 2 PB2DDR 0 W 1 PB1DDR 0 W 0 PB0DDR Port B input output select 0 1 Generic input Generic output 0 W ...

Page 543: ...al value Read Write 1 7 1 6 0 5 0 4 0 3 R 2 MDS2 R 1 MDS1 R 0 MDS0 Mode select 2 to 0 0 1 0 1 Operating Mode Bit 2 MD2 Bit 1 MD1 Bit 0 MD0 0 1 0 1 Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Mode 7 0 1 0 1 0 1 Note Determined by the state of the mode pins MD2 to MD0 ...

Page 544: ...user bit Standby timer select 2 to 0 Bit 6 STS2 Waiting Time 8 192 states Waiting Time 16 384 states Waiting Time 32 768 states Waiting Time 65 536 states Waiting Time 131 072 states Waiting Time 26 2144 states Waiting Time 1 024 states Illegal setting Bit 5 STS1 Bit 4 STS0 Standby Timer 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Software standby 0 1 SLEEP instruction causes transition to sleep mode SLEEP instru...

Page 545: ...to an external device The bus can be released to an external device Initial value Read Write 1 R W 1 R W 1 R W 0 1 1 1 0 R W Modes 3 and 4 ISCR IRQ Sense Control Register H EE014 Interrupt Controller Bit Initial value Read Write 0 R W 7 0 R W 6 0 R W 5 IRQ5SC 0 R W 4 IRQ4SC 0 R W 3 IRQ3SC 0 R W 2 IRQ2SC 0 R W 1 IRQ1SC 0 R W 0 IRQ0SC IRQ5 to IRQ0 sense control 0 1 Interrupts are requested when IRQ5...

Page 546: ... Read Write 0 7 0 6 0 R W 5 IRQ5F 0 R W 4 IRQ4F 0 R W 3 IRQ3F 0 R W 2 IRQ2F 0 R W 1 IRQ1F 0 R W 0 IRQ0F IRQ5 to IRQ0 flags 0 Note Only 0 can be written to clear the flag Bits 5 to 0 IRQ5F to IRQ0F Setting and Clearing Conditions 1 n 5 to 0 Clearing conditions Read IRQnF when IRQnF 1 then write 0 in IRQnF IRQnSC 0 IRQn input is high and interrupt exception handling is being carried out IRQnSC 1 and...

Page 547: ...RQ5 Bit 3 IPRA3 Bit 2 IPRA2 Bit 1 IPRA1 Bit 0 IPRA0 WDT A D con verter 16 bit timer channel 0 16 bit timer channel 1 16 bit timer channel 2 IPRB Interrupt Priority Register B H EE019 Interrupt Controller Bit Initial value Read Write 0 R W 7 IPRB7 0 R W 6 IPRB6 0 R W 5 0 R W 4 0 R W 3 IPRB3 0 R W 2 IPRB2 0 R W 1 0 R W 0 Priority level B7 B6 B3 and B2 0 1 Priority level 0 low priority Priority level...

Page 548: ...trol Register H EE01A D A Bit Initial value Read Write 1 7 1 6 1 5 1 4 1 3 1 2 1 1 0 R W 0 DASTE D A standby enable 0 1 D A output is disabled in software standby mode D A output is enabled in software standby mode Initial value ...

Page 549: ... Register H EE01B System control Bit Initial value Read Write 1 7 1 6 1 5 1 4 1 3 1 2 0 R W 1 DIV1 0 R W 0 DIV0 Division ratio bits 1 and 0 Frequency Division Ratio Bit 1 DIV1 Bit 0 DIV0 1 1 1 2 1 4 1 8 0 1 0 1 0 1 Initial value ...

Page 550: ...dules in standby state Bit Initial value Read Write Reserved bits φ clock stop Enables or disables ø clock output MSTCRL Module Standby Control Register L H EE01D System control 7 6 5 4 3 2 1 0 MSTPL2 MSTPL3 MSTPL4 MSTPL0 R W R W R W R W R W R W R W R W 0 0 0 0 0 0 0 0 Module standby L4 to L2 L0 Selection bits for placing modules in standby state Reserved bits Bit Initial value Read Write ...

Page 551: ...cription ADRCTL Address update mode 2 is selected Address update mode 1 is selected Initial value 0 1 CSCR Chip Select Control Register H EE01F Bus controller Bit Initial value Read Write 0 R W 7 CS7E n 7 to 4 0 R W 6 CS6E 0 R W 5 CS5E 0 R W 4 CS4E 1 3 1 2 1 1 1 0 Chip select 7 to 4 enable Description Bit n CSnE Output of chip select signal CSn is disabled Initial value Output of chip select signa...

Page 552: ... 0 ABW7 to ABW0 Areas 7 to 0 are 16 bit access areas Areas 7 to 0 are 8 bit access areas 0 1 Modes 1 and 3 Modes 2 and 4 ASTCR Access State Control Register H EE021 Bus controller Bit Initial value Read Write 1 R W 7 AST7 1 R W 6 AST6 1 R W 5 AST5 1 R W 4 AST4 1 R W 3 AST3 1 R W 2 AST2 1 R W 1 AST1 1 R W 0 AST0 Area 7 to 0 access state control Number of States in Access Area Bits 7 to 0 AST7 to AS...

Page 553: ... wait control 1 and 0 0 1 0 1 No program wait is inserted 1 program wait state is inserted 2 program wait states are inserted 3 program wait states are inserted 1 0 Area 6 wait control 1 and 0 0 1 0 1 No program wait is inserted 1 program wait state is inserted 2 program wait states are inserted 3 program wait states are inserted 1 0 Area 7 wait control 1 and 0 0 1 0 1 No program wait is inserted ...

Page 554: ...tates are inserted 1 Area 1 wait control 1 and 0 0 0 1 0 1 No program wait is inserted 1 program wait state is inserted 2 program wait states are inserted 3 program wait states are inserted 1 Area 2 wait control 1 and 0 0 0 1 0 1 No program wait is inserted 1 program wait state is inserted 2 program wait states are inserted 3 program wait states are inserted 1 Area 3 wait control 1 and 0 0 0 1 0 1...

Page 555: ...cycle insertion 1 Notes 1 These bits can be read and written but must not be set to 1 Normal operation cannot be guaranteed if 1 is written in these bits 2 0 must not be written in bit 2 0 1 No idle cycle is inserted in case of consecutive external read cycles for different areas Idle cycle is inserted in case of consecutive external read cycles for different areas Area division unit select 0 1 Ar...

Page 556: ... P47PCR 0 R W 6 P46PCR 0 R W 5 P45PCR 0 R W 4 P44PCR 0 R W 3 P43PCR 0 R W 2 P42PCR 0 R W 1 P41PCR 0 R W 0 P40PCR Port 4 input pull up control 7 to 0 0 1 Input pull up transistor is off Input pull up transistor is on Note Valid when the corresponding P4DDR bit is cleared to 0 designating generic input ...

Page 557: ... Write 6 1 5 1 Reserved bits 4 1 3 1 2 STR2 0 R W 1 STR1 0 R W 0 STR0 0 R W 0 1 16TCNT0 is halted Initial value 16TCNT0 is counting Counter start 0 0 1 16TCNT1 is halted Initial value 16TCNT1 is counting Counter start 1 0 1 16TCNT2 is halted Initial value 16TCNT2 is counting Counter start 2 ...

Page 558: ...ous clearing of 16TCNT0 is possible Timer sync 0 0 1 Channel 1 timer counter 16TCNT1 operates independently 16TCNT1 presetting clearing is independent of other channels Initial value Channel 1 operates synchronously Synchronous presetting synchronous clearing of 16TCNT1 is possible Timer sync 1 0 1 Channel 2 timer counter 16TCNT2 operates independently 16TCNT2 presetting clearing is independent of...

Page 559: ...mode PWM mode 0 0 1 Channel 1 operates normally Initial value Channel 1 operates in PWM mode PWM mode 1 0 1 Channel 2 operates normally Initial value Channel 2 operates in PWM mode PWM mode 2 0 1 OVF is set to 1 in TISRC when 16TCNT2 overflows or underflows Initial value OVF is set to 1 in TISRC when 16TCNT2 overflows Flag direction 0 1 Channel 2 operates normally Initial value Channel 2 operates ...

Page 560: ...OCA0 is 0 TIOCA0 is 1 Output level setting A0 0 1 TIOCB0 is 0 TIOCB0 is 1 Output level setting B0 0 1 TIOCA1 is 0 TIOCA1 is 1 Output level setting A1 0 1 TIOCB1 is 0 TIOCB1 is 1 Output level setting B1 0 1 TIOCA2 is 0 TIOCA2 is 1 Output level setting A2 0 1 TIOCB2 is 0 Initial value Initial value Initial value Initial value Initial value Initial value TIOCB2 is 1 Output level setting B2 ...

Page 561: ...ions as an input capture register 0 1 Input capture compare match flag A2 Clearing conditions Read IMFA2 when IMFA2 1 then write 0 in IMFA2 Initial value Initial value Initial value Setting conditions 16TCNT2 GRA2 when GRA2 functions as an output compare register 16TCNT2 value is transferred to GRA2 by an input capture signal when GRA2 functions as an input capture register 0 1 IMIA0 interrupt req...

Page 562: ...ions as an input capture register 0 1 Input capture compare match flag B2 Clearing condition Read IMFB2 when IMFB2 1 then write 0 in IMFB2 Initial value Initial value Initial value Setting conditions 16TCNT2 GRB2 when GRB2 functions as an output compare register 16TCNT2 value is transferred to GRB2 by an input capture signal when GRB2 functions as an input capture register 0 1 IMIB0 interrupt requ...

Page 563: ...al value Initial value Initial value OVI2 interrupt requested by OVF2 flag is enabled Overflow interrupt enable 2 Bit Initial value Read Write Clearing condition Read OVF0 when OVF0 1 then write 0 in OVF0 Setting condition 16TCNT0 overflowed from H FFFF to H 0000 Overflow flag 0 0 1 Clearing condition Read OVF1 when OVF1 1 then write 0 in OVF1 Setting condition 16TCNT1 overflowed from H FFFF to H ...

Page 564: ... External clock B TCLKB input External clock C TCLKC input External clock D TCLKD input 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Clock edge 1 and 0 Description Bit 4 CKEG Bit 3 CKEG0 Rising edges counted Falling edges counted Both edges counted 0 1 0 0 1 Counter clear 1 and 0 Description Bit 6 CCLR1 Bit 5 CCLR0 16TCNT is not cleared 16TCNT is cleared by GRA compare match or input capture 16TCNT is cleared by G...

Page 565: ... compare register GRA is an input capture register I O control B2 to B0 Description Bit 6 IOB2 Bit 5 IOB1 Bit 4 IOB0 No output at compare match Initial value 0 output at GRB compare match 1 output at GRB compare match Output toggles at GRB compare match 1 output on channel 2 GRB captures rising edges of input GRB captures falling edges of input GRB captures both edges of input GRB is an output com...

Page 566: ...6 bit timer channel 0 Bit Initial value Read Write 1 R W 1 R W 1 R W 1 R W 1 R W 1 R W 1 R W 1 R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 R W 1 R W 1 R W 1 R W 1 R W 1 R W 1 R W 1 R W Output compare or input capture register GRB0 H L General Register B0 H L H FFF6E H FFF6F 16 bit timer channel 0 Bit Initial value Read Write 1 R W 1 R W 1 R W 1 R W 1 R W 1 R W 1 R W 1 R W 15 14 13 12 11 10 9 8 7 6...

Page 567: ...FF71 16 bit timer channel 1 7 1 Bit Initial value Read Write 6 IOB2 0 R W 5 IOB1 0 R W 4 IOB0 0 R W 3 1 2 IOA2 0 R W 1 IOA1 0 R W 0 IOA0 0 R W Note Bit functions are the same as for 16 bit timer channel 0 16TCNT1 H L Timer Counter 1 H L H FFF72 H FFF73 16 bit timer channel 1 Bit Initial value Read Write 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 R W 0 R...

Page 568: ...ead Write 1 R W 1 R W 1 R W 1 R W 1 R W 1 R W 1 R W 1 R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 R W 1 R W 1 R W 1 R W 1 R W 1 R W 1 R W 1 R W Note Bit functions are the same as for 16 bit timer channel 0 16TCR2 Timer Control Register 2 H FFF78 16 bit timer channel 2 7 1 Bit Initial value Read Write 6 CCLR1 0 R W 5 CCLR0 0 R W 4 CKEG1 0 R W 3 CKEG0 0 R W 2 TPSC2 0 R W 1 TPSC1 0 R W 0 TPSC0 0 R W ...

Page 569: ... Bit Initial value Read Write 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W Phase counting mode Other mode up down counter up counter GRA2 H L General Register A2 H L H FFF7C H FFF7D 16 bit timer channel 2 Bit Initial value Read Write 1 R W 1 R W 1 R W 1 R W 1 R W 1 R W 1 R W 1 R W 15 14 13 12 11 10 9 8 7 6 5 4...

Page 570: ...F7F 16 bit timer channel 2 Bit Initial value Read Write 1 R W 1 R W 1 R W 1 R W 1 R W 1 R W 1 R W 1 R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 R W 1 R W 1 R W 1 R W 1 R W 1 R W 1 R W 1 R W Note Bit functions are the same as for 16 bit timer channel 0 ...

Page 571: ... edges Counter clear 1 and 0 0 0 1 0 1 Clearing is disabled Cleared by compare match A Cleared by compare match B input capture B Cleared by input capture B 1 Timer overflow interrupt enable 0 1 OVI interrupt requested by OVF is disabled OVI interrupt requested by OVF is enabled Compare match interrupt enable A 0 1 CMIA interrupt requested by CMFA is disabled CMIA interrupt requested by CMFA is en...

Page 572: ...ter start requests by an external trigger are enabled and A D converter start requests by compare match A are disabled A D converter start requests by compare match A are enabled and A D converter start requests by an external trigger are disabled Timer overflow flag 0 Clearing condition Read OVF when OVF 1 then write 0 in OVF Bit Initial value Read Write 0 R W 1 7 CMFB 0 R W 1 6 CMFA 0 R W 1 5 OV...

Page 573: ...edges 1 Timer overflow flag 0 Clearing condition Read OVF when OVF 1 then write 0 in OVF 0 1 1 Setting condition 8TCNT overflows from H FF to H 00 Compare match input capture flag A 0 Clearing condition Read CMFA when CMFA 1 then write 0 in CMFA 1 Setting condition 8TCNT TCORA Compare match input capture flag B 0 Clearing condition Read CMFB when CMFB 1 then write 0 in CMFB 1 Setting conditions 8T...

Page 574: ...1 Time Constant Register B1 H FFF86 H FFF87 8 bit timer channel 0 8 bit timer channel 1 Bit Initial value Read Write 1 R W 1 R W 1 R W 1 R W 1 R W 1 R W 1 R W 1 R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 R W 1 R W 1 R W 1 R W 1 R W 1 R W 1 R W 1 R W TCORB0 TCORB1 8TCNT0 Timer Counter 0 8TCNT1 Timer Counter 1 H FFF88 H FFF89 8 bit timer channel 0 8 bit timer channel 1 Bit Initial value Read Write ...

Page 575: ... 1 0 1 0 1 0 1 1 0 1 Timer enable 0 Timer disabled TCNT is initialized to H 00 and halted 1 Timer enabled TCNT starts counting up Timer mode select 0 Interval timer requests interval timer interrupts 1 Watchdog timer generates a reset signal Overflow flag 0 Clearing condition Read OVF when OVF 1 then write 0 in OVF 1 Setting condition TCNT changes from H FF to H 00 Note Only 0 can be written to cl...

Page 576: ...ial value Read Write 0 R W 7 WRST 0 R W 6 RSTOE 1 5 1 4 1 3 1 2 1 1 1 0 Reset output enable 0 External output of reset signal is disabled External output of reset signal is enabled 1 Watchdog timer reset 0 Clearing conditions Reset signal at RES pin Read WRST when WRST 1 then write 0 in WRST 1 Setting condition TCNT overflow generates a reset signal during watchdog timer operation Note Only 0 can ...

Page 577: ... clear 1 and 0 0 0 1 0 1 Clearing is disabled Cleared by compare match A Cleared by compare match B input capture B Cleared by input capture B 1 Timer overflow interrupt enable 0 1 OVI interrupt requested by OVF is disabled OVI interrupt requested by OVF is enabled Compare match interrupt enable A 0 1 CMIA interrupt requested by CMFA is disabled CMIA interrupt requested by CMFA is enabled Compare ...

Page 578: ...earing condition Read CMFB when CMFB 1 then write 0 in CMFB 1 Setting conditions 8TCNT TCORB The 8TCNT value is transferred to TCORB by an input capture signal when TCORB functions as an input capture register Note Only 0 can be written to bits 7 to 5 to clear these flags Output select A1 and A0 0 Description Bit 1 OS1 Bit 0 OS0 1 0 1 No change at compare match A 0 output at compare match A 1 outp...

Page 579: ...3 Time Constant Register B3 H FFF96 H FFF97 8 bit timer channel 2 8 bit timer channel 3 Bit Initial value Read Write 1 R W 1 R W 1 R W 1 R W 1 R W 1 R W 1 R W 1 R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 R W 1 R W 1 R W 1 R W 1 R W 1 R W 1 R W 1 R W TCORB2 TCORB3 8TCNT2 Timer Counter 2 8TCNT3 Timer Counter 3 H FFF98 H FFF99 8 bit timer channel 2 8 bit timer channel 3 Bit Initial value Read Write ...

Page 580: ...l value Read Write 0 R W 7 0 R W 6 0 R W 5 0 R W 4 0 R W 3 0 R W 2 0 R W 1 0 R W 0 D A conversion data DADR1 D A Data Register 1 H FFF9D D A Bit Initial value Read Write 0 R W 7 0 R W 6 0 R W 5 0 R W 4 0 R W 3 0 R W 2 0 R W 1 0 R W 0 D A conversion data ...

Page 581: ...n is disabled in channel 0 D A conversion is enabled in channel 1 Description D A conversion is enabled in channels 0 and 1 D A conversion is enabled in channels 0 and 1 D A conversion is enabled in channels 0 and 1 Bit 6 Bit 5 DAOE0 DAE 0 0 0 1 1 1 0 1 1 0 0 1 0 1 0 1 D A output enable 0 0 DA0 analog output is disabled 1 Channel 0 D A conversion and DA0 analog output are enabled D A output enable...

Page 582: ...hange at compare match A in the selected 16 bit timer channel 1 Non overlapping TPC output in group 1 controlled by compare match A and B in the selected 16 bit timer channel Group 2 non overlap 0 Normal TPC output in group 2 Output values change at compare match A in the selected 16 bit timer channel 1 Non overlapping TPC output in group 2 controlled by compare match A and B in the selected 16 bi...

Page 583: ...re match in 16 bit timer channel 2 0 1 0 1 0 1 Group 2 compare match select 1 and 0 Bit 5 G2CMS1 16 Bit Timer Channel Selected as Output Trigger Bit 4 G2CMS0 TPC output group 2 TP11 to TP8 is triggered by compare match in 16 bit timer channel 0 TPC output group 2 TP11 to TP8 is triggered by compare match in 16 bit timer channel 1 TPC output group 2 TP11 to TP8 is triggered by compare match in 16 b...

Page 584: ...ransferred to PB7 to PB0 TPC outputs TP15 to TP8 are enabled NDR15 to NDR8 are transferred to PB7 to PB0 0 1 NDERA Next Data Enable Register A H FFFA3 TPC Bit Initial value Read Write 0 R W 7 NDER7 0 R W 6 NDER6 0 R W 5 NDER5 0 R W 4 NDER4 0 R W 3 NDER3 0 R W 2 NDER2 0 R W 1 NDER1 0 R W 0 NDER0 Next data enable 7 to 0 Bits 7 to 0 NDER7 to NDER0 Description TPC outputs TP7 to TP0 are disabled NDR7 ...

Page 585: ...e the next output data for TPC output group 2 Address H FFFA6 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 Bit Initial value Read Write Different triggers for TPC output groups 2 and 3 Address H FFFA4 Bit Initial value Read Write 0 R W 7 NDR15 0 R W 6 NDR14 0 R W 5 NDR13 0 R W 4 NDR12 1 3 1 2 1 1 1 0 Store the next output data for TPC output group 3 Address H FFFA6 Bit Initial value Read Write 0 R W 7 0 R W 6 ...

Page 586: ...e the next output data for TPC output group 0 Address H FFFA7 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 Bit Initial value Read Write Different triggers for TPC output groups 0 and 1 Address H FFFA5 Bit Initial value Read Write 0 R W 7 NDR7 0 R W 6 NDR6 0 R W 5 NDR5 0 R W 4 NDR4 1 3 1 2 1 1 1 0 Store the next output data for TPC output group 1 Address H FFFA7 Bit Initial value Read Write 0 R W 7 0 R W 6 0 R ...

Page 587: ...Bit 1 Clock Source CKS0 CKS1 0 1 0 1 Stop bit length 0 One stop bit Two stop bits 1 Parity mode 0 Even parity Odd parity 1 Parity enable 0 Parity bit is not added or checked Parity bit is added and checked 1 GSM mode for smart card interface 0 TEND flag is set 12 5 etu after start bit TEND flag is set 11 0 etu after start bit 1 Character length 0 8 bit data 7 bit data 1 Communication mode for seri...

Page 588: ...572 BRR Bit Rate Register H FFFB1 SCI0 Bit Initial value Read Write 1 R W 7 1 R W 6 1 R W 5 1 R W 4 1 R W 3 1 R W 2 1 R W 1 1 R W 0 Serial communication bit rate setting ...

Page 589: ...d for serial clock output Internal clock SCK pin used for clock output Internal clock SCK pin used for serial clock output External clock SCK pin used for clock input External clock SCK pin used for serial clock input External clock SCK pin used for clock input External clock SCK pin used for serial clock input Multiprocessor interrupt enable 0 1 Multiprocessor interrupts are disabled normal recei...

Page 590: ...574 TDR Transmit Data Register H FFFB3 SCI0 Bit Initial value Read Write 1 R W 7 1 R W 6 1 R W 5 1 R W 4 1 R W 3 1 R W 2 1 R W 1 1 R W 0 Serial transmit data ...

Page 591: ...al status for smart card interface 0 Clearing conditions Reset or transition to standby mode Read ERS when ERS 1 then write 0 in ERS Setting condition A low error signal is received 1 1 Overrun error 0 Clearing conditions Reset or transition to standby mode Read ORER when ORER 1 then write 0 in ORER Setting condition Overrun error reception of the next serial data ends when RDRF 1 1 Receive data r...

Page 592: ...576 RDR Receive Data Register H FFFB5 SCI0 Bit Initial value Read Write 0 R 7 0 R 6 0 R 5 0 R 4 0 R 3 0 R 2 0 R 1 0 R 0 Serial receive data ...

Page 593: ...0 1 Unmodified TDR contents are transmitted Receive data is stored unmodified in RDR Initial value Inverted 1 0 logic levels of TDR contents are transmitted 1 0 logic levels of received data are inverted before storage in RDR Smart card data transfer direction 0 1 TDR contents are transmitted LSB first Receive data is stored LSB first in RDR Initial value TDR contents are transmitted MSB first Rec...

Page 594: ...lue Read Write BRR Bit Rate Register H FFFB9 SCI1 1 R W 7 1 R W 6 1 R W 5 1 R W 4 1 R W 3 1 R W 2 1 R W 1 1 R W 0 Note Bit functions are the same as for SCI0 Bit Initial value Read Write SCR Serial Control Register H FFFBA SCI1 0 R W 7 TIE 0 R W 6 RIE 0 R W 5 TE 0 R W 4 RE 0 R W 3 MPIE 0 R W 2 TEIE 0 R W 1 CKE1 0 R W 0 CKE0 Note Bit functions are the same as for SCI0 Bit Initial value Read Write ...

Page 595: ...s Register H FFFBC SCI1 0 R W 7 TDRE 0 R W 6 RDRF 0 R W 5 ORER 0 R W 4 FER ERS 0 R W 3 PER 1 R 2 TEND 0 R 1 MPB 0 R W 0 MPBT Bit Initial value Read Write Notes Bit functions are the same as for SCI0 Only 0 can be written to clear the flag RDR Receive Data Register H FFFBD SCI1 0 R 7 0 R 6 0 R 5 0 R 4 0 R 3 0 R 2 0 R 1 0 R 0 Bit Initial value Read Write Note Bit functions are the same as for SCI0 ...

Page 596: ...580 SCMR Smart Card Mode Register H FFFBE SCI1 0 R W 7 0 R W 6 1 5 0 R W 4 3 SDIR 2 SINV 1 1 1 1 1 0 SMIF Bit Initial value Read Write Note Bit functions are the same as for SCI0 ...

Page 597: ...4 P44 0 R W 3 P43 0 R W 2 P42 0 R W 1 P41 0 R W 0 P40 Data for port 4 pins Bit Initial value Read Write P6DR Port 6 Data Register H FFFD5 Port 6 1 R 7 P67 0 R W 6 P66 0 R W 5 P65 0 R W 4 P64 0 R W 3 P63 0 R W 2 P62 0 R W 1 P61 0 R W 0 P60 Data for port 6 pins Bit Initial value Read Write ...

Page 598: ...R 3 P73 R 2 P72 R 1 P71 R 0 P70 Data for port 7 pins Note Determined by pins P77 to P70 Bit Initial value Read Write P8DR Port 8 Data Register H FFFD7 Port 8 1 7 1 6 1 5 0 R W 4 P84 0 R W 3 P83 0 R W 2 P82 0 R W 1 P81 0 R W 0 P80 Data for port 8 pins Bit Initial value Read Write ...

Page 599: ...e PADR Port A Data Register H FFFD9 Port A 0 R W 7 PA7 0 R W 6 PA6 0 R W 5 PA5 0 R W 4 PA4 0 R W 3 PA3 0 R W 2 PA2 0 R W 1 PA1 0 R W 0 PA0 Data for port A pins Bit Initial value Read Write PBDR Port B Data Register H FFFDA Port B 0 R W 7 PB7 0 R W 6 PB6 0 R W 5 PB5 0 R W 4 PB4 0 R W 3 PB3 0 R W 2 PB2 0 R W 1 PB1 0 R W 0 PB0 Data for port B pins Bit Initial value Read Write ...

Page 600: ...AD2 0 R 7 AD1 0 R 6 AD0 0 R 5 0 R 4 0 R 3 0 R 2 0 R 1 0 R 0 ADDRAH ADDRAL Bit Initial value Read Write ADDRB H L A D Data Register B H L H FFFE2 H FFFE3 A D 0 R 15 AD9 0 R 14 AD8 0 R 13 AD7 0 R 12 AD6 0 R 11 AD5 0 R 10 AD4 0 R 9 AD3 0 R 8 AD2 0 R 7 AD1 0 R 6 AD0 0 R 5 0 R 4 0 R 3 0 R 2 0 R 1 0 R 0 ADDRBH ADDRBL A D conversion data 10 bit data giving an A D conversion result Bit Initial value Read ...

Page 601: ... R 15 AD9 0 R 14 AD8 0 R 13 AD7 0 R 12 AD6 0 R 11 AD5 0 R 10 AD4 0 R 9 AD3 0 R 8 AD2 0 R 7 AD1 0 R 6 AD0 0 R 5 0 R 4 0 R 3 0 R 2 0 R 1 0 R 0 ADDRDH ADDRDL A D conversion data 10 bit data giving an A D conversion result Bit Initial value Read Write ADCR A D Control Register H FFFE9 A D 0 R W 7 TRGE 1 6 1 5 1 4 1 3 1 2 1 1 0 R W 0 Trigger Enable 0 1 A D conversion start by external trigger or 8 bit ...

Page 602: ...0 1 Single mode Scan mode A D start 0 1 A D conversion is stopped 1 Single mode A D conversion starts ADST is automatically cleared to 0 when conversion ends 2 Scan mode A D conversion starts and continues cycling among the selected channels ADST is cleared to 0 by software by a reset or by a transition to standby mode A D interrupt enable 0 1 A D end interrupt request is disabled A D end interrup...

Page 603: ...D R C P4 DDR n Q D R C P4 DR n WP4P RP4P WP4D WP4 RP4 n 0 to 7 Write to P4PCR Read P4PCR Write to P4DDR Write to port 4 Read port 4 Write to external address Hardware standby External bus released Read external address Internal data bus upper Internal data bus lower 8 bit bus mode 16 bit bus mode Figure C 1 Port 4 Block Diagram ...

Page 604: ...6 Write to P6DDR Write to port 6 Read port 6 RP6 input WP6D Reset Q D R C P6 DDR 0 WP6 Reset Q D R C P6 DR 0 P60 Internal data bus Bus controller WAIT input enable Bus controller WAIT Hardware Standby Figure C 2 a Port 6 Block Diagram Pin P60 ...

Page 605: ...Write to P6DDR Write to port 6 Read port 6 WP6D Reset Q D R C P6 DDR 1 WP6 Reset Q D R C P6 DR 1 RP6 Internal data bus Bus controller Bus release enable BREQ input Hardware Standby Figure C 2 b Port 6 Block Diagram Pin P61 ...

Page 606: ...re standby Q D R C P6 DDR 2 WP6 Reset Q D R C P6 DR 2 RP6 P62 WP6D WP6 RP6 Write to P6DDR Write to port 6 Read port 6 Internal data bus Bus controller Bus release enable BACK output Figure C 2 c Port 6 Block Diagram Pin P62 ...

Page 607: ...591 Read port 6 RP6 Hardware standby RP6 P67 φ output φ output enable Internal data bus Figure C 2 d Port 6 Block Diagram Pin P67 ...

Page 608: ...put enable Channel select signal Analog input Figure C 3 a Port 7 Block Diagram Pins P70 to P75 P7n RP7 RP7 Read port 7 n 6 7 Internal data bus D A converter Analog output Output enable A D converter Input enable Channel select signal Analog input Figure C 3 b Port 7 Block Diagram Pins P76 and P77 ...

Page 609: ...k Diagrams P80 RP8 WP8D Reset Q D R C P8 DDR 0 WP8 Reset Q D R C P8 DR 0 WP8D WP8 RP8 Write to P8DDR Write to port 8 Read port 8 Internal data bus Interrupt controller input IRQ0 Figure C 4 a Port 8 Block Diagram Pin P80 ...

Page 610: ...n 1 2 Write to P8DDR Write to port 8 Read port 8 Software standby output port enable Internal data bus Bus controller output Interrupt controller IRQ IRQ CS CS 2 3 1 2 input SSOE Software standby External bus released Hardware standby Figure C 4 b Port 8 Block Diagram Pins P81 and P82 ...

Page 611: ...tware standby output port enable WP8D WP8 RP8 SSOE WP8 R Reset Internal data bus RP8 P83 Bus controller CS1 output Reset Interrupt controller IRQ3 input ADTRG input P83DDR C Q D R SSOE Software standby External bus released Hardware standby Figure C 4 c Port 8 Block Diagram Pin P83 ...

Page 612: ...RP8 WP8D WP8 RP8 SSOE Write to P8DDR Write to port 8 Read port 8 Software standby output port enable Internal data bus Bus controller output 0 CS SSOE Software standby External bus released Hardware standby Reset R Figure C 4 d Port 8 Block Diagram Pin P84 ...

Page 613: ...P9 RP9 Write to P9DDR Write to port 9 Read port 9 P90 RP9 WP9D Reset Hardware standby Q D R C P9 DDR 0 WP9 Reset Q D R C P9 DR 0 Internal data bus SCI Output enable Serial transmit data Guard time Figure C 5 a Port 9 Block Diagram Pin P90 ...

Page 614: ...to P9DDR Write to port 9 Read port 9 P91 RP9 WP9D Reset Q D R C P9 DDR 1 WP9 Reset Q D R C P9 DR 1 Internal data bus SCI Output enable Serial transmit data Guard time Hardware standby Figure C 5 b Port 9 Block Diagram Pin P91 ...

Page 615: ...Write to P9DDR Write to port 9 Read port 9 P92 WP9D Reset Q D R C P9 DDR 2 WP9 Reset Q D R C P9 DR 2 RP9 Internal data bus Input enable Serial receive data SCI Hardware standby Figure C 5 c Port 9 Block Diagram Pin P92 ...

Page 616: ...D WP9D RP9 P93DR C Q D P93 Serial receive data Input enable Write to P9DDR Write to port 9 Read port 9 WP9D WP9 RP9 WP9 R R Reset Internal data bus Reset SCI Hardware standby Figure C 5 d Port 9 Block Diagram Pin P93 ...

Page 617: ...Read port 9 WP9D Hardware standby Reset Q D R C P9 DDR 4 WP9 Reset Q D R C P9 DR 4 RP9 P94 Internal data bus SCI Clock input enable Clock output enable Clock output Clock input Interrupt controller input IRQ4 Figure C 5 e Port 9 Block Diagram Pin P94 ...

Page 618: ...C Q D Reset P95 SCI Clock input enable Clock output enable Clock output Interrupt controller IRQ5 input Clock input Write to P9DDR Write to port 9 Read port 9 WP9D WP9 RP9 Internal data bus Hardware standby Figure C 5 f Port 9 Block Diagram Pin P95 ...

Page 619: ...rt A Read port A PAn WPAD Reset Hardware standby Q D R C PA DDR n Reset Q D R C PA DR n RPA WPA Internal data bus TPC output enable TPC Next data Output trigger Counter clock input 16 bit timer Counter clock input 8 bit timer Figure C 6 a Port A Block Diagram Pins PA0 and PA1 ...

Page 620: ...et Q D R C PA DDR n Reset Q D R C PA DR n Internal data bus TPC output enable TPC Next data Output trigger Output enable Compare match output Input capture Counter clock input 16 bit timer Counter clock input 8 bit timer Hardware standby Figure C 6 b Port A Block Diagram Pins PA2 and PA3 ...

Page 621: ...y output port enable PAn WPAD Reset RPA WPA Q D R C PAnDDR Reset Q D R C PAnDR Internal address bus Internal data bus TPC 16 bit timer TPC output enable Next data Output trigger Output enable Compare match output Input capture Software standby SSOE Bus released Modes 3 and 4 Address output enable Hardware standby Figure C 6 c Port A Block Diagram Pins PA4 to PA7 ...

Page 622: ...ble Reset Q D R C PB DDR n WPBD Reset Q D R C PB DR n WPB RPB Internal data bus TPC output enable TPC Next data Output trigger Output enable Compare match output 8 bit timer Mode 1 to 5 Bus released Bus controller CS output enable CS7 CS5 output Software standby Hardware standby SSOE Figure C 7 a Port B Block Diagram Pins PB0 and PB2 ...

Page 623: ...output enable CS6 CS4 output Next data Output trigger Output enable Compare match output TMO2 TMO3 input Write to PBDDR Write to port B Read port B Software standby output port enable WPBD WPB RPB SSOE n 1 3 Bus released Software standby SSOE Internal data bus Hardware standby Figure C 7 b Port B Block Diagram Pins PB1 and PB3 ...

Page 624: ...rite to PBDDR Write to port B Read port B WPB RPB Reset Q D R C PB DDR Hardware standby 4 WPBD Reset Q D R C PB DR 4 Internal data bus TPC output enable Next data Output trigger TPC Figure C 7 c Port B Block Diagram Pin PB4 ...

Page 625: ...eset WPBD WPB RPB R PB5DR C Q D Reset PB5 TPC TPC output enable Next data Output trigger Write to PBDDR Write to port B Read port B WPBD WPB RPB Internal data bus Hardware standby Figure C 7 d Port B Block Diagram Pin PB5 ...

Page 626: ... D R C PB DDR Q D R C PB DR 6 RPB WPB TPC WPBD WPB RPB Write to PBDDR Write to port B Read port B TPC output enable Next data Output trigger Internal data bus 6 PB6 Hardware standby Figure C 7 e Port B Block Diagram Pin PB6 ...

Page 627: ...et Q D R C PB DDR Q D R C PB DR 7 RPB WPB TPC WPBD WPB RPB Write to PBDDR Write to port B Read port B TPC output enable Next data Output trigger Internal data bus 7 Hardware standby Figure C 7 f Port B Block Diagram Pin PB7 ...

Page 628: ... 0 T SSOE 1 Keep T A15 to A8 D15 to D8 T T T T D15 to D8 P47 to P40 1 3 T T Keep Keep I O port 2 4 T T T T D7 to D0 A19 to A16 L T SSOE 0 T SSOE 1 Keep T A19 to A16 P60 T T Keep Keep I O port WAIT P61 T T BRLE 0 Keep BRLE 1 T T I O port BREQ P62 T T BRLE 0 Keep BRLE 1 H L BRLE 0 I O port BRLE 1 BACK AS RD HWR LWR H T SSOE 0 T SSOE 1 H T AS RD HWR LWR P67 Clock output T PSTOP 0 H PSTOP 1 Keep PSTOP...

Page 629: ...SSOE 1 H DDR 0 Keep DDR 1 T DDR 0 Input port DDR 1 CS2 P83 T T DDR 0 T DDR 1 SSOE 0 T DDR 1 SSOE 1 H DDR 0 Keep DDR 1 T DDR 0 Input port DDR 1 CS1 P84 H T DDR 0 T DDR 1 SSOE 0 T DDR 1 SSOE 1 H DDR 0 Keep DDR 1 T DDR 0 Input port DDR 1 CS0 P95 to P90 T T Keep Keep I O port PA3 to PA0 T T Keep Keep I O port PA6 to PA4 1 2 T T Keep Keep I O port 3 4 T T Address output 1 SSOE 0 T SSOE 1 Keep Otherwise...

Page 630: ...7 to CS4 Otherwise 4 I O port PB7 to PB4 T T Keep Keep I O port Legend H High L Low T High impedance state keep Input pins are in the high impedance state output pins maintain their previous state DDR Data direction register Notes 1 When A23E A22E A21E 0 in BRCR bus release control register 2 When A23E A22E A21E 1 in BRCR bus release control register 3 When CS7E CS6E CS5E CS4E 1 in CSCR chip selec...

Page 631: ... to D0 go to the high impedance state The address bus is initialized to the low output level 2 5 φ clock cycles after the low level of RES is sampled Clock pin P67 φ goes to the output state at the next rise of φ after RES goes low AS RD read D15 to D0 write HWR LWR write Internal reset signal RES P67 φ I O port CS7 to CS1 CS0 A19 to A0 T1 T2 T3 Access to external memory H 00000 High impedance Hig...

Page 632: ...fter the low level of RES is sampled However when PA4 to PA6 are used as address bus pins or when P83 to P81 and PB0 to PB3 are used as CS output pins they go to the high impedance state at the same time as RES goes low Clock pin P67 φ goes to the output state at the next rise of φ after RES goes low T1 T2 T3 Access to external memory H 00000 High impedance High impedance AS RD read D15 to D0 writ...

Page 633: ...em clock cycles before the STBY signal goes low as shown below RES must remain low until STBY goes low minimum delay from STBY low to RES high 0 ns t1 10tcyc t2 0 ns STBY RES 2 To retain RAM contents with the RAME bit cleared to 0 in SYSCR RES does not have to be driven low as in 1 Timing of Recovery from Hardware Standby Mode Drive the RES signal low approximately 100 ns before STBY goes high STB...

Page 634: ...e Hitachi Package Code H8 3008 ROMless 5 V HD6413008F HD6413008F 100 pin QFP FP 100B HD6413008TE HD6413008TE 100 pin TQFP TFP 100B HD6413008FP HD6413008FP 100 pin QFP FP 100A 3 V HD6413008VF HD6413008VF 100 pin QFP FP 100B HD6413008VTE HD6413008VTE 100 pin TQFP TFP 100B HD6413008VFP HD6413008VFP 100 pin QFP FP 100A ...

Page 635: ... the FP 100A package dimensions Hitachi Code JEDEC EIAJ Weight reference value FP 100B Conforms 1 2 g Unit mm Dimension including the plating thickness Base material dimension 0 10 16 0 0 3 1 0 0 5 0 2 16 0 0 3 3 05 Max 75 51 50 26 1 25 76 100 14 0 8 0 5 0 08 M 0 22 0 05 2 70 0 17 0 05 0 12 0 13 0 12 1 0 0 20 0 04 0 15 0 04 Figure G 1 Package Dimensions FP 100B ...

Page 636: ...rms 0 5 g Unit mm Dimension including the plating thickness Base material dimension 16 0 0 2 14 0 08 0 10 0 5 0 1 16 0 0 2 0 5 0 10 0 10 1 20 Max 0 17 0 05 0 8 75 51 1 25 76 100 26 50 M 0 22 0 05 1 0 1 00 1 0 0 20 0 04 0 15 0 04 Figure G 2 Package Dimensions TFP 100B ...

Page 637: ...t mm Dimension including the plating thickness Base material dimension 0 13 M 0 10 0 32 0 08 0 17 0 05 3 10 Max 1 2 0 2 24 8 0 4 20 80 51 50 31 30 1 100 81 18 8 0 4 14 0 15 0 65 2 70 2 4 0 20 0 10 0 20 0 58 0 83 0 30 0 06 0 15 0 04 Figure G 3 Package Dimensions FP 100A ...

Page 638: ...2 Series 30 36 27 3 Bus controller Burst ROM interface Yes H8 3067 No H8 3062 Series No Yes No Idle cycle insertion function Yes No Yes Yes Wait mode 2 modes 4 modes 2 modes 2 modes Wait state number setting Per area Common to all areas Per area Per area Address output method Choice of address update mode fixed in H8 3067F ZTAT and H8 3062F ZTAT Fixed Fixed Choice of address update mode 4 DRAM int...

Page 639: ...ernal clock φ φ 2 φ 4 φ 8 φ 8 φ 64 φ 8192 φ φ 2 φ 4 φ 8 φ φ 2 φ 4 φ 8 φ 8 φ 64 φ 8192 φ φ 2 φ 4 φ 8 φ 8 φ 64 φ 8192 Comple mentary PWM function No No Yes No No No No Reset synchronous PWM function No No Yes No No No No Buffer operation No No Yes No No No No Output initialization function Yes No No Yes No Yes No PWM output 3 4 2 5 3 4 2 3 4 2 DMAC activation 3 channels H8 3067 only No 4 channels 3 ...

Page 640: ... Pin control φ pin φ input port multiplexing φ output only φ input port multiplexing φ output input port A20 in 16 MB ROM enabled expanded mode A20 I O port multiplexing A20 output Address bus AS RD HWR LWR CS7 CS0 RFSH in software standby state High level output high impedance selectable RFSH H8 3067 only High level output except CS0 Low level output CS0 High level output high impedance selectabl...

Page 641: ...B5 TP13 LCAS SCK2 PB5 TP13 PB5 TP13 TOCXB4 PB5 TP13 TOCXB4 PB5 TP13 LCAS SCK2 PB5 TP13 8 PB6 TP14 TxD2 PB6 TP14 PB6 TP14 DREQ0 CS7 PB6 TP14 DREQ0 PB6 TP14 TxD2 PB6 TP14 9 PB7 TP15 RxD2 PB7 TP15 PB7 TP15 DREQ1 ADTRG PB7 TP15 DREQ1 ADTRG PB7 TP15 RxD2 PB7 TP15 10 RESO FWE 1 RESO FWE 1 RESO VPP RESO RESO NC RESO 11 Vss Vss Vss Vss Vss Vss 12 P90 TxD0 P90 TxD0 P90 TxD0 P90 TxD0 P90 TxD0 P90 TxD0 13 P9...

Page 642: ...1 A1 A1 A1 38 P12 A2 P12 A2 P12 A2 P12 A2 A2 A2 39 P13 A3 P13 A3 P13 A3 P13 A3 A3 A3 40 P14 A4 P14 A4 P14 A4 P14 A4 A4 A4 41 P15 A5 P15 A5 P15 A5 P15 A5 A5 A5 42 P16 A6 P16 A6 P16 A6 P16 A6 A6 A6 43 P17 A7 P17 A7 P17 A7 P17 A7 A7 A7 44 Vss Vss Vss Vss Vss Vss 45 P20 A8 P20 A8 P20 A8 P20 A8 A8 A8 46 P21 A9 P21 A9 P21 A9 P21 A9 A9 A9 47 P22 A10 P22 A10 P22 A10 P22 A10 A10 A10 48 P23 A11 P23 A11 P23 ...

Page 643: ...c AVcc AVcc 77 VREF VREF VREF VREF VREF VREF 78 P70 AN0 P70 AN0 P70 AN0 P70 AN0 P70 AN0 P70 AN0 79 P71 AN1 P71 AN1 P71 AN1 P71 AN1 P71 AN1 P71 AN1 80 P72 AN2 P72 AN2 P72 AN2 P72 AN2 P72 AN2 P72 AN2 81 P73 AN3 P73 AN3 P73 AN3 P73 AN3 P73 AN3 P73 AN3 82 P74 AN4 P74 AN4 P74 AN4 P74 AN4 P74 AN4 P74 AN4 83 P75 AN5 P75 AN5 P75 AN5 P75 AN5 P75 AN5 P75 AN5 84 P76 AN6 DA0 P76 AN6 DA0 P76 AN6 DA0 P76 AN6 DA...

Page 644: ...CLKD PA3 TP3 TIOCB0 TCLKD PA3 TP3 TIOCB0 TCLKD 97 PA4 TP4 TIOCA1 A23 PA4 TP4 TIOCA1 A23 PA4 TP4 TIOCA1 CS6 A23 PA4 TP4 TIOCA1 A23 PA4 TP4 TIOCA1 A23 PA4 TP4 TIOCA1 A23 98 PA5 TP5 TIOCB1 A22 PA5 TP5 TIOCB1 A22 PA5 TP5 TIOCB1 CS5 A22 PA5 TP5 TIOCB1 A22 PA5 TP5 TIOCB1 A22 PA5 TP5 TIOCB1 A22 99 PA6 TP6 TIOCA2 A21 PA6 TP6 TIOCA2 A21 PA6 TP6 TIOCA2 CS4 A21 PA6 TP6 TIOCA2 A21 PA6 TP6 TIOCA2 A21 PA6 TP6 T...

Page 645: ...September 2000 Published by Electronic Devices Sales Marketing Group Semiconductor Integrated Circuits Hitachi Ltd Edited by Technical Documentation Group Hitachi Kodaira Semiconductor Co Ltd Copyright Hitachi Ltd 2000 All rights reserved Printed in Japan ...

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