Hitachi H8/3008, Hardware Manual

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14.1.4 Register Configuration
Table 14.2 summarizes the A/D converter’s registers.
Table 14.2 A/D Converter Registers
Address*
1
Name Abbreviation R/W Initial Value
H'FFFE0 A/D data register A H ADDRAH R H'00
H'FFFE1 A/D data register A L ADDRAL R H'00
H'FFFE2 A/D data register B H ADDRBH R H'00
H'FFFE3 A/D data register B L ADDRBL R H'00
H'FFFE4 A/D data register C H ADDRCH R H'00
H'FFFE5 A/D data register C L ADDRCL R H'00
H'FFFE6 A/D data register D H ADDRDH R H'00
H'FFFE7 A/D data register D L ADDRDL R H'00
H'FFFE8 A/D control/status register ADCSR R/(W)*
2
H'00
H'FFFE9 A/D control register ADCR R/W H'7E
Notes: 1. Lower 20 bits of the address in advanced mode.
2. Only 0 can be written in bit 7, to clear the flag.
14.2 Register Descriptions
14.2.1 A/D Data Registers A to D (ADDRA to ADDRD)
Bit
ADDRn
Initial value
14
AD8
0
R
12
AD6
0
R
10
AD4
0
R
8
AD2
0
R
6
AD0
0
R
0
—
0
R
4
—
0
R
2
—
0
R
15
AD9
0
R
13
AD7
0
R
11
AD5
0
R
9
AD3
0
R
7
AD1
0
R
1
—
0
R
5
—
0
R
3
—
0
R
A/D conversion data
10-bit data giving an
A/D conversion result Reserved bits
Read/Write
(n = A to D)
The four A/D data registers (ADDRA to ADDRD) are 16-bit read-only registers that store the
results of A/D conversion.
An A/D conversion produces 10-bit data, which is transferred for storage into the A/D data
register corresponding to the selected channel. The upper 8 bits of the result are stored in the upper
byte of the A/D data register. The lower 2 bits are stored in the lower byte. Bits 5 to 0 of an A/D