Hitachi H8/3008, Hardware Manual

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In byte access, whether the upper or lower data bus is used is determined by whether the address is
even or odd. The upper data bus is used for an even address, and the lower data bus for an odd
address.
D
15
D
8
D
7
D
0
Upper data bus Lower data bus
1st bus cycle
2nd bus cycle
Byte size
Longword size
· Even address
· Odd address
Word size
Byte size
Figure 6.8 Access Sizes and Data Alignment Control (16-Bit Access Area)
6.4.3 Valid Strobes
Table 6.4 shows the data buses used, and the valid strobes, for the access spaces.
In a read, the
RD
signal is valid for both the upper and the lower half of the data bus.
In a write, the
HWR
signal is valid for the upper half of the data bus, and the
LWR
signal for the
lower half.
Table 6.4 Data Buses Used and Valid Strobes
Area
Access
Size Read/
Write
Address
Valid
Strobe Upper Data Bus
(D
15
to D
8
)
Lower Data Bus
(D
7
to D
0
)
8-bit access Byte Read —
RD
Valid Invalid
area
Write —
HWR
Undetermined data
16-bit access Byte Read Even
RD
Valid Invalid
area
Odd Invalid Valid
Write Even
HWR
Valid Undetermined data
Odd
LWR
Undetermined data Valid
Word Read —
RD
Valid Valid
Write —
HWR
,
LWR
Valid Valid
Notes: 1. Undetermined data means that unpredictable data is output.
2. Invalid means that the bus is in the input state and the input is ignored.