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16-Bit, Two-State-Access Areas: Figures 6.14 to 6.16 show the timing of bus control signals for
a 16-bit, two-state-access area. In these areas, the upper data bus (D
15
to D
8
) is used in accesses to
even addresses and the lower data bus (D
7
to D
0
) in accesses to odd addresses. Wait states cannot
be inserted.
Bus cycle
Even external address in area n
Valid
Invalid
Valid
High
φ
Address bus
CS
n
AS
RD
D
15
to D
8
D
7
to D
0
HWR
LWR
D
15
to D
8
D
7
to D
0
Read access
Write access
Note: n = 7 to 0
T
1
T
2
Undetermined data
Figure 6.14 Bus Control Signal Timing for 16-Bit, Two-State-Access Area (1)
(Byte Access to Even Address)
Summary of Contents for H8/3008
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