Hitachi CP2896TA, Service Manual

Page: 26 / 112

15
Teletext
Megatext SDA5273, ICr1
The SDA5273 Megatext circuit is a single chip which com-
bines data slicer, teletext processor, page / pixel memory,
and display controller. Digital signal processing is used to
eliminate external discrete components.
The memory can be extended using an external DRAM to
increase the teletext capacity.
The multistandard capability of the Megatext circuit en-
sures its suitability for all countries which transmit the
World System Teletext (WST) level 1.5.
The Megatext circuit functions are the decoding and dis-
play of teletext information from an analog source, CVBS
input, and the generation of On Screen Displays, which
can provide the TV user with status information or assist-
ance. The RGB output of the Megatext IC is connected to
the RGB input of the RGB video processor together with
fast blanking information.
The Megatext IC is controlled through the M3L-bus which
has a maximum data rate of 1 Mbit/s.
Circuit description
The CVBS signal from the video matrix switch is fed to
input pin 9.
The basic principles of the signal handling are shown in
the block diagram below.
The analog RGB signals and fast blanking signal are out-
put on pins 44 (R), 45 (G), 46 (B) and 47 (FB). The vertical
sync pulse (2V) is fed to pin 3 and the horizontal sync pulse
(2H) to pin 4. Sync pulses are taken from the Feature box
(VDFL and HDFL).
An external 20.48 MHz crystal is connected between pins 5
and 6. Pins 18...35 and 37 are the address and data lines
for the external DRAM (icr2). The +5 Vr supply voltage is
fed to pins 10, 11, 13, 15 and 17. A high level on pin 14
causes the chip to be reset.
A stabilized 3.3 V reference voltage for internal use, from
the zener diode Zdr1, is connected to pin 16.
The Megatext circuit communicates with the
microcontroller via the M3L-bus, using pins 49 (SCL), 50
(SDA) and 51 (IICENable).
A/D Converter converts the CVBS signal to 7-
bit binary code.
Sync Slicer and Timing separates the hor/vert sync
from the digitized CVBS signal
and generates a line-locked 24
MHz acq clock.
20.5 MHz
Crystal to external
DRAM 2V
M3L-Bus RGB
CVBS
DAC
FIFO
CLUT
SDA 5273
24-KByte DRAM
External DRAM-Interface
2H
Bus
Interface
Data
Slicer
Acq
Interface
A/D
Converter
PU
Character
ROM
Display
Generator
Sync
Slicer &
Timing
Crystal
Oscillator
Display
Clock &
Timing
Data Slicer separates the teletext data from
the digitized CVBS signal.
Acquisition Interface synchronizes the bytes, con-
verts serial bits to the parallel
bytes and detects the framing
code.
Processing Unit manages the interchange func-
tions between acquisition,
memory, display, and bus inter-
face.
Internal Memory Internal 24 Kbyte DRAM.
Ext DRAM Interface Interface between the megatext
and external DRAM.
Display Generator controls data transfer from
IRAM to DG, decodes the dis-
play words, controls the display
formats and generates special
cursors.
Character ROM Character pixel memory.
CLUT Colour look up tables.
Display clock and Timing generates the horizontal timing
signals for the display and a line
locked display clock.
FIFO speeds up the pixel rate from
normally 24 MHz to 32 MHz in
16:9 mode.
D/A converter produces analog RGB signals.
Bus Interface M3L-bus interface between the
Megatext and microcontroller.
Megatext Plus SDA5275, ICr1
The Megatext Plus circuit SDA5275 is based on the origi-
nal Megatext circuit SDA5273. The main difference is in
the internal data processing, which enables the teletext data
processing in accordance with the level 2.5. The level 2.5
generates much better graphics (bitmap graphics), more
colours (4096) and an extension for the 16:9 format, which
enables a wider display page. Consequently, the level 2.5
can display 56 characters on each 25 lines (1400 charac-
ters / page). The level 1.5 can display only 40 characters
per line (1000 characters / page).
Because of higher level pages, the Megatext Plus circuit
always requires an external memory circuit.
Teletext memory DRAM, icr2
The external teletext memory is a 4 Mbit high-speed Dy-
namic Random Access Memory (DRAM). It is organized as
1 048 576 four-bit words (4 194 304 bit). The circuit uses
CMOS silicon gate technology.
One teletext page takes 1 Kbyte (8 192 bit) of memory, so
the circuit is able in theory to store 512 teletext pages (4
194 304 : 8 192 = 512). This reduces the page access time
to virtually zero.
During the first cycle of the teletext transmission, the
memory circuit is formatted for the transmitted pages.
During the second cycle, transmitted pages are stored in
the memory.