Hitachi CP2896TA, Service Manual

Page: 21 / 112

11
The horizontal (HDFL) and vertical (VDFL) sync signals from
the DPLL1 are fed to input pins 13 and 12 to synchronize
the circuit.
The horizontal flyback pulse is taken from the horizontal
output stage to input pin 1.
Horizontal drive signal
From the horizontal detector stage, the horizontal sync sig-
nal is fed to the horizontal counter, the horizontal place
control, the phase 2 loop, and finally output from pin 20 to
drive the horizontal driver stage. The H-phase adjustment
is performed in the horizontal position control stage using
the IIC-bus.
Vertical drive signal
From the vertical detector stage, the vertical sync signal is
fed to the vertical place control, the vertical place genera-
tor, the vertical geometry stage and finally the differential
current vertical drive signals are output from pins 10 and
11 to drive the vertical deflection circuit ICs1. Vertical am-
plitude, S-correction and V-shift are controlled in the verti-
cal geometry stage via the IIC-bus. The reference current
for both the vertical and E-W geometry processing is de-
termined by resistor r68 on pin 8.
E-W drive signal
The E-W drive signal is a single ended current output and
it is taken out from pin 6. The control parameters: E-W
width, E-W parabola/width ratio, E-W corner/parabola, and
E-W trapezium are included in the E-W geometry process-
ing stage. All of these controls can be set using the IIC-
bus.
EHT compensation
Both the vertical and the E-W drive outputs are modulated
for EHT compensation via pin 7. The EHT information is
taken from DST pin 8 (“static” information) and from Ck31
/ Rk58 and Ch21 / Rh29 (dynamic information).
Sandcastle
The TDA9151 generates a two level display sandcastle pulse
(DSC). The 2.5 V level is used for horizontal and vertical
blanking, and the 4.5 V level for video clamping. The DSC
is output from pin 2 and it is used for the timing of the RGB
Video processor ICt1.
In addition, pin 2 operates as an input pin for the vertical
guard. The DSC pulse is connected to pin 1 of the vertical
deflection circuit. In possible fault cases, the vertical IC will
supply a voltage level of 2.5 V, which causes blanking of
the screen.
DPLL1 circuit, ic11
The DPLL (Digital Phase Locked Loop) circuit generates all
line locked clock and sync signals for the whole digital sig-
nal processing system. The circuit is IIC-bus controlled and
it needs only a few external components, one of them a 27
MHz crystal. The 27 MHz clock operates as a main clock,
from which the other clock frequencies are generated us-
ing suitable factors.
Pin description of ic11:
Pin Symbol Description
1 HSYNC1 Horizontal sync from sync
processor
5 VSYNC1 Vertical sync from sync
processor
7 HOUT1 Horizontal sync for ADC and
IQTV2
9 CLK27_1 27 MHz main clock for FM1
and IQTV1
11 CLK13_5_1 13.5 MHz clock for ADC
13 VOUT1 Vertical sync for IQTV2
22 CLK27_2 27 MHz main clock for
deflection controller
24 HS_GSCART Horizontal sync from VGA
(DB700)
26 HSYNC2 Horizontal sync from VGA
(DB700)
27 VS_GSCART Vertical sync from VGA
(DB700)
28 CLK Format dependant clock for
FM1/2 and IQTV2
29 VSYNC2 Double frequency vert sync
from IQTV2
30 HOUT2 (HDFL) Hor sync for IQTV2 and
deflection controller
31 VOUT2 (VDFL) Vert sync for IQTV2 and
deflection controller
33 FORMAT_VGA Low by DB711/710, high by
DB700
35, 36 XTALCLK 27 MHz crystal (for main
clock)
37 FORMAT_MEM High by DB711, low by
DB700/710
40, 41 SDA / SCL IIC-bus, serial data and clock
42 ADC_OVFL Overflow data from ADC
43 PWM_REF Output of width modulated
pulses for ADC
Deflection Controller TDA9151, IC17
The TDA9151 circuit is an IIC-bus controlled synchroniza-
tion and deflection processor having horizontal and verti-
cal drive outputs and an East-West correction drive circuit.
Input signals
The serial data (SDA) and serial clock (SCL) are connected
to pins 17 and 18.
The 27 MHz line locked clock pulse (CLK27_2) from the
DPLL1 is fed to pin 14. The internal synchronous logic uses
the LLC as a system clock. It is important to realise that the
circuit will not operate without the LLC, it will switch off
the outputs and will not perform any operations. The LLC
frequency is divided by two by connecting the line-locked
clock select input pin 5 (LLCS) to ground. This activates
the prescaler stage and creates a line duration of 32
µ
s.