Hitachi CP2896TA, Service Manual

Page: 19 / 112

9
Functional description
The colour difference signals are fed to input pins 14 (U)
and 16 (V). First the signals are clamped, and then they are
fed through pre-amplifiers to the undelayed / delayed sig-
nal paths. All the switching signals needed in the delay
process are generated from the 3 MHz master clock fre-
quency. This frequency is divided from the internal 6 MHz
VCO, which is line-locked by the sandcastle pulse (SC). The
SC pulse taken from the sync processor is fed to pin 5.
Delay processed colour difference signals are fed through
the addition circuits to the output buffers and are finally
output on pins 12 (U) and 11 (V).
Feature boxes, DB7**
The feature box has two main functions, to perform the
conversion of the 50 (60) Hz scan to 100 (120) Hz scan for-
mat and to improve the picture quality. Depending on the
chassis version, there are few different feature boxes with
more or less variant features. The whole signal processing
takes place digitally and all functions are controlled using
the IIC-bus.
The basic version is DB711, that contains only one 3 Mb
field memory. The use of one field memory allows the con-
version of 50 (60) Hz video to 100 (120) Hz video, but not
line flicker and noise reduction or vertical zooms. This
module is designed for TV sets with a 4:3 picture aspect
ratio.
The DB710 version contains two 3 Mb field memories, so
noise reduction and vertical zooms are also implemented.
The DB710 (and DB700) are designed for TV sets with both
a 4:3 and 16:9 picture aspect ratio.
The DB700 version is called a “full feature” version, that
includes in addition to the features of DB710, a signal in-
terface in accordance with the VGA standard.
Feature DB711 DB710
100 Hz flicker reduction - field repetition - median interpolation
Line flicker reduction - no - median filter
Noise reduction (Y / C) - no - motion adapted
Aspect ratio conversions
- horizontally -
±
12.5 and
±
25 % -
±
12.5 and
±
25 %
- vertically - by deflection - +12.5 and +25 % (by DSP)
- hor picture position - fully programmable - fully programmable
- lift - no - yes
- side panels - programmable grey - programmable grey
Picture sharpening - vertical / horizontal peaking - vertical / horizontal peaking
- CTI, LTI - CTI, LTI
Histogram equalizing - yes - yes
Still picture - yes - yes
A/D conversion - YUV 4:1:1 signal format - YUV 4:1:1 signal format
- 8-bit per component - 8-bit per component
- input signal amplitude adapted - input signal amplitude adapted
- sampling rate - 13.5 MHz - 13.5 MHz
D/A conversion - Y-component 9-bit - Y-component 9-bit
- U- and V-component 8-bit - U- and V-component 8-bit
- sampling rate - 20.25 MHz ... 36 MHz - 20.25 MHz ... 36 MHz
Field memory - 3 Mbit (1 x 3 Mbit) - 6 Mbit (2 x 3 Mbit)
Synchronizing - line locked operation - line locked operation
- crystal based sync generation - crystal based sync generation
Feature box DB711
The main components of the DB711 are an A/D converter,
field memory (FM), picture quality improvement circuit
(IQTV2), digital phase locked loop (DPLL) and deflection
controller.
Y, U and V inputs
The luminance (Y) and colour difference signals (U and V)
are taken from the colour decoder to the module connec-
tor Q101, pins 6 (Y), 7 (U) and 8 (V). Each signal is first
amplified and then low pass filtered. After that the signals
are fed via buffer transistors to the A/D-converter, pins 63
(Y), 50 (U) and 31 (V).
Analog to digital converter, ic9
Analog to digital conversion is carried out using A/D-con-
verter circuit TLC5733, which contains three separate 8-bit
A/D-converters. Each signal is clamped using the horizon-
tal sync pulse (HOUT1) on pin 55 and then converted to
digital form. The converters sample the input signals at a
13.5 MHz sampling rate. The sampling frequency is taken
to pin 56. The converters are controlled by reference
voltages REFH (pins 61, 52 and 29) and REFL (pins 1, 48
and 33).
If an overflow is detected, the reference voltages will be
either increased or decreased. Information about a possi-
ble overflow is taken from the luminance output data (pins
6...13) and fed to the NAND gate ic28 and onward to the
DPLL circuit ic11 pin 42 (ADC_OVFL). The circuit detects
the overflow data and if necessary, it changes the width of
the pulses on pin 43 (PWM_REF). These width modulated
pulses are fed to the low pass filter consisting of transis-
tors t1 and t9 and associated capacitor network. The low
pass filter generates both voltages, the REFH and REFL,
and these are fed to control the A/D-converters.
After converters the signals are fed to the output format
multiplexer, which is controlled by pins 45 (mode1) and 46
(mode0). The combination of a logical low on both pins
causes the output data format of the YUV signals to be
4:1:1. The U and V components have 1/4 of the signal
strength of the Y component.
The luminance data bus (pins 6...13) is eight bits wide and
the chrominance data bus (pins 17...20) four bits wide.