Publication No. SBC330-0HH/3
FPGA Registers 59
6.9.3 PCIe Spread Spectrum clocking control
PCIe
has
the
ability
to
work
with
Spread
‐
Spectrum
clocks,
which
reduce
EMI
emissions.
The
ICS9FG108
clock
device
has
a
pin
to
control
whether
it
generates
a
spread
‐
spectrum
clock
from
a
fixed
frequency
reference
oscillator.
This
is
disabled
by
default.
On
the
SBC330,
the
FPGA
has
the
ability
to
run
the
PCIe
clocks
in
spread
spectrum
mode
by
turning
the
feature
on.
By
default
SPREAD_CLK_EN
is
inactive
(low)
at
power
‐
up.
6.9.4 PEX SROM write protection
The
backplane
NVMRO
signal
overrides
register
bit
4,
so
the
following
table
shows
the
circumstances
under
which
the
SROMs
attached
to
the
PEX8518
PCIe
Switch
and
PEX8114
PCIE/PCI
Bridge
can
be
written
to:
At
power
up,
the
register
bit
is
set
high
to
disable
writing
to
the
PEX8114
and
PEX8518
SROMS.
This
reduces
the
chance
that
a
customer
can
easily
corrupt
the
contents
of
the
SROM.
6.9.5 PEX SROMs presence detect
By
default,
the
BSP
contains
all
the
set
‐
up
information
for
the
PEX8518
and
PEX8114.
However,
the
PEX
devices
may
optionally
load
their
set
up
from
SROMs
either
during
development
or
by
customer
configuration.
If
this
is
required,
bits
10
and
9
must
be
set
so
that
the
appropriate
SROM
is
seen
as
present
by
the
corresponding
PEX
device.
At
power
‐
up,
both
bits
are
set
to
‘1’
(disable
SROMs).
At
reset,
both
bits
are
sticky
to
the
last
value
written
6.10 Backplane Registers
The
VPX
specification
includes
several
‘System’
signals
that
are
either
bused
along
the
backplane
or
assigned
in
a
particular
way
for
a
given
slot.
Slot
1
is
the
‘System
Controller’
slot,
and
the
SBC330
has
the
ability
to
be
a
System
Controller.
In
VPX,
the
main
functions
of
the
System
Controller
are
to
provide
the
SYSRESET#
signal
and
the
NMVRO
signal.
The
SBC330
has
a
Status
register
(read
only)
and
a
Command
register
(read/write)
in
the
FPGA
for
backplane
functions.
The
SBC330
detects
whether
it
is
the
System
Controller
by
reading
the
SYSCON#
signal,
which
is
low
‘0’
for
the
System
Controller
slot
(slot
1)
only.
If
bit
2
of
the
Status
register
is
low,
indicating
the
board
is
System
Controller,
then
the
Command
register
can
be
used
to
toggle
the
SYSRESET#
and
NVMRO
lines.
Otherwise,
writes
to
the
Command
register
are
ignored.
NOTE
The Status and Command registers reflect true signal values – there is no inversion
.
Bit 4
NVMRO
PEX SROMS
0
0
Writable
0
1
Protected
1
0
Protected
1
1
Protected
