GE SBC330 3U VPX Hardware Reference Manual Download Page 28

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28 SBC330 3U VPX Single Board Computer

Publication No. SBC330-0HH/3

data

bus.

The

Flash

each

device

arranged

256

KByte

sectors,

has

erase

capacity

100,000

cycles

per

sector

and

typical

data

retention

years.

NOTE

Integrity of Flash data cannot be guaranteed if a hard reset occurs during a Flash write cycle.

The

following

table

shows

the

Flash

options

available

for

the

SBC330:

The

Flash

divided

into

two

contiguous

area

types:

Boot

Flash

and

User

Flash.

least

the

top

MBytes

Flash

reserved

for

Boot

Code

(16

MBytes

the

Core

Boot

bit

set

the

FPGA

Flash

Control

The

boot

code

region

separated

into

four

MByte

boot

regions

that

may

selected

using

hardware

links.

The

remainder

the

Flash

memory

allocated

User

Flash.

5.3.4 Boot Flash

MBytes

each

the

Flash

memory

options

taken

Boot

Flash,

and

used

hold

initialization

and

operating

system

boot

routines.

Each

the

two

MByte

regions

can

used

hold

boot

images

each

for

processing

cores

and

However,

normal

that

both

processing

cores

access

the

same

BootROM.

this

case,

only

the

top

MBytes

used;

core

boots

from

the

same

BootROM

core

and

the

rest

Flash

mapped

User

Flash.

Figure 5-2 Local Bus CS0 Mapping

Table 5-4 Flash Options

Flash Size (MBytes)

Banks

Flash Bank Organization

256

2 x 1024 Mbit

512 (when available)

2 x 2048 Mbit (when available)

Not

scale

CS0

Normal

four

MByte

Boot

areas

Flash

Control

‘Core

Boot’

bit

set

0xFFA0

0000

0xFF80

0000

0xFF60

0000

0xFF40

0000

0xFF20

0000

0xFF00

0000

0xFFC0

0000

0xFFE0

0000

0xFFFC

0000

0xFFFF

FFFF

Core

BANC

Spare

Core

0/1

Extended

Core

0/1

Alternate

Core

0/1

Main

Core

BANC

Spare

Core

Extended

Core

Alternate

Core

Main

Spare

Core

Extended

Core

Alternate

Core

Main

User

Flash

User

Flash

Errata
May

2011

Summary of Contents for SBC330 3U VPX

Page 1: ...Hardware Reference Manual SBC330 3U VPX Single Board Computer Edition 3 Publication No SBC330 0HH 3 GE Intelligent Platforms ...

Page 2: ...sed in accordance with the requirements of the WEEE Directive GE Intelligent Platforms Limited will evaluate requests to take back products purchased by our customers before August 13 2005 on a case by case basis A WEEE management fee may apply Edition Date Description 1 September 2008 Board Rev3 Firmware Release 3 2 August 2009 Firmware Release 4 addition of a separate TAS semaphore FPGA register...

Page 3: ...n and Inspection 14 2 1 Product Identification 14 2 2 Inspection 14 3 Installation and Power Up 15 3 1 Installation 15 3 2 Cooling 16 3 3 Power up 16 3 3 1 Checklist 16 3 3 2 Power up 16 3 4 Connecting to SBC330 16 3 5 Power Up Sequence 17 3 5 1 On board sequencing 17 3 5 2 Inter board sequencing 17 4 Configuration 19 4 1 Jumper Locations 19 4 2 Default Link Settings 19 4 3 P10 Header 20 4 3 1 Fla...

Page 4: ...PCI Express switch 32 5 4 3 PCI Express to PCI bridge 34 5 4 4 PCI Bus 34 5 5 Local Bus 34 5 6 Local Bus Control FPGA 35 5 6 1 Ethernet 35 5 6 2 Serial ports 35 5 6 3 USB 36 5 6 4 Serial ATA 37 5 6 5 General Purpose I O 37 5 7 I2C 38 5 7 1 I2C addressing 38 5 7 2 Real Time Clock 39 5 7 3 Elapsed Time Indicator 39 5 7 4 Temperature sensors 39 5 7 5 Power Supply manager 39 5 7 6 MPC8641D configurati...

Page 5: ...register 54 6 5 4 GPIO output register 54 6 6 Geographic Address Register 55 6 7 Platform Multiplier Register 56 6 8 Core Multiplier Register 57 6 9 Miscellaneous Functions Register 58 6 9 1 AMP SMP mode 58 6 9 2 PEX8518 mode 58 6 9 3 PCIe Spread Spectrum clocking control 59 6 9 4 PEX SROM write protection 59 6 9 5 PEX SROMs presence detect 59 6 10 Backplane Registers 59 6 10 1 Backplane status re...

Page 6: ...73 7 4 Power Status LEDs Blue 74 7 5 PCI Express Link Status LEDs Orange 74 7 6 SATA Activity LED Yellow 74 7 7 PCIe Fatal Error LED Red 74 8 Software 75 8 1 Operating Systems 75 8 2 BIT 75 8 3 Boot Firmware 75 8 4 Background Condition Screening 76 9 Connectors and Cables 77 9 1 VPX Connectors 77 9 2 Connector Pinout 78 9 2 1 P0 connector pinout 78 9 2 2 J0 backplane connector pinout 78 9 2 3 P0 s...

Page 7: ...87 A 2 4 GPIO electrical characteristics 87 A 3 Reliability MTBF 87 A 4 Build Levels 88 A 4 1 Convection cooled boards 88 A 4 2 Conduction cooled boards 88 A 5 Mechanical Specifications 89 A 5 1 Weight 89 A 5 2 Dimensions 89 A 6 Product Code Information 90 Index 91 ...

Page 8: ...f Flash memory two Gigabit Ethernet channels on board serial communications RS232 four USB2 ports two SATA 2 0 ports and two independent PCI Express links routed to the VPX backplane a direct 8 lane port for extreme graphics applications and a 4 lane port routed via an on board PCIe switch The MPC8641D is connected to all on board PCI devices using PCI Express This is a high speed serial interconn...

Page 9: ... Silicon Image si3132 SATA IC http www siliconimage com products product aspx id 32 The USB Standard http www usb org developers docs NEC 4 port USB Controller http www necel com usb en document index html upd720101 Dual core MPC8641D processor at up to 1 5 GHz each core with 1 MByte cache Expandable 2 x ECC DDR2 SODIMMS each offering 2 GByte 533 MHz 256 MByte password or hardware protected 32 bit...

Page 10: ...OTE Note text in here Cautions call attention to actions that may cause system damage or loss of data and are shown as follows CAUTION Caution text here Warnings call attention to actions that may cause risk of personal injury and are shown as follows WARNING Warning text here Recommendations give guidance on procedures that may be tackled in a number of ways and are shown as follows TIP Tip text ...

Page 11: ...al safety precautions during operation of this equipment Failure to comply with these precautions or with specific Warnings and or Cautions elsewhere in this manual violates safety standards of design manufacture and intended use of the equipment GE Intelligent Platforms Ltd assumes no liability for the user s failure to comply with these requirements The safety precautions listed below represent ...

Page 12: ... FCC regulations for EMC emissions and susceptibility Conduction cooled build levels of the SBC330 are designed for integration into EMC hardened cabinets boxes 1 6 Handling CAUTION Only handle the board at the edges heatsink or front panel 1 7 Heatsink CAUTION Do not remove the heatsink The heatsink is thermally bonded to the ICs and will generally not separate from the board by removal of the sc...

Page 13: ...for use in future correspondence Alternatively you may also contact GEIPʹs Technical Support via LINK support towcester ip ge com TELEPHONE 44 0 1327 322760 1 9 Returns If you need to return a product there is a Return Materials Authorization RMA request form that can be printed out and filled in available via the web site Repairs page LINK http defense ge ip com support embeddedsupport rmalocator...

Page 14: ...BC330 is not received in perfect physical condition report this to the Customer Services department immediately Identification labels similar to this attached to the shipping box and the antistatic bag provide identical information SBC330 product code product description equipment number and board revision On the board within the antistatic bag there is an identifying label similar to this attache...

Page 15: ...s electrically compatible with the pin listings in Chapter 9 Carry out all installation with the power and data cables fully disconnected NOTE Only plug SBC330 boards into compatible system backplane slots Air cooled versions of the SBC330 have an injector ejector handle to ensure that the backplane connectors mate properly with the backplane The best way to install a build level 1 to 3 SBC330 int...

Page 16: ... 5 V 50 W from VS3 VCC operating within the VPX Specification limits 5 V 5 2 5 The VPX P3V3_AUX voltage rail is required only for supplying the Real Time Clock in the absence of system power WARNING Do not exceed the maximum rated input voltages or apply reversed bias to the assembly If such conditions occur toxic fumes may be produced due to the destruction of components You can now power up the ...

Page 17: ... once the backplane voltage on VS3 is above 4 49 Volts If the Board Management Microcontroller BMM asserts the BMM_OFF signal the power manager will shut down all on board supplies except VCC and P3V3_AUX The power manager is connected to the on board I2 C Bus 2 allowing software read out of the voltages of all on and off board supplies 3 5 2 Inter board sequencing The SBC330 supports inter board ...

Page 18: ...T low Wait for VS3 to reach 4 49Volts 90th percentile triggering Wait for PSU_SEQ_IN signal to be high or for 500ms Release PSU_SEQ_OUT Following the PSU_SEQ_OUT signal which occurs once all the on board PSUs have active POWER_GOOD signals if the board is the slot 1 VPX controller then the backplane SYS_RESET signal is driven low for a further 20 mS ...

Page 19: ... 2 way jumpers that affect booting and need to be set correctly 4 2 Default Link Settings The SBC330 is shipped from the factory with some links fitted This simplifies the most likely use of the SBC330 Some jumpers are essential and some are not Before changing any of the link options refer to the following sections NOTE If you are about to install your board and power up for the first time leavin...

Page 20: ...re 0 boot sites 4 3 3 Boot Flash image selection The Boot Flash for processing core 0 is divided into four 2 MByte sections named Main Alternate Extended and BANC Boot Area Non Corruptible These allow for three different boot images to be loaded from the Flash plus when available a factory programmed boot image that allows the user to recover if a non bootable image is erroneously put into Flash T...

Page 21: ...amming of the FPGA CPLD which is the most likely JTAG operation to be performed by a user However it is important that a user sets the AMP SMP jumper correctly for their intended operation AMP mode is the favored operational mode which requires P12 pins 1 and 2 to be linked Table 4 2 Flash Jumper operation Link Configuration Pins 5 and 6 Not fitted Fitted Not fitted Fitted Pins 7 and 8 Not fitted ...

Page 22: ...e 4 3 JTAG Jumpers on Header P12 P12 Pins Function Action when fitted Pin 1 pin 2 1 Isolate ispPAC device from JTAG 2 Select AMP SMP mode PWR MAN isolated AMP mode selected Pin 3 pin 4 Processor JTAG chain or Emulator Processor in chain Pin 5 pin 6 Binary combination with pins 7 8 See next table Pin 7 pin 8 Binary combination with pins 5 6 See next table Table 4 4 JTAG Multiplex Jumpers on P12 Hea...

Page 23: ...of Flash memory with enhanced write protection features PCI Express board interconnect with non blocking switch architecture Two 10 100 1000BaseT Ethernet ports Two Serial I O channels RS232 both with hardware flow control Four USB 2 0 ports 480 Mbits second Two Serial ATA disk interfaces up to 3 0 Gbits second Up to 8 bits of General Purpose digital I O with interrupt capability Real Time Clock E...

Page 24: ...ated Host Processor The SBC330 is based around the Freescale MPC8641D Integrated Host Processor This provides Dual e600 PowerPC processing cores Internal MPX bus Dual DDR2 Memory Controllers PCI Express Interface Gigabit Ethernet Interfaces Local Bus Interface I2 C Interfaces Serial I O Interfaces DMA Engines Interrupt Controller ...

Page 25: ...ptions Contact your nearest GE Intelligent Platforms Sales Office or Agent for more information 5 2 2 Dual Processing Core operation The MPC8641D contains two processing cores Following reset processing core 1 is prevented from accessing the MPX bus until it is enabled by core 0 The two processing cores can run two different operating systems or two separate instances of the same operating system ...

Page 26: ... reference but since the memory map is almost completely software configurable see the applicable software manual for more information Table 5 2 VxWorks Default Memory Map Internal 32 bit Core 0 Internal 32 bit Core 1 FFFF FFFF FFFF FFFF 8 MByte Boot Flash Core 1 boot Flash when defined in Firmware FF80 0000 FF80 0000 FF7F FFFF FF7F FFFF FF00 0000 FF00 0000 FEFF FFFF FEFF FFFF CCSR FEF0 0000 FEF0 ...

Page 27: ...h conformally coated SODIMMs to preserve the warranty GEIP will endeavor to assist customers who wish to change memory modules CAUTION Due to an erratum of the MC8641 rev 2 0 rev 2 1 processor there is a folding back of memory above 2 GBytes This precludes memory sizes above 2 GBytes It is possible to configure the DDR memory as 2 GBytes on 1 controller or 2x 1 GByte on both controllers 5 3 3 Flas...

Page 28: ... Boot Flash and is used to hold initialization and operating system boot routines Each of the two 8 MByte regions can be used to hold up to 4 boot images each for processing cores 0 and 1 However it is more normal that both processing cores access the same BootROM In this case only the top 8 MBytes is used core 1 boots from the same BootROM as core 0 and the rest of Flash is mapped as User Flash F...

Page 29: ...jumpers on SBC330 to make them completely independent 5 3 5 User Flash Any Flash that is not used as Boot Flash is designated as User Flash and is intended to hold user application code or data User Flash is accessed using Chip Select CS1 on the Local Bus Controller of the MPC8641D Chip Select 1 is intended for use by Processing Core 0 and may be used to access all areas of Flash as required when ...

Page 30: ...in the Flash The configuration of this protection is only possible when the Flash password Protection Unlock Link P10 pins 1 and 2 is fitted If this link is not fitted the software is unable to change the sector protection and those sectors that are locked may not be erased or reprogrammed under any circumstances Non persistent protection may also be used This protection is only present until a po...

Page 31: ...so perform end to end error checking to ensure integrity of the received data All 8 lanes of PCIe from port 2 are routed directly to the VPX connector This link supports very high bandwidth peripheral cards such as the GEIP GRA110 graphics processor All 8 lanes of PCIe from port 1 are routed to a PLX PEX8518 Switch device This routes 4 lanes externally and can be set up via an associated SPI EEPRO...

Page 32: ...PLX PEX8518 PCI Express switch to connect the various PCIe devices together This device is a 16 lane non blocking PCIe rev 1 1 switch that can support up to six PCIe ports The device also supports cut thru mode to reduce packet latency On the SBC330 the PLX8518 is set up to operate as 4 ports with port widths of x8 x4 x2 and x2 The switch connects to the processor over the x8 port for maximum band...

Page 33: ...be ascertained from registers within the Switch device The default Switch setting is for the external 4 lane port to be Transparent This allows the SBC330 to attach to PCIe End Point devices To connect together two intelligent devices on PCIE such as two SBC330 processor boards on one of the boards the PEX8518 Switch needs to be set as Non Transparent for the external port Port 1 To achieve this t...

Page 34: ...rocessor via in band PCIe Message Signaled Interrupts MSI or as legacy PCI INTx interrupt delivery 5 4 4 PCI Bus The 32 bit PCI bus on the SBC330 runs at 33 MHz and is connected between the PEX8114 Bridge and the NEC UPD720101 USB2 0 controller only The NEC device is on IDSEL line 19 the Bridge does not need an IDSEL in its forward mode 5 5 Local Bus The MPC8461D local bus is a 32 bit multiplexed ...

Page 35: ...equired Jumbo frames are also supported The SBC330 uses two of these controllers to provide external 1000 100 10 Ethernet interfaces eTSEC1 and eTSEC3 are used as these have independent connections to the platform bus The controllers are connected via a GMII interface to Marvell 88E1111 PHYs The PHYs are isolated from the backplane using transformer coupled magnetics The PHYs are configured at pow...

Page 36: ... between the terminal and the SBC330 can have the effect that it appears as board has not booted 5 6 3 USB An NEC μPD720101 device provides four USB ports on the SBC330 and is connected to the PCI bus The device is capable of operation at USB standard low full or high speed The device contains two OHCI controllers for USB1 1 operation and one EHCI controller for USB2 0 operation Alternate ports us...

Page 37: ...ended signals with 5V tolerance These signals are controlled by the Local Bus FPGA and can be configured as inputs with the ability to generate level or edge triggered interrupts or totem pole outputs that switch to CMOS levels The lines are protected via an in line IDT QuickSwitchTM FET device that limits any over voltages seen by the FPGA The in line FET modifies the switching characteristic of ...

Page 38: ...rite to I2 C devices the LSB is 0 to read from I2C devices the address is normally the write address 1 The following table shows the addresses used by the I2 C devices connected to the on board I2 C buses These are the byte addresses that would be used to write to read from the device on the bus i e the 7 bit device address and the least significant bit set to 0 or 1 as required Table 5 11 I2C Bus...

Page 39: ...rther can be used to switch off the power supplies to the board The current release of firmware has this feature implemented but disabled Future releases will allow users to enable or disable the feature 5 7 5 Power Supply manager The SBC330 uses a Lattice ispPAC POWR1014A to monitor and sequence the on board voltages The device provides an I2C interface that can be used to access an internal A to...

Page 40: ... 12 These are the Byte addresses that would be used to write to the device on the bus i e the 7 bit device address and the least significant bit set to 0 The local processor communicates with the BMM via the COM2 port from the MPC8641D The BMM serial interface is enabled when the BMM Communications Mode bit in the BMM Control register is set to 1 The BMM is programmed from the BMM Control register...

Page 41: ...n the operation of the watchdogs can be found in the Watchdog Registers section 5 9 AXIS Support The SBC330 provides hardware features required to support GEIP s AXIS software suite Four 32 bit wide FIFOs capable of holding 64 messages each are provided to support message passing between the two on board processing nodes or from other nodes in the system to the on board processing nodes An interru...

Page 42: ...MM is asserted Either of the two watchdog timers expire The front panel switch is activated build levels 1 to 3 only The duration of the internal hard reset signal is at least 10ms The processing cores may be individually reset by software using the Processor Core Reset Register within the MPC8641D interrupt controller 5 10 2 SYSRESET Signal The VPX SYSRESET signal is asserted by hardware when a h...

Page 43: ... On the SBC330 INT8 is used to receive interrupts from the secondary interrupt controller in the FPGA INT0 to INT7 are left free for PCIe interrupt messages This minimizes any latency of PCIe response and maximizes its bandwidth The MCP8641D interrupt controller supports routing of internal and external interrupt sources to one of the two processing cores including programmable priority levels All...

Page 44: ...ller and mezzanines and routes them directly to the interrupt controller via the Local Bus Control FPGA bypassing the fabric altogether 5 11 Power Management 5 11 1 Processor All power management features of the processing cores such as the programmable power states Doze Nap and Sleep Dynamic Power Management Instruction Cache Throttling and Dynamic Frequency switching are available to the softwar...

Page 45: ...sor but excluding the power manager NOTE P12 Jumper 1 2 is dual function it is also used in normal operation to distinguish between AMP and SMP processing Modes The default configuration has jumpers P12 1 2 7 8 linked which defaults the processor to AMP mode operation and sets up the JTAG chain for reprogramming of the FPGA or CPLD if required Table 5 14 JTAG Configuration P12 Pins Linked JTAG Cha...

Page 46: ...ly 0x 000C Board Revision Read write 0x 0010 BIT and User LEDs Read write 0x 0014 BMM Control Read write NA Blank address for expansion 0x 001C Geographic Address Read write 0x 0020 Platform Multiplier Read write 0x 0024 Core Multiplier Read write 0x 0028 Miscellaneous Functions Read only 0x 002C Axis Timer 1 Read only 0x 0030 Axis Timer 2 Read only 0x 0034 Axis Timer 3 Read only 0x 0038 Axis Time...

Page 47: ... to for them to be cleared Level interrupts are not latched and disappear if the interrupt source changes the level All interrupts signals are active low signals but the Interrupt register uses a 1 to represent an active interrupt 0x 0070 Hardware Exclusive Access Semaphore Read write 0x 0074 Core 0 Semaphore Read write 0x 0078 Core 1 Semaphore Read write 0x 007C CSR Exclusive Access Semaphore Rea...

Page 48: ... bit 6 0 16 7 R W GPIO bit 7 0 15 8 0 orig R W Ethernet PHY on ETSEC 1 0 14 9 R W Ethernet PHY on ETSEC 3 0 13 10 R W USB INT A 0 12 11 R W USB INT B 0 11 12 R W USB INT C 0 10 13 R W CPU_HOT_ALERT 0 9 14 R W THERMAL SHUTDOWN 0 8 15 R W PEX8114_INT_A 0 7 16 R W EXTERNAL_INT if enabled 0 6 17 R W REAL TIME CLOCK INT 0 5 18 R W WATCHDOG 0 INTERRUPT 0 4 19 R W WATCHDOG 1 INTERRUPT 0 3 20 R W Reserved...

Page 49: ...e 5V input voltage and the P3V3_LIN rail remain powered to maintain RTC and BMM functions Chip Select CS2 Offset 0x0004 LAD Bit Reg Bit R W Interrupt Source Reset Value 23 0 R W GPIO bit 0 0 22 1 R W GPIO bit 1 0 21 2 R W GPIO bit 2 0 20 3 R W GPIO bit 3 0 19 4 R W GPIO bit 4 0 18 5 R W GPIO bit 5 0 17 6 R W GPIO bit 6 0 16 7 R W GPIO bit 7 0 15 8 0 orig R W Ethernet PHY on ETSEC 1 0 14 9 R W Ethe...

Page 50: ... Offset 0x0008 Reset value 0x0000 LAD Bit Reg Bit R W Interrupt Source 23 0 R W GPIO bit 0 22 1 R W GPIO bit 1 21 2 R W GPIO bit 2 20 3 R W GPIO bit 3 19 4 R W GPIO bit 4 18 5 R W GPIO bit 5 17 6 R W GPIO bit 6 16 7 R W GPIO bit 7 15 8 0 orig R W Ethernet PHY on ETSEC 1 14 9 R W Ethernet PHY on ETSEC 3 13 10 R W USB INT A 12 11 R W USB INT B 11 12 R W USB INT C 10 13 R W CPU_HOT_ALERT 9 14 R W THE...

Page 51: ...y any software The register is echoed in power up defaults loaded into the M8641 on the Local AD bus lines This replication is for ease of use with an emulator Chip Select CS2 Offset 0x000C Reset value Depends on board revision LAD Bit Reg Bit R W Description 15 0 R PCB rev bit 0 14 1 R PCB rev bit 1 13 2 R PCB rev bit 2 12 3 R PCB minor rev bit 0 11 4 R PCB minor rev bit 1 10 5 R FPGA rev bit 0 9...

Page 52: ...s for GPIO At power up all the GPIO lines default to inputs so the reset value of the GPIO Input register depends on external circuit conditions Reads and writes to the register are synchronous to the local clock bus so fast operations generate synchronous timing on the GPIO pins at a maximum frequency of the local bus speed which is 100 MHz for 400 MHz platforms or 133 MHz for 533 MHz platforms T...

Page 53: ...te 1 to invert the value into the GPIO Input and Interrupt registers 14 1 R W GPIO 1 invert write 1 to invert the value into the GPIO Input and Interrupt registers 13 2 R W GPIO 2 invert write 1 to invert the value into the GPIO Input and Interrupt registers 12 3 R W GPIO 3 invert write 1 to invert the value into the GPIO Input and Interrupt registers 11 4 R W GPIO 4 invert write 1 to invert the v...

Page 54: ...e same way as the other interrupts 6 5 4 GPIO output register Chip Select CS2 Offset 0x005C Reset value 0x00 LAD Bit Reg Bit R W Description 15 0 R W GPIO 0 direction 0 Input 1 Output 14 1 R W GPIO 1 direction 0 Input 1 Output 13 2 R W GPIO 2 direction 0 Input 1 Output 12 3 R W GPIO 3 direction 0 Input 1 Output 11 4 R W GPIO 4 direction 0 Input 1 Output 10 5 R W GPIO 5 direction 0 Input 1 Output 9...

Page 55: ...er so each slot has a specific address The GAP signal is a parity signal which dictates that the number of pins tied to ground is odd Software can check that the global address is valid 0 is the active level Hence from the VPX specification Table 6 2 Slot GA 01234 GAP Slot 1 01111 1 Slot 2 10111 1 Slot 3 00111 0 Chip Select CS2 Offset 0x001C LAD Bit Reg Bit R W Description Reset Value 15 0 R GLOB_...

Page 56: ...es not boot e g because the memory is not capable of working at a higher speed then cycling the power returns the register to its safe power up default Take care when selecting multiplier values as only a few are valid and produce sensible results From the 8641D specification Chip Select CS2 Offset 0x0020 Reset value Most probably set to 6 1 0110 for early boards for a 400 MHz platform clock LAD B...

Page 57: ...reset i e the core speed can be adjusted by writing to this register and asserting the Reset signal The register returns to its default following a power cycle The meaning of the bits is reproduced here from the 8641D specification Chip Select CS2 Offset 0x0024 LAD Bit Reg Bit R W Description Reset Value 15 0 R W DP 0 Variant dependent 14 1 R W DP 1 Variant dependent 13 2 R W DP 2 Variant dependen...

Page 58: ...ware is running See Section 4 4 2 regarding AMP SMP mode selection 6 9 2 PEX8518 mode The PEX8518 Switch device defaults to a mode selected by strapping resistors This mode can be overridden by the CPLD Swapping the mode allows a blank SBC330 to be Flash programmed over PCIe from another host during production Chip Select CS2 Offset 0x0028 Reset value 0x0096 LAD Bit Reg Bit R W Description Reset V...

Page 59: ... SROMs either during development or by customer configuration If this is required bits 10 and 9 must be set so that the appropriate SROM is seen as present by the corresponding PEX device At power up both bits are set to 1 disable SROMs At reset both bits are sticky to the last value written 6 10 Backplane Registers The VPX specification includes several System signals that are either bused along ...

Page 60: ... and writes to the Core Semaphore Register Once the Core Semaphore Register has been accessed normally to take a semaphore for a resource the Hardware Exclusive Access Semaphore Register should be written to with a 0x0 to clear it It is the software s responsibility NOT to update the Core Semaphore Register if the Hardware Exclusive Access Semaphore Register returns a 1 when called The initial val...

Page 61: ... 1 0x0 13 2 R W if HWA Sem taken Core 0 Core 1 Semaphore bit 2 0x0 12 3 R W if HWA Sem taken Core 0 Core 1 Semaphore bit 3 0x0 11 4 R W if HWA Sem taken Core 0 Core 1 Semaphore bit 4 0x0 10 5 R W if HWA Sem taken Core 0 Core 1 Semaphore bit 5 0x0 9 6 R W if HWA Sem taken Core 0 Core 1 Semaphore bit 6 0x0 8 7 R W if HWA Sem taken Core 0 Core 1 Semaphore bit 7 0x0 7 8 R W if HWA Sem taken Core 0 Cor...

Page 62: ... power up it is cleared to 0x0 such that it is available 6 11 3 Test and Set TAS semaphore register This Semaphore register works in the same way as the CSR Exclusive Semaphore register Generally its purpose is to support VxWorks Shared Memory Objects Core0 Core n of a multicore CPU uses this register to control access to an area of shared memory normally volatile RAM At power up it is cleared to ...

Page 63: ...determine the address of the boot Flash areas as described in Section 4 3 The initial value depends on jumper settings Fitted jumpers are indicated by a 1 which is opposite to the signal level The Password Control bit is low 0 so that the password is not visible at power up Page mode is disabled low 0 Page mode is not implemented for the initial release Page mode bits are initialized to 0000b Page...

Page 64: ... R CPLD_JMP2 1 if jumper fitted 13 2 R Flash_BOOT_SEC1 1 if jumper fitted 12 3 R Flash_BOOT_SEC2 1 if jumper fitted 11 4 R W Core 1 boot 0 Core 1 boots from same area as core 0 FF80000 to FFFFFFFF 1 Core 1 boots from FF000000 to FF7FFFFF lower 8 megs 0 both cores boot from the same location 10 5 R W Page Mode enable 0 9 6 R W Page mode bit 0 0 8 7 R W Page mode bit 1 0 7 8 R W Page mode bit 2 0 6 ...

Page 65: ...atchdog Timers which can be controlled from either a fast 10 MHz 100 ns period or a slow 1 25 KHz 0 8 mS period clock Using the fast clock the watchdog timer range is 200 ns to 6 536 ms whereas using the slow clock the Watchdog Timer range is 8 ms to 52 4 seconds the periods overlap so there are no gaps in the time out period that can be chosen The slow clock is used by default The period of the W...

Page 66: ...ence is calculated as follows Watchdog timer period Watchdog interrupt clock period NOTE The Watchdog interrupt is not yet implemented 6 16 1 Watchdog 0 and 1 control register 6 16 2 Watchdog 0 and 1 preset register Chip Select CS2 Offset 0x0090 Watchdog 0 0x0098 Watchdog 1 LAD Bit Reg Bit R W Description Reset Value 15 0 R Watchdog status 0 Watchdog enabled 1 Watchdog disabled 0x0 14 1 R Watchdog...

Page 67: ...whether the clock source for the Axis timer is from the 66 6 MHz on board clock or whether it is from an external off board clock SBC330 has the ability to receive an external off board high speed differential clock on the VPX specified REF_CLK_P REF_CLK_N signals on P0 Frequencies of up to 50 MHz can be handled In a system there must therefore be an AXIS Timestamp Master which drives the clock an...

Page 68: ...register 3 Most Significant Word Chip Select CS2 Offset 0x002C LAD Bit Reg Bit R W Description Reset Value 15 to 0 0 to 15 R W Timer count Value 0x0000 Chip Select CS2 Offset 0x0030 LAD Bit Reg Bit R W Description Reset Value 15 to 0 0 to 15 R W Timer count value 0x0000 Chip Select CS2 Offset 0x0034 LAD Bit Reg Bit R W Description Reset Value 15 to 0 0 to 15 R W Timer count value 0x0000 ...

Page 69: ...lock if Master 0x000000 7 8 R W Enable 0 Timer counters do not run 1 Timer counters run 0x0 6 9 R W On board clock source 66 6 MHz fixed system clock 0 Do not select 66 6 MHz on board clock 1 66 6 MHz on board clock selected 0x0 5 10 R W On board clock source Processor Local Clock 100 133 MHz DDR2 clock 2 0 Do not select Processor Local Bus clock 1 Processor Local Bus clock selected 0x0 4 11 R W O...

Page 70: ...400 1000 MHz A total of six configuration resistors control the default platform and core speed of the processor These are R570 R569 R571 10K pull ups to P3V3 and R215 R244 R245 1K pull downs to ground R570 R215 control CFG 0 R569 R244 control CFG 1 and R571 R245 control CFG 2 Chip Select CS2 Offset 0x00AC LAD Bit Reg Bit R W Description Reset Value 15 to 13 0 to 2 R Straight binary of resistor pu...

Page 71: ... 15 0 R W User defined bit 0 0 14 1 R W User defined bit 1 0 13 2 R W User defined bit 2 0 12 3 R W User defined bit 3 0 11 4 R W User defined bit 4 0 10 5 R W User defined bit 5 0 9 6 R W User defined bit 6 0 8 7 R W User defined bit 7 0 7 8 R W User defined bit 8 0 6 9 R W User defined bit 9 0 5 10 R W User defined bit 10 0 4 11 R W User defined bit 11 0 3 12 R W User defined bit 12 0 2 13 R W U...

Page 72: ..._USER_LED1 DS211 Blue PSU P1V SERDES DS201 Green CPLD_USER_LED2 DS212 Blue PSU P1V_Platform DS202 Red BIT core 0 DS213 Blue PSU P_Vcore DS203 Red BIT core 1 DS214 Blue Vcc 5 Volt supply DS204 Yellow Ethernet Channel 1 DS216 Orange To PEX8114 USB DS205 Yellow Ethernet Channel 3 DS217 Orange To SATA DS206 Blue PSU P3V3_linear DS218 Orange Off board 4 way PCIE DS207 Blue PSU P1V8 DDR2 DS219 Orange Sw...

Page 73: ...nvironment progress Ordinarily user software should not make use of these LEDs unless BIT code is not present in which case the BSP and or user code should switch them off Table 7 3 BIT Status LEDs LED Function Description DS202 DS203 BIT Fail core 0 BIT Fail core 1 Once a board has been programmed with firmware these LEDS are LIT red at power up Software is used to switch them off BIT code VxWork...

Page 74: ...ult finding for when PSU rails have failed and normal electrical investigation may not be possible Each LED is driven via a FET switch and cannot be controlled by software Table 7 6 PCI Express Link Status LEDs LED Function Description DS216 DS217 DS218 DS219 On board and Off board PCIe Status When lit all on board PCIe links have initialized and trained successfully on at least one lane of each P...

Page 75: ... on line help files The VxWorks Workbench BSP Maintenance product code is SBC330BSP WBV1M 8 2 BIT BIT probes from the lowest level of discrete on board hardware up to Line Replaceable Unit level within a system ensuring the highest degree of confidence in system integrity BIT includes comprehensive configuration facilities allowing automatic initialization tests to be defined for the desired mix o...

Page 76: ...ot firmware technology is absorbed into such boot methodology 8 4 Background Condition Screening BCS supplements the BIT initialization test coverage with further health screening that can co exist with a standard COTS Operating System In contrast to a traditional BIT style test the intensity and coverage of which makes it destructive to operating systems the configurable BCS package allows functi...

Page 77: ...ce Also by geographical arrangement each pair is completely shielded left right top and bottom from the next signal pair VPX connectors may appear less robust than previous industrial connectors but their construction means that actually they are more robust they cannot suffer from pins bending to create shorts and the multiple contact solution results in high reliability in high vibration environ...

Page 78: ... NC NC NC NC NC 3 VCC VCC VCC NC VCC VCC VCC 4 P0_NVMRO P0_SYSRESET GND NC GND SM 3 SM 2 5 SM 1 SM 0 GND P3V3_AUX GND GA 4 GAP 6 GA 0 GA 1 GND NC GND GA 2 GA 3 7 JTAG_TRST JTAG_TMS GND JTAG_TDI JTAG_TDO GND JTAG_TCK 8 GND BUS_P BUS_N GND BP_CLK_P BP_CLK_N GND Table 9 2 J0 Pinout Pin A B C D E F G H I 1 NOT USED NOT USED NOT USED NOT USED NOT USED NOT USED NOT USED NOT USED NOT USED 2 NOT USED NOT ...

Page 79: ... is not used by SBC330 P0_NVMRO I O Non Volatile Memory Read Only Used by SBC330 as an input Also can be driven by SBC330 by FPGA if the SBC330 is configured to be VPX slot 1 system controller P0_SYSRESET I O VPX backplane System Reset SBC330 holds in reset till this signal is negated Can drive it for minimum 20mS if VPX slot 1 controller P3V3_AUX Input VPX 3 3V_AUX Power Input See Section A 2 1 f...

Page 80: ...TH1_B_P ETH1_B_N GND COM2_232TX 14 GND ETH1_C_P ETH1_C_N GND ETH1_D_P ETH1_D_N GND 15 ETH0_A_P ETH0_A_N GND ETH0_B_P ETH0_B_N GND COM2_232RX 16 GND ETH0_C_P ETH0_C_N GND ETH0_D_P ETH0_D_N GND Table 9 5 J1 Pinout Pin A B C D E F G H I 1 PCIE_4W_ RX0P PCIE_4W_ RX0N GND GND PCIE_4W_ TX0P PCIE_4W_ TX0N GND GND NOT USED 2 GND GND PCIE_4W_ RX1P PCIE_4W_ RX1N GND GND PCIE_4W_ TX1P PCIE_4W_ TX1N GND 3 PCI...

Page 81: ... is not used by SBC330 P3V3_BAT Power Input VPX 3 3 Volt Battery backup supply input see Section A 2 1 for details PCIE_4W_TX RXnN P I O 4 lane PCI Express link lane n transmit receive data differential pair PCIEn_TX RXnN P I O PCIe bus transmit receive differential pair signals RFU1 Undefined Defined by VITA 46 0 as Reserved for Future Use SATAn_RX_N P Input Serial ATA channel n Receive data diff...

Page 82: ...SB3_P USB3_N GND 15 GPIO 0 GPIO 1 GND GPIO 2 GPIO 3 GND SEQ_OUT 16 GND GPIO 4 GPIO 5 GND GPIO 6 GPIO 7 GND Table 9 8 J2 Pinout Pin A B C D E F G H I 1 PCIE1_RX4P PCIE1_RX4N GND GND PCIE1_TX4P PCIE1_TX4N GND GND PS2_5V 2 GND GND PCIE1_RX5P PCIE1_RX5N GND GND PCIE1_TX5P PCIE1_TX5N GND 3 PCIE1_RX6P PCIE1_RX6N GND GND PCIE1_TX6P PCIE1_TX6N GND GND COM1_232RTS 4 GND GND PCIE1_RX7P PCIE1_RX7N GND GND PC...

Page 83: ...air PCIEn_TXnN P Output 8 lane PCI Express link B 2 lane x transmit data differential pair PS2_5V Output SBC330 provides fused 5V power to Keyboard and Mouse devices The fuse prevents the SBC330 against any harmfully high user generated voltages SATAn_RX_N P Input Serial ATA channel n receive data differential pair SATAn_TX_N P Output Serial ATA channel n transmit data differential pair SEQ IN Inp...

Page 84: ...ed to the on board FPGA Customers are advised to remove or secure the ZIF locks on these connectors for high vibration use The connector body has been vibration proven at all environmental levels For deep embedded test purposes only a separate card SBC330_TB has been designed to break out these connections to a high speed logic analyzer header and high frequency Oscilloscope feeds Table 9 10 P11 P...

Page 85: ...tecture Ethernet Interfaces 2x 10 100 1000BaseT ports Two Gigabit Ethernet ports Serial ports 2x RS232 with hardware flow control MPC8641D provides COM1 COM2 debug ports USB 4 ports USB 2 0 capable Serial ATA Up to 2 Channels Supports speeds of up to 3 0 Gbps DMA Controllers 4 Available in the MPC8641D for efficiently moving large blocks of data Timers 8 x 31 bit timers Provided by the MPC8641D Pr...

Page 86: ...ed bias to the assembly If such conditions occur toxic fumes may be produced due to the destruction of components A 2 2 Current consumption Current consumption figures for SBC330 are shown below These are given at cold wall temperatures of 25 C and 85 C in a conduction cooled environment All figures were measured on a board with 1 GByte of DDR2 RAM and 256 MBytes of Flash Typical consumption was m...

Page 87: ...tions are carried out using MIL HDBK 217F Notices 1 and 2 parts count method To complement the 217 failure rates some manufacturers data is included where appropriate Q values have been modified according to industry practice Table A 4 Parameter Min Max Vinl 0 3V 0 8V Vinh 2 0V 3 6V Voutl 0 4V Vouth 2 9V Table A 5 Environment Fail Rate FPMH MTBF Hours Ground Benign 30 C 4 08225134 244962 86862 Gro...

Page 88: ... 5 to 2000 Hz 20g peak sawtooth 11 ms duration Up to 95 RH with varying temperature 10 cycles 240 hours Wide temperature rugged cooled by forced air Conformal coated for additional protection Table A 7 Build style Temperature c Low pressure feet Vibration Shock Humidity salt fog Comments Rugged Conduction cooled Level 4 Operating 40 to 75 at the thermal interface Storage 50 to 100 Shock 10 C minut...

Page 89: ...imensions The dimensions of the SBC330 level 4 5 conform to the 3U VPX Standard which in turn calls up the standard for 3U Multilayer EuroCard dimensions specified in the IEEE 1101 1 specification The dimensions of the SBC330 level 1 3 conform to the 3U VPX Standard which in turn calls up the standard for 3U Multilayer EuroCard dimensions specified in the IEEE 1101 2 specification They are nominal...

Page 90: ...ne 2 BIT only 3 VxWorks only 4 BIT VxWorks Reserved 0 Memory 0 512 MB 1x512 1 1 GB 2x512 2 Reserved 3 2 GB 2x1G Processor 0 Single core 1 GHz 1 Dual core 1 GHz 2 Single core 1 33 GHz 3 Dual core 1 33 GHz 4 Single core 1 5 GHz 5 Dual core 1 5 GHz Build Level 1 Build Level 1 2 Build Level 2 3 Build Level 3 4 Build Level 4 5 Build Level 5 ...

Page 91: ...89 E EMI EMC 12 Error Reporting 42 Ethernet 35 ETI 39 F Features 9 Flammability 12 Flash 20 27 29 Flash Password 20 FPGA 35 G GPIO 37 87 H Handling 12 Hard Reset 42 Heatsink 12 I I2C 38 Addressing 38 Reset 40 Inspection 14 Installation 15 Inter board Sequencing 17 Interrupt Controller 43 Interrupts 42 External 43 PCI 44 Registers 47 SMI 43 Introduction 8 J JTAG 45 L Labels 14 LEDs BIT Status 73 Et...

Page 92: ...ore 1 Semaphore 61 Core Multiplier 57 CSR Exclusive Access Semaphore 62 Flash Control 63 Flash Password 64 Flash Size 65 Geographic Address 55 GPIO 52 GPIO Direction 54 GPIO Input 53 GPIO Invert 53 GPIO Output 54 ID 63 Interrupt 48 Interrupt Edge Level 50 Interrupt Mask 49 Miscellaneous Functions 58 Platform Multiplier 56 Scratch 71 TAS Semaphore 62 Test 69 Watchdog 65 Registers 46 Resets 42 Retur...

Page 93: ...TENTS ARE PROVIDED AS IS WITH NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED INCLUDING BUT NOT LIMITED TO WARRANTIES OF DESIGN MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ALL OTHER LIABILITY ARISING FROM RELIANCE UPON ANY INFORMATION CONTAINED HEREIN IS EXPRESSLY DISCLAIMED GE Intelligent Platforms Information Centers Americas 1 800 322 3616 or 1 256 880 0444 Asia ...

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