Publication No. SBC330-0HH/3
Functional Description 43
5.10.4 Soft reset
A
soft
reset
(SRESET
signal)
causes
the
processing
core
to
reach
a
recoverable
state
and
then
branch
to
either
0x0000
0100
or
0xFFF0
0100,
depending
on
the
state
of
the
IP
bit
in
the
core’s
Machine
State
Register.
No
other
on
‐
board
resources
are
reset.
The
processing
cores
may
be
individually
soft
reset
by
software
using
the
Processor
Core
Initialization
Register
within
the
MPC8641D
interrupt
controller.
A
soft
reset
is
initiated
on
both
processing
cores
when
the
SRESET~
signal
on
the
BDM
header
is
asserted.
A
soft
reset
is
initiated
on
both
processing
cores
if
the
front
panel
switch
is
activated
(build
level
1
to
3
boards
only).
5.10.5 System Management Interrupt
A
System
Management
Interrupt
(SMI~)
to
the
processing
cores
can
only
be
generated
by
asserting
the
external
SMI0~
or
SMI1~
pins
on
the
MPC8641D.
These
pins
are
unused
on
the
SBC330.
5.10.6 External Interrupts (INT~)
The
processing
core
external
interrupt
pin
(INT~)
is
asserted
for
a
pending
interrupt
from
the
interrupt
controller
in
the
MPC8641D.
On
the
SBC330,
INT8
is
used
to
receive
interrupts
from
the
secondary
interrupt
controller
in
the
FPGA.
INT0
to
INT7
are
left
free
for
PCIe
interrupt
messages.
This
minimizes
any
latency
of
PCIe
response
and
maximizes
its
bandwidth.
The
MCP8641D
interrupt
controller
supports
routing
of
internal
and
external
interrupt
sources
to
one
of
the
two
processing
cores,
including
programmable
priority
levels.
All
interrupt
routing
between
the
source
and
the
processing
cores
is
established
by
software.
Core
0
and
Core
1
may
transfer
interrupts
using
inter
‐
core
messages.
5.10.7 Secondary Interrupt Controller
The
Secondary
Interrupt
Controller
within
the
Local
Bus
Control
FPGA
(see
Figure
5
‐
5
)
allows
all
on
‐
board
interrupts
to
be
routed
to
two
of
the
MPC8641D
external
interrupt
inputs.
(In
the
default
release,
only
1
of
the
two
interrupt
pins
is
used:
INT8).
The
BSP
dictates
which
core
handles
which
interrupts.
This
allows
software
to
configure
on
‐
board
devices
to
interrupt
either
of
the
cores
independently
from
the
other,
providing
maximum
flexibility.
The
external
interrupt
input
to
the
MPC8641D
has
associated
with
it
a
mask
register
within
the
secondary
interrupt
controller,
which
determines
which
of
the
interrupts
is
visible
to
the
processor.
See
Section
6.2.2
for
more
information.