Publication No. SBC330-0HH/3
Functional Description 33
A
serial
SPI
‐
type
EEPROM
(ATMEL
25256A
(32Kx
8))
is
used
to
configure
registers
within
the
device
at
power
‐
up.
This
EEPROM
is
write
‐
protected
by
default
and
can
be
write
‐
enabled
by
clearing
the
Serial
EEPROM
Write
Protect
bit
in
the
Miscellaneous
Functions
Register
(offset
0x28).
This
bit
may
only
be
cleared
when
the
NVMRO
signal
on
the
VPX
backplane
is
negated.
In
the
event
of
this
EEPROM
device
becoming
corrupted,
it
is
possible
to
recover
it
by
toggling
the
EEPROM
Presence
Detect
bit
of
the
Miscellaneous
Functions
register.
In
this
case,
the
switch
configuration
is
defined
by
hardware
strapping.
Each
port
can
negotiate
down
to
smaller
link
widths
if
required
(such
as
if
a
fault
occurs
on
any
particular
lane).
Port
widths
of
x1,
x2,
x4
and
x8
are
supported.
Port
0
is
connected
to
the
MPC8461D
and
is
usually
configured
as
the
Upstream
Port.
The
PEX8518
is
connected
to
on
‐
board
I
2
C
Bus
1
(address
0xB0)
to
allow
configuration
by
the
processor
and
out
‐
of
‐
band
monitoring
of
link
status.
The
status
of
all
of
the
on
‐
board
links,
and
the
two
VPX
links
can
be
determined
from
LEDs
on
the
rear
of
the
board
(see
Chapter
7 •
)
Further
status
information
(the
number
of
active
lanes,
etc.)
can
be
ascertained
from
registers
within
the
Switch
device.
The
default
Switch
setting
is
for
the
external
4
‐
lane
port
to
be
Transparent.
This
allows
the
SBC330
to
attach
to
PCIe
End
‐
Point
devices.
To
connect
together
two
intelligent
devices
on
PCIE,
such
as
two
SBC330
processor
boards,
on
one
of
the
boards
the
PEX8518
Switch
needs
to
be
set
as
Non
‐
Transparent
for
the
external
port
(Port
1).
To
achieve
this,
the
SPI
EEPROM
must
be
reprogrammed
via
Software.
This
changes
the
power
‐
up
configuration
of
the
switch
to
create
a
non
transparency
such
that
there
is
no
collision
on
memory
domains.
The
intelligent
device
that
has
not
been
set
to
have
a
non
‐
transparent
port
passes
configuration
through
to
the
PEX8518
Switch
port
1,
but
not
beyond
it.
The
local
processor
on
the
board
that
has
been
set
such
that
the
PEX8518
port
1
is
non
‐
transparent
will
not
try
to
pass
any
configuration
cycles
to
the
remote
host
device.
In
this
way,
full
PCI
configuration
is
achieved.
On
the
SBC330
there
is
an
orange
LED
(DS218)
connected
to
the
PEX8518
Switch
to
show
if
the
external
PCIe
4
‐
lane
port
is
connected.
If
the
LED
is
lit,
then
PCIe
link
connection
has
been
established.
This
LED
will
not
light
between
two
SBC330
boards
if
either
both
boards
or
neither
board
have
had
their
default
PEX8518
SPI
EEPROM
contents
adjusted
so
that
1
of
the
boards
sets
Port
1
to
be
Non
‐
transparent.
Figure 5-3 Non-Transparent Port Setting for Host- Host PCIe Communication
