GE SBC330 3U VPX, Hardware Reference Manual

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50 SBC330 3U VPX Single Board Computer Publication No. SBC330-0HH/3
6.2.3 Interrupt Edge/Level register
This register defines whether the incoming interrupt is dealt with as a ‘Level’ or
an ‘Edge’ signal. The default at power ‐ up and reset is 0x0000, which dictates all
‘Level’ interrupts.
Setting a bit to 1 changes an interrupt to ‘Edge’. Edge interrupts are latched in the
Interrupt register which then needs to have the same bit written ‐ to as a ‘0’ for the
interrupt to be cleared.
Chip Select CS2
Offset 0x0008
Reset value 0x0000
LAD Bit Reg Bit R/W Interrupt Source
23 0 R/W GPIO bit (0)
22 1 R/W GPIO bit (1)
21 2 R/W GPIO bit (2)
20 3 R/W GPIO bit (3)
19 4 R/W GPIO bit (4)
18 5 R/W GPIO bit (5)
17 6 R/W GPIO bit (6)
16 7 R/W GPIO bit (7)
15 8/0 (orig) R/W Ethernet PHY on ETSEC 1
14 9 R/W Ethernet PHY on ETSEC 3
13 10 R/W USB INT A
12 11 R/W USB INT B
11 12 R/W USB INT C
10 13 R/W CPU_HOT_ALERT
9 14 R/W THERMAL SHUTDOWN
8 15 R/W PEX8114_INT_A
7 16 R/W EXTERNAL_INT (if enabled)
6 17 R/W REAL TIME CLOCK INT
5 18 R/W WATCHDOG 0 INTERRUPT
4 19 R/W WATCHDOG 1 INTERRUPT
3 20 R/W (Reserved for expansion)
2 21 R/W (Reserved for expansion)
1 22 R/W (Reserved for expansion)
0 23 R/W (Reserved for expansion)