38 SBC330 3U VPX Single Board Computer
Publication No. SBC330-0HH/3
5.7 I
2
C
The
MPC8641D
provides
two
I
2
C
buses,
both
of
which
are
set
up
to
run
at
400 KHz.
This
speed
is
derived
as
a
divisor
of
the
MPX
Bus/Platform
speed,
so
be
aware
that
the
divisor
may
need
adjusting
if
the
platform
bus
changes.
Figure
5
‐
5
shows
the
I
2
C
circuitry
of
the
board.
Figure 5-4 I
2
C Architecture
5.7.1 I
2
C addressing
I
2
C
devices
have
8
‐
bit
addresses.
To
write
to
I
2
C
devices,
the
LSB
is
0;
to
read
from
I
2
C
devices,
the
address
is
normally
the
write
address
+
1.
The
following
table
shows
the
addresses
used
by
the
I
2
C
devices
connected
to
the
on
‐
board
I
2
C
buses.
These
are
the
byte
addresses
that
would
be
used
to
write
to/read
from
the
device
on
the
bus
(i.e.
the
7
‐
bit
device
address,
and
the
least
significant
bit
set
to
‘0’
or
‘1’
as
required).
Table 5-11 I2C Bus Addresses
Bus 0
Bus 1
Device
Address (Hex)
Device
Address (Hex)
Read Write
Read
Write
EEPROM
A9
A8
RTC
A3
A2
PEX8518
E1
E0
SPD 1
A5
A4
PCIe Clock
DD
DC
SPD 2
A1
A0
Temp Sensor
99
98
PWR MAN
FD
FC
BMM
--
--
DS1682 ETI
D7
D6
MC8641D
00
MC8641D
00
