56 SBC330 3U VPX Single Board Computer
Publication No. SBC330-0HH/3
6.7 Platform Multiplier Register
This
register
is
loaded
during
power
‐
up/reset
with
hard
‐
coded
values.
It
contains
the
same
values
as
those
that
are
passed
into
the
8641
PORPLLSR
for
the
associated
bits.
Their
meaning
is
given
in
the
8641D
specification
and
repeated
below
for
convenience.
Writing
to
the
register
has
no
effect
until
the
board
is
reset.
This
register
is
‘sticky’
through
a
front
panel
reset,
i.e.
the
processor
speed
may
be
changed
by
writing
to
this
register
and
pressing
reset.
If
the
processor
does
not
boot,
e.g.
because
the
memory
is
not
capable
of
working
at
a
higher
speed,
then
cycling
the
power
returns
the
register
to
its
safe
power
up
default.
Take
care
when
selecting
multiplier
values
as
only
a
few
are
valid
and
produce
sensible
results.
From
the
8641D
specification:
Chip
Select
CS2
Offset
0x0020
Reset
value
Most
probably
set
to
6:1
(0110)
for
early
boards
for
a
400
MHz
platform
clock
LAD Bit
Reg Bit
R/W
Description
Reset Value
15
0
R/W
ADD28
Variant dependent
14
1
R/W
ADD29
Variant dependent
13
2
R/W
ADD30
Variant dependent
12
3
R/W
ADD31
Variant dependent
Table 6-3
Signal
Binary
Platform Clock (MPX Bus)
Multiplier
Comments
LA[28:31]
0100
4:1
0101
5:1
0110
6:1
Default for 400 MHz platforms
0111
Reserved. Not valid
1000
8:1
Default for 533 MHz platforms
1001
9:1