41
Bit 0: Route finding
0
According to the memory registers (default value)
1
Trace the received packet.
Table 5–29: Settings of the route
REG26: Data input timeout
[default value: 00H]
•
Sets the vacant duration time interval to recognize as the end of the message data
input in the headerless stream mode.
REG27: Reserved
[default value: 00H]
•
The FDL01TU does not use this register. Keep the default value as it is.
Summary of Contents for FDL01TU
Page 14: ......
Page 15: ...1 1 SECTION 1 INTRODUCTION ...
Page 19: ...5 2 SECTION 2 SYSTEM INSTALLATION ...
Page 25: ...11 3 SECTION 3 SYSTEM OPERATION ...
Page 34: ...20 ...
Page 35: ...21 4 SECTION 4 FUNCTION CONTROL METHODS ...
Page 41: ...27 5 SECTION 5 MEMORY REGISTER DESCRIPTION ...
Page 56: ...42 ...
Page 57: ...43 6 SECTION 6 COMMAND SET DESCRIPTION ...
Page 76: ...62 ...
Page 77: ...Futaba Corporation Rev 020323 01 7 APPENDIX 7 SECTION ...
Page 82: ...68 7 4 Dimensions 7 4 1 FDL01TU 7 4 2 Communication Cable ...