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Fujitsu MHT2040BH, Product Manual

The Fujitsu MHT2040BH is a reliable and high-performance hard drive designed for your storage needs. To fully utilize its capabilities, make sure to refer to the product manual. At manualshive.com, you can easily download the manual for free, ensuring seamless integration and optimal usage of this exceptional product.

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5.2   Logical Interface 

C141-E203-01EN 5-13 

The host system uses the Register - Host to Device FIS when information in the 
Register Block is transferred from the host system to the device.  This is the 
mechanism for issuing the ATA command from the host system to the device. 

C -  To update the Command field, "1" would be set in this field; and to update the 
Device Control field, "0" would be set in the field. 

If both C = 1 and SRST = 1 are set, operation is not guaranteed. 

5.2.3.3  Register - Device to Host 

The Register - Device to Host FIS has the following layout: 

 

3
1 

3
0 

2
9 

2
8 

2
7 

2
6 

2
5 

2
4 

2
3 

2
2 

2
1 

2
0 

1
9 

1
8 

1
7 

1
6 

1
5 

1
4 

1
3 

1
2 

1
1 

1
0 

9  8 7 6 5 4 3  2  1  0 

Error Status 

R  I  R  Reserved (0) 

FIS Type (34h) 

0 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Device 

LBA High 

LBA Mid 

LBA Low 

1 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Reserved (0) 

LBA High (exp) 

LBA Mid (exp) 

LBA Low (exp) (0) 

2 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Reserved (0) 

Reserved (0) 

Sector Count (exp) 

Sector Count 

3 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Reserved (0) 

Reserved (0) 

Reserved (0) 

Reserved (0) 

4 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Figure 5.4  Register - Device to Host FIS layout 

The Register - Device to Host FIS is used when information concerning the Shadow 
Register Block in the host adapter is updated.  This FIS indicates that the device has 
completed a command operation.  Furthermore, this is a mechanism for changing 
information concerning the Shadow Register Block of the host adapter. 

I -  If this bit is set, an interrupt request is issued to the host system. 

5.2.3.4  DMA Active - Device to Host 

The DMA Active - Device to Host FIS has the following layout: 

 

3
1 

3
0 

2
9 

2
8 

2
7 

2
6 

2
5 

2
4 

2
3 

2
2 

2
1 

2
0 

1
9 

1
8 

1
7 

1
6 

1
5 

1
4 

1
3 

1
2 

1
1 

1
0 

9  8 7 6 5 4 3  2  1  0 

Reserved (0) 

Reserved (0) 

R  R  R  Reserved (0) 

FIS Type (39h) 

0 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Figure 5.5  DMA Active - Device to Host FIS layout 

Summary of Contents for MHT2040BH

Page 1: ...C141 E203 01EN MHT2080BH MHT2060BH MHT2040BH DISK DRIVES PRODUCT MANUAL ...

Page 2: ...ncidental or consequential damages arising therefrom FUJITSU DISCLAIMS ALL WARRANTIES REGARDING THE INFORMATION CONTAINED HEREIN WHETHER EXPRESSED IMPLIED OR STATUTORY FUJITSU reserves the right to make changes to any products described herein without further notice and without obligation This product is designed and manufactured for use in standard applications such as office work personal device...

Page 3: ...C141 E203 01EN Revision History 1 1 Edition Date Revised section 1 Added Deleted Altered Details 01 2004 02 27 1 Section s with asterisk refer to the previous edition when those were deleted ...

Page 4: ...This page is intentionally left blank ...

Page 5: ...view This chapter gives an overview of the disk drive and describes their features CHAPTER 2 Device Configuration This chapter describes the internal configurations of the disk drive and the configuration of the systems in which they operate CHAPTER 3 Installation Conditions This chapter describes the external dimensions installation conditions and switch settings of the disk drive CHAPTER 4 Theor...

Page 6: ...lert signal is centered followed below by the indented message A wider line space precedes and follows the alert message to show where the alert message begins and ends The following is an example Example Data corruption Avoid mounting the disk drive near strong magnetic sources such as loud speakers Ensure that the disk drive is not affected by external magnetic fields The main alert messages in ...

Page 7: ...t at the back of this manual and forward it to the address described in the sheet Liability Exception Disk drive defects refers to defects that involve adjustment repair or replacement Fujitsu is not liable for any other disk drive defects such as those caused by user misoperation or mishandling inappropriate operating environments defects in the power supply or cable problems of the host system o...

Page 8: ...This page is intentionally left blank ...

Page 9: ...rm the procedure correctly Task Alert message Page Normal Operation Data corruption Avoid mounting the disk drive near strong magnetic sources such as loud speakers Ensure that the disk drive is not affected by external magnetic fields Damage Do not press the cover of the disk drive Pressing it too hard the cover and the spindle motor contact which may cause damage to the disk drive Static When ha...

Page 10: ...This page is intentionally left blank ...

Page 11: ...ES PRODUCT MANUAL C141 E203 This manual Device Overview Device Configuration Installation Conditions Theory of Device Operation Interface Operations MHT2080BH MHT2060BH MHT2040BH DISK DRIVES MAINTENANCE MANUAL C141 F068 Maintenance and Diagnosis Removal and Replacement Procedure ...

Page 12: ...This page is intentionally left blank ...

Page 13: ...1 6 1 4 Environmental Specifications 1 8 1 5 Acoustic Noise 1 9 1 6 Shock and Vibration 1 9 1 7 Reliability 1 10 1 8 Error Rate 1 11 1 9 Media Defects 1 11 1 10 Load Unload Function 1 11 1 11 Advanced Power Management 1 12 1 12 Interface Power Management IPM 1 14 1 12 1 Host initiated Interface Power Management HIPM 1 14 1 12 2 Device initiated Interface Power Management DIPM 1 14 CHAPTER 2 Device...

Page 14: ...nection 3 11 3 3 5 Note about SATA interface cable connection 3 11 CHAPTER 4 Theory of Device Operation 4 1 4 1 Outline 4 2 4 2 Subassemblies 4 2 4 2 1 Disk 4 2 4 2 2 Spindle 4 2 4 2 3 Actuator 4 2 4 2 4 Air filter 4 3 4 3 Circuit Configuration 4 3 4 4 Power on Sequence 4 6 4 5 Self calibration 4 7 4 5 1 Self calibration contents 4 7 4 5 2 Execution timing of self calibration 4 8 4 5 3 Command pro...

Page 15: ...5 5 1 3 Electrical specifications 5 6 5 1 4 Connector pinouts 5 8 5 2 Logical Interface 5 9 5 2 1 Communication layers 5 10 5 2 2 Outline of the Shadow Block Register 5 11 5 2 3 Outline of the frame information structure FIS 5 12 5 2 3 1 FIS types 5 12 5 2 3 2 Register Host to Device 5 12 5 2 3 3 Register Device to Host 5 13 5 2 3 4 DMA Active Device to Host 5 13 5 2 3 5 DMA Setup Device to Host o...

Page 16: ...5 43 13 IDLE IMMEDIATE X 95 or X E1 5 44 14 STANDBY X 96 or X E2 5 45 15 IDLE X 97 or X E3 5 46 16 CHECK POWER MODE X 98 or X E5 5 48 17 SLEEP X 99 or X E6 5 49 18 SMART X B0 5 50 19 DEVICE CONFIGURATION X B1 5 67 20 READ MULTIPLE X C4 5 71 21 WRITE MULTIPLE X C5 5 74 22 SET MULTIPLE MODE X C6 5 76 23 READ DMA X C8 or X C9 5 78 24 WRITE DMA X CA or X CB 5 80 25 READ BUFFER X E4 5 82 26 FLUSH CACHE...

Page 17: ...0 48 WRITE LOG EXT X 3F 5 131 49 READ VERIFY SECTOR S EXT X 42 5 133 50 FLUSH CACHE EXT X EA 5 134 51 WRITE MULTIPLE FUA EXT X CE 5 135 52 WRITE DMA FUA EXT X 3D 5 136 53 READ FP DMA QUEUED X 60 5 137 54 WRITE FP DMA QUEUED X 61 5 138 5 3 3 Error posting 5 139 5 4 Command Protocol 5 141 5 4 1 Non data command protocol 5 141 5 4 2 PIO data in command protocol 5 143 5 4 3 PIO data out command protoc...

Page 18: ...wer Save 6 9 6 3 1 Power save mode of the interface 6 9 6 4 Read ahead Cache 6 11 6 4 1 Data buffer structure 6 11 6 4 2 Caching operation 6 12 6 4 3 Using the read segment buffer 6 14 6 4 3 1 Miss hit 6 14 6 4 3 2 Sequential hit 6 15 6 4 3 3 Full hit 6 15 6 4 3 4 Partial hit 6 17 6 5 Write Cache 6 18 6 5 1 Cache operation 6 18 Glossary GL 1 Acronyms and Abbreviations AB 1 Index IN 1 ...

Page 19: ...onfiguration 4 5 Figure 4 3 Power on operation sequence 4 6 Figure 4 4 Read write circuit block diagram 4 9 Figure 4 5 Frequency characteristic of programmable filter 4 10 Figure 4 6 Block diagram of servo control circuit 4 12 Figure 4 7 Physical sector servo configuration on disk surface 4 15 Figure 4 8 Servo frame format 4 16 Figure 5 1 Interface signals 5 2 Figure 5 2 Conceptual diagram of comm...

Page 20: ...UED command protocol 5 149 Figure 5 16 WRITE FP DMA QUEUED command protocol 5 150 Figure 5 17 Power on sequence 5 151 Figure 5 18 COMRESET sequence 5 152 Figure 6 1 Response to power on when the host is powered on earlier than the device 6 2 Figure 6 2 Response to power on when the device is powered on earlier than the host 6 3 Figure 6 3 Response to COMRESET 6 4 Figure 6 4 Response to a software ...

Page 21: ...ing procedure of data 384K Bytes 30000h Bytes of microcode 5 42 Table 5 9 Features Field values subcommands and functions 5 51 Table 5 10 Format of device attribute value data 5 55 Table 5 11 Format of guarantee failure threshold value data 5 55 Table 5 12 Off line data collection status 5 58 Table 5 13 Self test execution status 5 58 Table 5 14 Off line data collection capability 5 59 Table 5 15 ...

Page 22: ...nation of Identifier and Security level and operation of the lock function 5 102 Table 5 28 Contents of security password 5 110 Table 5 29 Data format of Read Log Ext log page 10h 5 125 Table 5 30 Tag field information 5 125 Table 5 31 Command code and parameters 5 139 ...

Page 23: ...Error Rate 1 9 Media Defects 1 10 Load Unload Function 1 11 Advanced Power Management 1 12 Interface Power Management IPM Overview and features are described in this chapter and specifications and power requirement are described The disk drive is 2 5 inch hard disk drives with built in disk controllers These disk drives use the SATA interface protocol which has a high speed interface data transfer...

Page 24: ...voice coil motor in the head positioning mechanism greatly increases the positioning speed The average positioning time is 12 ms at read 1 1 2 Adaptability 1 Power save mode The disk drive is ideal for applications since it supports the power save mode function that works in each of the Idle Standby and Sleep modes and has the Partial and Slumber interface power management functions 2 Wide tempera...

Page 25: ...st data access The next disk read command would normally cause another disk access But if the read ahead data corresponds to the data requested by the next read command the data in the buffer can be transferred instead 4 Error correction and retry by ECC If a recoverable read error occurs the disk drive itself attempt error recovery The ECC has improved buffer error correction for correctable data...

Page 26: ...ead and seek Minimum Track Track Average Maximum Full 1 5 ms typ Read 12ms typ 22 ms typ Start time 4 0 sec typ Interface Compliant with ATA ATAPI 7 SATA1 0a and SATA II 1 0 Cable length less than 1 0m 39 37 inchs Data Transfer Rate 2 To From Media To From Host 53 9 MB s Max 1 5Gbps Max Serial ATA Generation 1 Data Buffer Size 3 8MB Physical Dimensions Height Depth Width 9 5 mm 100 0 mm 70 0 mm 4 ...

Page 27: ...nd sectors are specified as shown in this table 1 2 2 Model and product number Table 1 2 lists the model names and product numbers of the disk drive The model name does not necessarily correspond to the product number as listed in Table 1 2 since some models have been customized and have specifications that are different from those for the standard model If a disk drive is ordered as a replacement...

Page 28: ...r supplies 2 Ripple 5 V Maximum 100 mV peak to peak Frequency DC to 1 MHz 3 A negative voltagelike the bottom figure isn t to occur at 5 V when power is turned off and a thing with no ringing Permissible level 0 2 V Voltage V 5 0 100 200 300 400 500 600 700 800 Time ms 4 3 2 1 0 1 Figure 1 1 Negative voltage at 5 V when power is turned off ...

Page 29: ...leep 6 20 mA 0 1 W Energy Efficiency 4 0 011 W GB rank E MHT2080BH 0 014 W GB rank E MHT2060BH 0 021 W GB rank D MHT2040BH 1 Maximum current and power at starting spindle motor 2 Current and power level when the operation command that accompanies a transfer of 63 sectors is executed 3 times in 100 ms 3 Power requirements reflect nominal values for 5 V power 4 Energy efficiency based on the Law con...

Page 30: ... the need to be concerned with the power on off sequence 1 4 Environmental Specifications Table 1 4 lists the environmental specifications Table 1 4 Environmental specifications Item Specification Temperature Operating Non operating Thermal Gradient 5 C to 55 C ambient 5 C to 60 C disk cover surface 40 C to 65 C 20 C h or less Humidity Operating Non operating Maximum Wet Bulb 8 to 90 RH Non conden...

Page 31: ... Shock and Vibration Table 1 6 lists the shock and vibration specification Table 1 6 Shock and vibration specification Item Specification Vibration Swept sine 1 4 octave per minute Operating Non operating 5 to 500 Hz 9 8m s2 0 peak 1G 0 peak without non recovered errors 5 to 500 Hz 49m s2 0 peak 5G 0 peak no damage Shock half sine pulse Operating Non operating 2205 m s2 0 peak 225G 0 peak 2ms dura...

Page 32: ...o repair MTTR is 30 minutes or less if repaired by a specialist maintenance staff member 3 Service life In situations where management and handling are correct the disk drive requires no overhaul for five years when the DE surface temperature is less than 48 C When the DE surface temperature exceeds 48 C the disk drives requires no overhaul for five years or 20 000 hours of operation whichever occ...

Page 33: ...han 10 times in 10 7 seek operations 1 9 Media Defects Defective sectors are replaced with alternates when the disk drive is formatted prior to shipment from the factory low level format Thus the hosts see a defect free devices Alternate sectors are automatically accessed by the disk drive The user need not be concerned with access to alternate sectors 1 10 Load Unload Function The Load Unload fun...

Page 34: ... 2 Head Unload Standby Immediate command execution 3 Wait Status Checking whether bit 7 of the status register was set to 0 wait to complete STANDBY IMMEDIATE command 4 HDD power supply cutting 1 11 Advanced Power Management The disk drive shifts to the three kinds of APM modes automatically under the Idle condition The APM mode can be chosen with a Sector Count register of the SET FEATURES EF com...

Page 35: ...hat the HDD is waiting for commands has been exceeded Mode 0 Mode shifts from Active condition to Active Idle in 0 2 1 2 and to Low Power Idle in 15 minutes Mode 1 Mode shifts from Active condition to Active Idle in 0 2 1 2 seconds and to Low Power Idle in 10 0 40 0 seconds Mode 2 Mode shifts from Active condition to Active Idle in 0 2 1 2 seconds and to Low Power Idle in 10 0 40 0 seconds After 1...

Page 36: ...inds of IPM modes automatically under the Idle condition 1 Partial mode PMREQ_P is sent when the disk drive requests the Partial mode 2 Slumber mode PMREQ_S is sent when the disk drive requests the Slumber mode I F power states 1 Active state The SATA interface is active and data can be sent and received 2 Partial state The SATA interface is in the Power Down state In this state the interface is s...

Page 37: ...E203 01EN 1 15 Table 1 8 Interface power management IPM Mode I F power state Return time to active I F condition Active Active State Active Partial Partial State 5 to 10 µs maximum Power Down Slumber Slumber State 5 to 10 ms maximum Power Down ...

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Page 39: ... 1 CHAPTER 2 Device Configuration 2 1 Device Configuration 2 2 System Configuration This chapter describes the internal configurations of the hard disk drives and the configuration of the systems in which they operate ...

Page 40: ...ect drive Sensor less DC motor 4 Actuator The actuator uses a revolving voice coil motor VCM structure which consumes low power and generates very little heat The head assembly at the edge of the actuator arm is controlled and positioned by feedback of the servo information read by the read write head If the power is not on or if the spindle motor is stopped the head assembly stays on the ramp out...

Page 41: ...nsists of an LSI chip which includes Serial ATA core to achieve a high performance native Serial ATA controller 2 2 System Configuration 2 2 1 SATA interface Figure 2 2 shows the SATA interface system configuration The disk drive complies with ATA ATAPI 7 SATA 1 0a and SATA II 1 0 standards 2 2 2 Drive connection Serial ATA Adapter Driver Operating System Application 1 Application 2 Application 3 ...

Page 42: ...This page is intentionally left blank ...

Page 43: ...nstallation Conditions 3 1 Dimensions 3 2 Mounting 3 3 Cable Connections This chapter gives the external dimensions installation conditions surface temperature conditions cable connections and switch settings of the hard disk drives ...

Page 44: ...connectors are not included in these dimensions 2 Dimension from the center of the user tap to the base of the connector pins 3 Length of the connector pins 4 Dimension from the outer edge of the user tap to the center of the connector pins 5 Dimension from the outer edge of the user tap to the innermost edge of the connector pins Figure 3 1 Dimensions ...

Page 45: ...g see the FUJITSU 2 5 INCH HDD INTEGRATION GUIDANCE C141 E144 1 Orientation Figure 3 2 illustrates the allowable orientations for the disk drive a Horizontal 1 b Horizontal 1 c Vertical 1 d Vertical 2 e Vertical 3 f Vertical 4 Figure 3 2 Orientation gravity gravity gravity ...

Page 46: ... 0 49N m 5kgf cm m 5kgf cm When attaching the HDD to the system frame do not allow the system frame to touch parts cover and base other than parts to which the HDD is attached 3 Limitation of mounting Note These dimensions are recommended values if it is not possible to satisfy them contact us Screw Screw Details of A 3 0 or less 3 0 or less Frame of system cabinet Frame of system cabinet B PCA A ...

Page 47: ...cause of breather hole mounted to the HDD do not allow this to close during mounting Locating of breather hole is shown as Figure 3 4 For breather hole of Figure 3 4 at least do not allow its around φ 2 4 to block Figure 3 4 Location of breather ...

Page 48: ...mperature from exceeding 60 C Provide air circulation in the cabinet such that the PCA side in particular receives sufficient cooling To check the cooling efficiency measure the surface cover temperatures of the DE Regardless of the ambient temperature this surface cover temperature must meet the standards listed in Table 3 1 Figure 3 5 shows the temperature measurement point 1 Figure 3 5 Surface ...

Page 49: ...rces such as loud speakers Ensure that the disk drive is not affected by external magnetic fields Damage Do not press the cover of the disk drive Pressing it too hard the cover and the spindle motor contact which may cause damage to the disk drive Static When handling the device disconnect the body ground 500 kΩ or greater Do not touch the printed circuit board but hold it by the edges 6 Handling ...

Page 50: ...of the screw strictly M3 0 49N m 5 kgf cm m 5 kgf cm Recommended equipments Contents Model Maker Wrist strap JX 1200 3056 8 SUMITOMO 3M ESD ESD mat SKY 8A Color Seiden Mat Achilles Shock Low shock driver SS 6500 HIOS Place the shock absorbing mat on the operation table and place ESD mat on it Use the Wrist strap Do not hit HDD each other Do not stack when carrying Do not place HDD vertically to av...

Page 51: ...with Host System 3 3 1 Device connector The disk drive has the SATA interface connectors listed below for connecting external devices Figure 3 8 shows the locations of these connectors and terminals SATA interface and power connectors PCA Figure 3 8 Connector locations ...

Page 52: ... in the signal segment View from the connector side View from the PCA side Signal segment Figure 3 9 Power supply pins CN1 3 3 3 Connector specifications for host system Table 3 2 lists the recommended specifications for the host interface connectors Table 3 2 The recommended connector specifications for the host system Segment Name Model Manufacturer SATA interface and power supply Host receptacl...

Page 53: ...y more than 10 kgf of force in the connection direction once they are snugly and securely in position Note Hot Plug These drives support the serial ATA interface and Hot Plug hot pluggable However the disk drive installation and removal procedures and notes on safety precautions with regard to hot plugging vary depending on the specific requirements and environment related conditions of the system...

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Page 55: ...4 3 Circuit Configuration 4 4 Power on Sequence 4 5 Self calibration 4 6 Read write Circuit 4 7 Servo Control This chapter explains basic design concepts of the disk drive Also this chapter explains subassemblies of the disk drive each sequence servo control and electrical circuit blocks ...

Page 56: ...ins disks with an outer diameter of 65 mm and an inner diameter of 20 mm Servo data is recorded on each cylinder total 124 Servo data written at factory is read out by the read head For servo data see Section 4 7 4 2 2 Spindle The spindle consists of a disk stack assembly and spindle motor The disk stack assembly is activated by the direct drive sensor less DC spindle motor which has a speed of 5 ...

Page 57: ... channel RDC The PreAMP consists of the write current switch circuit that flows the write current to the head coil and the voltage amplifier circuit that amplitudes the read output from the head The RDC is the read demodulation circuit using the Modified Extended Partial Response MEEPR and contains the Viterbi detector programmable filter adaptable transversal filter times base generator data sepa...

Page 58: ...ntroller circuit Major functions are listed below Serial ATA interface control and data transfer control Data buffer management Sector format control Defect management ECC control Error recovery and self diagnosis Figure 4 1 Power Supply Configuration ...

Page 59: ... 4 5 MPU HDC RDC 88i6535 Marvell HDC MPU RDC Data Buffer SDRAM Flash ROM FROM SVC TLS2255 Crystal 40MHz R W Pre Amp TLS26B624 Thermistor VCM HEAD SP Motor Media DE PCA Serial ATA Interface Shock Sensor Console Figure 4 2 Circuit Configuration ...

Page 60: ...he head assembly is loaded on the disk d The disk drive positions the heads onto the SA area and reads out the system information e The disk drive sets up a requirement for execution of self calibration This collects data for VCM torque and mechanical external forces applied to the actuator and updates the calibrating value f The drive becomes ready The host can issue commands Start Self diagnosis...

Page 61: ...ory calibration The measured values are stored in the SA cylinder In the self calibration the compensating value is updated using the value in the SA cylinder 2 Compensating open loop gain Torque constant value of the VCM has a dispersion for each drive and varies depending on the cylinder that the head is positioned To realize the high speed seek operation the value that compensates torque consta...

Page 62: ...ommand processing during self calibration This enables the host to execute the command without waiting for a long time even when the disk drive is performing self calibration The command execution wait time is about maximum 72 ms When the error rate of data reading writing or seeking becomes lower than the specified value self calibration is performed to maintain disk drive stability If the disk d...

Page 63: ...ial I O In the event of any abnormalities including a head short circuit or head open circuit the write unsafe signal is generated so that abnormal write does not occur 4 6 2 Write circuit The write data is output from the hard disk controller HDC with the NRZ data format and sent to the encoder circuit in the RDC The NRZ write data is converted to RLL Run Length Limited code data by the encoder c...

Page 64: ...he AGC amplifier output is maintained at a constant level even when the head output fluctuates due to the head characteristics or outer inner head positions 2 Programmable filter circuit The programmable filter circuit has a low pass filter function that eliminates unnecessary high frequency noise component and a high frequency boost up function that equalizes the waveform of the read signal Cut o...

Page 65: ...ing to the survivor path sequence 6 ENDEC This circuit converts the read data into the NRZ data 4 6 4 Digital PLL circuit The drive uses constant density recording to increase total capacity This is different from the conventional method of recording data with a fixed data transfer rate at all data area In the constant density recording method data area is divided into zones by radius and the data...

Page 66: ...is the block diagram of the servo control circuit The following describes the functions of the blocks Head Spindle motor CSR VCM Position Sense VCM current CSR Current Sense Resister VCM Voice Coil Motor 1 MPU 2 Servo burst capture 3 DAC 4 SVC Power Amp 5 Spindle motor control 6 Driver 7 MPU core Figure 4 6 Block diagram of servo control circuit 1 Microprocessor unit MPU The MPU executes startup o...

Page 67: ... and index information The servo signals do A D convert by Fourier demodulator in the servo burst capture circuit At that time the AGC circuit is in hold mode The A D converted data is recognized by the MPU as position information with A B and C D processed 3 D A converter DAC The control program calculates the specified data value digital value of the VCM drive current and the value is converted ...

Page 68: ... 1 Inner guard band IGB This area is located inside the user area and the rotational speed of the VCM can be controlled on this cylinder area for head moving 2 Data area This area is used as the user data area and the SA cylinder 3 Outer guard band OGB This area is located at outer position of the user data area and the rotational speed of the spindle can be controlled on this cylinder area for he...

Page 69: ... W R Recovery Servo Mark Gray Code W R Recovery Servo Mark Gray Code Erase Servo A Erase Servo A Servo B Erase Servo B Erase Servo C Erase Servo C Erase Servo D Erase PAD CYLn 1 CYLn CYLn 1 n even number Diameter direction Circumference Direction Erase DC erase area OGB Data area IGB expand Servo frame 124 servo frames per revolution ...

Page 70: ...rvo frame format 1 Write read recovery This area is used to absorb the write read transient and to stabilize the AGC 2 Servo mark This area generates a timing for demodulating the gray code and position demodulating the servo A to D by detecting the servo mark 3 Gray code including sector address bits This area is used as cylinder address The data in this area is converted into the binary data by ...

Page 71: ...speed d If the head is stopped at the reference cylinder from there Track following control starts 2 Seek operation Upon a data read write request from the host the MPU confirms the necessity of access to the disk If a read write instruction is issued the MPU seeks the desired track The MPU feeds the VCM current via the D A converter and power amplifier to move the head The MPU calculates the diff...

Page 72: ...hing signal is generated and the phase of the current flowed in the motor is changed in the order of V phase to U phase W phase to U phase W phase to V phase U phase to V phase U phase to W phase and V phase to W phase after that repeating this order d During phase switching the spindle motor starts rotating in low speed and generates a counter electromotive force The SVC detects this counter elec...

Page 73: ...harging or discharging the charge pump for the different time For example when the actual rotational speed is 4 000 rpm the time for one revolution is 15 000 ms And the time for one revolution at 4 200 rpm is 14 286 ms Therefore the MPU charges the charge pump for 0 714 ms k k constant value This makes the flowed current into the motor higher and the rotational speed up When the actual rotational ...

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Page 75: ... 1 CHAPTER 5 Interface 5 1 Physical Interface 5 2 Logical Interface 5 3 Host Commands 5 4 Command Protocol 5 5 Power on and COMRESET This chapter gives details about the interface and the interface commands and timings ...

Page 76: ...nt end Device analog front end GND Figure 5 1 Interface signals An explanation of each signal is provided below TX TX These signals are the outbound high speed differential signals that are connected to the serial ATA cable RX RX These signals are the inbound high speed differential signals that are connected to the serial ATA cable TxData Serially encoded 10b data attached to the high speed seria...

Page 77: ...r that indicates the COMWAKE out of band signal is being detected COMRESET COMINIT Host Signal from the out of band detector that indicates the COMINIT out of band signal is being detected Device Signal from the out of band detector that indicates the COMRESET out of band signal is being detected 5VDC GND 5VDC 5 V power supply to the disk drive GND Ground signal for each signal ...

Page 78: ...f band signaling During OOB signaling transmissions the differential and common mode levels of the signal lines shall comply with the same electrical specifications as for in band data transmission specified as follows COMRESET COMINIT 106 7 ns 320 ns COMWAKE 106 7 ns 106 7 ns ...

Page 79: ... management request to partial This primitive is sent continuously until PMACK or PMNAK is received When PMACK is received current node host or device will stop PMREQ_P and enters the Partial power management state PMREQ_S Power management request to Slumber This primitive is sent continuously until PMACK or PMNAK is received When PMACK is received current node host or device will stop PMREQ_S and...

Page 80: ... amplitude of Vcm ac Tsettle CM 10 ns Maximum time for common mode transients to and from the idle bus condition Vdiff tx 500 400 600 mVp p 250 mV differential nominal Measured at Serial ATA connector on transmit side Vdiff rx 400 325 600 mVp p 200 mV differential nominal Measured at Serial ATA connector on receive side Tx pair differential impedance 100 85 115 Ohm As seen by a differential TDR wi...

Page 81: ...ominal value architecture specific Squelch detector threshold 100 50 200 mVp p Minimum differential signal amplitude COMRESET C OMINIT detector off threshold 175 525 ns Detector shall reject all bursts with spacings outside this spec COMRESET C OMINIT detector on threshold 320 304 336 ns Detector shall detect all bursts with spacings meeting this period COMRESET C OMINIT transmit spacing 320 0 310...

Page 82: ...harge 2nd mate 1 P4 Gnd 1st mate P5 Gnd 2nd mate P6 Gnd 2nd mate P7 V5 5 V power pre charge 2nd mate P8 V5 5 V power P9 V5 5 V power P10 Gnd 2nd mate P11 Reserved The pin corresponding to P11 in the backplane receptacle connector is also reserved The corresponding pin to be mated with P11 in the power cable receptacle connector shall be grounded P12 Gnd 1st mate P13 V12 12 V power pre charge 2nd m...

Page 83: ... within the host or device and between layers at the same level that link the host and device Figure 5 2 is a conceptual diagram of the communication layers Host Software control Buffer Memory DMA engine s Host located layers Physical Layer Link Layer Transport Layer Device located layers Physical Layer Link Layer Transport Layer Device Software control Buffer memory DMA engine s Application layer...

Page 84: ...transfer requests between the host system and device Encodes serial data as 10 or 8 bit data then converts it into DWORD data Inserts auxiliary signals SOF CRC and EOF deletes auxiliary signals and communicates with the transport and physical layers Transport layer Exchanges data in communication with the link layer and builds the frame information structure FIS Contains a Shadow Block Register Re...

Page 85: ...p Sector Count Sector Count exp Sector Count Sector Number exp Sector Number Sector Number exp Sector Number Cylinder Low exp Cylinder Low Cylinder Low exp Cylinder Low Cylinder High exp Cylinder High Cylinder High exp Cylinder High Device Head Status Command Control Block registers Alternate Status Device Control Note Each of the Sector Count Sector Number Cylinder Low and Cylinder High fields ha...

Page 86: ...ce Bidirectional Set Device Bits Device to Host BIST Active Bidirectional PIO Setup Device to Host Data Host to Device or Device to Host Bidirectional 5 2 3 2 Register Host to Device The Register Host to Device FIS has the following layout 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0 Features Command C R R Reserved 0 FIS Type 27h 0 Dev...

Page 87: ...BA High LBA Mid LBA Low 1 Reserved 0 LBA High exp LBA Mid exp LBA Low exp 0 2 Reserved 0 Reserved 0 Sector Count exp Sector Count 3 Reserved 0 Reserved 0 Reserved 0 Reserved 0 4 Figure 5 4 Register Device to Host FIS layout The Register Device to Host FIS is used when information concerning the Shadow Register Block in the host adapter is updated This FIS indicates that the device has completed a ...

Page 88: ...h 0 0 TAG 1 0 2 Reserved 0 3 DMA Buffer Offset 4 DMA Transfer Count 5 Reserved 0 6 Figure 5 6 DMA Setup Device to Host or Host to Device FIS layout The DMA Setup Device to Host or Host to Device FIS communicates the start of a first party DMA access to the host system This FIS is used to request the host system or device to set up the DMA controller before the start of a DMA data transfer A Auto A...

Page 89: ...o Loop Back mode This FIS can be sent by either the host system or device The following combinations of pattern definitions are supported Table 5 4 BIST combinations T A S L F P V SC Reg Contents 1 1 09h SATA Phy Analog Loopback Mode 1 10h Far End Retimed Loopback Mode 1 1 C0h No ALIGN Transmit_only Mode Scramble ON 1 1 1 1 E0h No ALIGN Transmit_only Mode Scramble OFF 1 1 1 C4h No ALIGN Transmit_o...

Page 90: ...g layout 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0 Reserved 0 Reserved 0 R R R Reserved 0 FIS Type 46h 0 N Dwords of data 1 to 2048 Dwords n Figure 5 8 Data FIS Bidirectional layout The Data FIS is used for data transfers between the host system and device ...

Page 91: ...ing the write process Bit 5 Unused Bit 4 ID Not Found IDNF This bit indicates an error except for bad sector uncorrectable error and SB not found Or SATA Frame Error Write SFRW This bit indicates that a SATA communication error has been encountered during the write process In this case bit4 and bit2 are set both Bit 3 SATA Frame Error Read SF RR This bit indicates that a SATA communication error h...

Page 92: ...ost system That is this field indicates the number of remaining sectors that the data has not been transferred due to the error However as of the last sector of PIO transfer SC 1 indicates the normal completion The contents of this field also have other definitions Refer to 5 4 4 Sector Number Field exp The contents of this field indicates the starting sector number for the subsequent command The ...

Page 93: ...ad Field The contents of this field indicate the device and the head number When executing INITIALIZE DEVICE PARAMETERS command the contents of this field defines the number of heads minus 1 a maximum head No Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 X L X X HS3 HS2 HS1 HS0 Bit 7 Unused Bit 6 L 0 for CHS mode and 1 for LBA mode Bit 5 Unused Bit 4 Unused Bit 3 HS3 CHS mode head address 3 2 3 ...

Page 94: ...Bit 6 Device Ready DRDY bit This bit indicates that the device is capable to respond to a command The IDD checks its status when it receives a command If an error is detected not ready state the IDD clears this bit to 0 This is cleared to 0 at power on and it is cleared until the rotational speed of the spindle motor reaches the steady speed Bit 5 Device Write Fault DF bit This bit indicates that ...

Page 95: ...e slave device is not required to execute the DASP handshake 11 E_Status Field This field is in the PIO Setup FIS The field contents are the same as those described in 8 Status Field However the values in the Status field are those before a PIO data transfer and the values in the E_Status field are those when a PIO data transfer is completed 12 DMA Buffer Offset Field This field is in the DMA Setu...

Page 96: ...d parameters Table 5 5 lists the supported commands command code and the related fields to be written necessary parameters at command execution Table 5 5 Command code and parameters 1 3 COMMAND CODE Bit PARAMETER USED COMMAND NAME 7 6 5 4 3 2 1 0 FR SC SN CY DH RECALIBRATE 0 0 0 1 X X X X N N N N D READ SECTOR S 0 0 1 0 0 0 0 R N Y Y Y Y READ LONG 0 0 1 0 0 0 1 R N Y Y Y Y WRITE SECTOR S 0 0 1 1 0...

Page 97: ...AD BUFFER 1 1 1 0 0 1 0 0 N N N N D FLUSH CACHE 1 1 1 0 0 1 1 1 N N N N D WRITE BUFFER 1 1 1 0 1 0 0 0 N N N N D IDENTIFY DEVICE 1 1 1 0 1 1 0 0 N N N N D IDENTIFY DEVICE DMA 1 1 1 0 1 1 1 0 N N N N D SET FEATURES 1 1 1 0 1 1 1 1 Y N N N D SECURITY SET PASSWORD 1 1 1 1 0 0 0 1 N N N N D SECURITY UNLOCK 1 1 1 1 0 0 1 0 N N N N D SECURITY ERASE PREPARE 1 1 1 1 0 0 1 1 N N N N D SECURITY ERASE UNIT 1...

Page 98: ... 1 0 N Y Y Y D FLUSH CACHE EXT 1 1 1 0 1 0 1 0 N N N N D WRITE MULTIPLE FUA EXT 1 1 0 0 1 1 1 0 N Y Y Y D WRITE DMA FUA EXT 0 0 1 1 1 1 0 1 N Y Y Y D READ FP DMA QUEUED 0 1 1 0 0 0 0 0 Y Y Y Y D WRITE FP DMA QUEUED 0 1 1 0 0 0 0 1 Y Y Y Y D CY cylinder field DH device head field FR features field SC sector count field SN sector number field R Retry at error 1 Without retry 0 With retry Y Necessary...

Page 99: ...der address LSB LBA 15 8 SN EXP LBA 31 24 SN EXP LBA 31 24 SN Start sector No LBA 7 0 SN End sector No LBA 7 0 SC EXP Transfer sector count 15 8 SC EXP X 00 SC Transfer sector count 7 0 SC X 00 FR EXP xx FR xx ER Error information CH EXP Cylinder High Field EXP CL EXP Cylinder Low Field EXP CM Command Field DH Device Head Field ER Error Field FR EXP Features Field EXP L LBA Logical Block Address s...

Page 100: ...reporting conditions 1 An error was detected during head positioning ST 51h ER 02h 2 A SATA communication error occurred ST 51h ER 14h At command issuance Shadow Block Registers setting contents CM 0 0 0 1 x x x x DH x x x x xx CH CL SN SC FR xx xx xx xx xx At command completion Shadow Block Registers contents to be read ST Status information DH x x x x xx CH CL SN SC ER xx xx xx xx Error informat...

Page 101: ...hadow block registers contain the cylinder head and sector addresses in the CHS mode or logical block address in the LBA mode of the last sector read If an unrecoverable disk read error occurs in a sector the read operation is terminated at the sector where the error occurred Shadow block registers contain the cylinder the head and the sector addresses of the sector in the CHS mode or the logical ...

Page 102: ...SB LBA Start sector No LBA LSB Transfer sector count xx R Retry At command completion Shadow Block Registers contents to be read ST Status information DH x L x x HDNo LBA CH CL SN SC ER End cylinder No MSB LBA End cylinder No LSB LBA End sector No LBA LSB 01 1 Error information 1 If the command is terminated due to an error the remaining number of sectors of which data was not transferred ...

Page 103: ...ting conditions 1 A specified address exceeds the range where read operations are allowed ST 51h ER 10h 2 A value other than 01h is specified in the SC field ST 51h ER 04h 3 The sync byte indicating the beginning of a sector was not found ST 51h ER 01h 4 A SATA communication error occurred ST 51h ER 0Ch 5 An error other than the above errors occurred ST 51h ER 04h At command issuance Shadow Block ...

Page 104: ...and sector addresses of the last sector written If an disk error occurs during multiple sector write operation the write operation is terminated at the sector where the error occurred Shadow block registers contain the cylinder the head the sector addresses in the CHS mode or the logical block address in the LBA mode of the sector where the error occurred Error reporting conditions 1 A specified a...

Page 105: ...A Start sector No LBA LSB Transfer sector count xx R Retry At command completion Shadow Block Registers contents to be read ST Status information DH x L x x HDNo LBA CH CL SN SC ER End cylinder No MSB LBA End cylinder No LSB LBA End sector No LBA LSB 00 1 Error information 1 If the command was terminated because of an error the number of sectors for which data has not been written is set in this f...

Page 106: ...ta becomes an uncorrectable error for subsequent READ command Error reporting conditions 1 A specified address exceeds the range where write operations are allowed after a transfer of dummy data ST 51h ER 10h 2 The range where write operations are allowed will be exceeded by an address during a write operation after a transfer of dummy data ST 51h ER 10h 3 A write fault was detected when the write...

Page 107: ... 0 0 1 R DH x L x x HD No LBA CH CL SN SC FR Cylinder No MSB LBA Cylinder No LSB LBA Sector No LBA LSB 01 xx At command completion Shadow Block Registers contents to be read ST Status information DH x L x x HD No LBA CH CL SN SC ER Cylinder No MSB LBA Cylinder No LSB LBA Sector No LBA LSB xx Error information ...

Page 108: ...eration after a transfer of dummy data ST 51h ER 10h 3 A write fault was detected when the write cache was disabled ST 71h ER 10h 4 While the write cache is enabled if the status indicating a completed transfer STS 50h is returned and a data write operation failed because a write fault was detected during the data write operation Abort will be returned for all subsequent ATA commands ST 71h ER 04h...

Page 109: ...Status information DH x L x x HDNo LBA CH CL SN SC ER Start cylinder No MSB LBA Start cylinder No LSB LBA Start sector No LBA LSB 00 1 Error information 1 If the command is terminated because of an error the number of remaining sectors for which data has not been written or verified is set in this register ...

Page 110: ...lock address in the LBA mode of the sector where the error occurred The Sector Count field indicates the number of sectors that have not been verified Error reporting conditions 1 A specified address exceeds the range where read operations are allowed ST 51h ER 10h 2 The range where read operations are allowed will be exceeded by an address during a read operation ST 51h ER 10h 3 An uncorrectable ...

Page 111: ... read ST Status information DH x L x x HDNo LBA CH CL SN SC ER Start cylinder No MSB LBA Start cylinder No LSB LBA Start sector No LBA LSB 00 1 Error information 1 If the command is terminated due to an error the remaining number of sectors of which data was not transferred is set in this register ...

Page 112: ...address exceeds the range where the head can be positioned ST 51h ER 10h 2 Head positioning is not possible because an error occurred ST 51h ER 10h 3 A SATA communication error occurred ST 51h ER 14h At command issuance Shadow Block Registers setting contents CM 0 1 1 1 x x x x DH x L x x HD No LBA CH CL SN SC FR Start cylinder No MSB LBA Start cylinder No LSB LBA Start sector No LBA LSB xx xx At ...

Page 113: ...completed No error detected HDC diagnostic error Data buffer diagnostic error Memory diagnostic error Reading the system area is abnormal Calibration abnormal Note The device responds to this command with the result of power on diagnostic test Error reporting conditions 1 A SATA communication error occurred ST 51h ER 14h At command issuance Shadow Block Registers setting contents CM 1 0 0 1 0 0 0 ...

Page 114: ...ained even after soft reset issuance or power save operation regardless of the setting of disabling the reverting to default setting however the COMRESET is not retained The operation is always performed in CHS mode with the command ignoring any setting of LBA mode Error reporting conditions 1 00h is specified in the SC field ST 51h ER 04h 2 A SATA communication error occurred ST 51h ER 14h At com...

Page 115: ...the microcode rewriting according to Subcommand code Rewriting is also possible simultaneously with the data transfer Refer to Table 5 7 In the data transfer of Subcommand code 01h transfer by which data is divided into multiple times is possible Refer to Table 5 8 After the designation of rewriting by Subcommand code 07h reactivates in the device for the update of the rewriting microcode of the m...

Page 116: ... 0000h FR 07h Transfer of 384 KB Firmware rewriting execution Transfer example 3 1 CMD 92h SN SC 0300h FR 07h Transfer of 384 KB and Firmware rewriting execution Transfer example 4 1 CMD 92h SN SC 0100h FR 0lh 2 CMD 92h SN SC 0100h FR 0lh 3 CMD 92h SN SC 0100h FR 07h Transfer of 127 KB from the first Transfer from 128 to 255 KB Transfer from 256 to 383 KB and Firmware rewriting execution The Abort...

Page 117: ...s command does not support the APS timer function Error reporting conditions 1 A SATA communication error occurred ST 51h ER 14h At command issuance Shadow Block Registers setting contents CM X 94 or X E0 DH x x x x xx CH CL SN SC FR xx xx xx xx xx At command completion Shadow Block Registers contents to be read ST Status information DH x x x x xx CH CL SN SC ER xx xx xx xx Error information ...

Page 118: ...nd does not support the APS timer function Error reporting conditions 1 A SATA communication error occurred ST 51h ER 14h At command issuance Shadow Block Registers setting contents CM X 95 or X E1 DH x x x x xx CH CL SN SC FR xx xx xx xx xx At command completion Shadow Block Registers contents to be read ST Status information DH x x x x xx CH CL SN SC ER xx xx xx xx Error information ...

Page 119: ...vice automatically enters Standby mode If the Sector Count field value is 0 the APS timer is disabled when the command is received Under the standby mode the spindle motor is stopped Thus when the command involving a seek such as READ SECTOR s command is received the device processes the command after driving the spindle motor Error reporting conditions 1 A SATA communication error occurred ST 51h...

Page 120: ...e enters standby mode The APS timer is set to prohibition if the Sector Count field s value was 0 when device has received this command The period of timer count is set depending on the value of the Sector Count register as shown below Sector Count field value Point of timer 0 X 00 Timeout disabled 1 to 240 X 01 to X F0 Value 5 seconds 241 to 251 X F1 to X FB Value 240 30 min 252 X FC 21 minutes 2...

Page 121: ...5 3 Host Commands C141 E203 01EN 5 47 At command completion Shadow Block Registers contents to be read ST Status information DH x x x x xx CH CL SN SC ER xx xx xx xx Error information ...

Page 122: ...e device reports the status to the host system Power save mode Sector Count field During moving to Standby mode Standby mode X 00 Idle mode X FF Active mode X FF Error reporting conditions 1 A SATA communication error occurred ST 51h ER 14h At command issuance Shadow Block Registers setting contents CM X 98 or X E5 DH x x x x xx CH CL SN SC FR xx xx xx xx xx At command completion Shadow Block Regi...

Page 123: ...tered the sleep mode In the sleep mode the spindle motor is stopped The only way to release the device from sleep mode is to execute a software or COMRESET Error reporting conditions 1 A SATA communication error occurred ST 51h ER 14h At command issuance Shadow Block Registers setting contents CM X 99 or X E6 DH x x x x xx CH CL SN SC FR xx xx xx xx xx At command completion Shadow Block Registers ...

Page 124: ... 4Fh in the Cylinder Low field and C2h in the Cylinder High field If the key values are incorrect the Aborted Command error is issued If the failure prediction function is disabled the device returns the Aborted Command error to subcommands other than those of the SMART Enable Operations with the Features field set to D8h If the failure prediction function is enabled the device collects and update...

Page 125: ... 15 minutes has elapsed since the last time that attributes were saved then the attributes are saved However if the automatic attribute save function is disabled the attributes are not saved Upon receiving this subcommand a device enables or disables the automatic attribute save function and transfers the RegDH then reports the status X D3 SMART SAVE ATTRIBUTE VALUES When the device receives this ...

Page 126: ...e SMART selective self test log data format X D6 SMART WRITE LOG A device which receives this sub command when it has prepared to receive data from the host computer it transfers the PIOSU Next it receives data from the host computer and writes the specified log sector in the Sector Number Field SN SC Log sector 09h 01h SMART selective self test log 80h 9Fh 01h 10h Host vendor log The host can wri...

Page 127: ... This setting is preserved whether the drive s power is switched on or off If 24 hours have passed since the power was switched on or since the last time that off line data were collected off line data collection is performed without relation to any command from the host computer The host must regularly issue the SMART READ DATA subcommand Features field D0h SMART SAVE ATTRIBUTE VALUES subcommand ...

Page 128: ...prediction status C2h 2Ch Key failure prediction status 4Fh F4h xx xx Error information The attribute value information is 512 byte data the format of this data is shown the following Table 5 10 The host can access this data using the SMART READ DATE subcommand Features field D0h The guarantee failure threshold value data is 512 byte data the format of this data is shown the following Table 5 11 T...

Page 129: ...erved 16F Off line data collection capability 170 171 Trouble prediction capability flag 172 Error logging capability 173 Self test error detection point 174 Simple self test Quick Test execution time min 175 Comprehensive self test Comprehensive Test execution time min 176 Conveyance self test execution time min 177 to 181 Reserved 182 to 1FE Vendor unique 1FF Check sum Table 5 11 Format of guara...

Page 130: ...e ID is defined as follows Attribute ID Attribute name 0 Indicates unused attribute data 1 Read Error Rate 2 Throughput Performance 3 Spin Up Time 4 Start Stop Count 5 Reallocated Sector Count 7 Seek Error Rate 8 Seek Time Performance 9 Power On Hours Count 10 Spin Retry Count 12 Drive Power Cycle Count 192 Emergency Retract Cycle Count 193 Load Unload Cycle Count 194 HDA Temperature 195 ECC On th...

Page 131: ...ted saved even if SMART is disabled 6 to 15 Reserve bit Current attribute value It indicates the normalized value of the original attribute value The value deviates in a range of 01h to 64h range of 01h to C8h for the Ultra ATA CRC error rate and communication error rate It indicates that the closer the value is to 01h the higher the possibility of a failure The host compares the attribute value w...

Page 132: ...ed Self test execution status Table 5 13 Self test execution status Bit Meaning 0 to 3 Remainder of the self test is indicated as a percentage in a range of 0h to 9h corresponding to 0 to 90 4 to 7 Self test execution status 0h Self test has ended successfully or self test has not been executed 1h Self test is suspended by the host 2h Self test is interrupted by a soft COMRESET from the host 3h Se...

Page 133: ...d Scanning Technology is supported 4 If this bit is 1 it indicates that the SMART Self test function is supported 5 If this bit is 1 it indicates that the SMART Conveyance Self test is supported 6 If this bit is 1 it indicates that the SMART Selective Self test is supported 7 Reserved bits Failure prediction capability flag Table 5 15 Failure prediction capability flag Bit Meaning 0 If this bit is...

Page 134: ...ed 100 Number of sector 101 Address 80h Reserved 102 to 13F Address 81h to Address 9Fh 102 and 13F are both the same format as 100 101 140 to 1FF Reserved SMART error logging If the device detects an unrecoverable error during execution of a command received from the host the device registers the error information in the SMART Summary Error Log see Table 5 18 and the SMART Comprehensive Error Log ...

Page 135: ...value 33 Features field value 34 Sector Count field value 35 Sector Number field value 36 Cylinder Low field value 37 Cylinder High field value 38 Drive Head field value 39 Command field value 3A to 3D Command data structure Elapsed time after the power on sequence unit ms 3E Reserved 3F Error field value 40 Sector Count field value 41 Sector Number field value 42 Cylinder Low field value 43 Cylin...

Page 136: ...cates the status register when an error occurs Total number of drive errors Indicates total number of errors registered in the error log Checksum Two s complement of the lower byte obtained by adding 511 byte data one byte at a time from the beginning Status Bits 0 to 3 Indicates the drive status when received error commands according to the following table Bits 4 to 7 Vendor unique Status Meaning...

Page 137: ...Data Structure 5n 4 16A 1C3 5 th Error Log Data Structure5 Error Log Data Structure 5n 5 1C4 1C5 Total number of drive errors Reserved 1C6 1FE Reserved Reserved 1FF Check sum Check sum n indicates sector number in the Error Log The first sector is 0 SMART Self Test The host computer can issue the SMART Execute Off line Immediate sub command Features field D4h and cause the device to execute a self...

Page 138: ... unique 1A to 1F9 Self test log 2 to 21 Each log data format is the same as that in byte 02 to 19 1FA 1FB Vendor unique 1FC Self test index 1FD 1FE Reserved 1FF Check sum Self test number Indicates the type of self test executed Self test execution status Same as byte 16Bh of the attribute value Self test index If this is 00h it indicates the status where the self test has never been executed Chec...

Page 139: ...Reserved 152h 1EBh Vender Unique 1Ech 1F3h Current LBA under test 1F4h 1F5h Current Span under test 1F6h 1F7h Feature Flags 1F8h Offline Execution Flag 1F9h Selective Offline Scan Number 1FAh 1FBh Vender Unique Reserved 1FCh 1FDh Selective Self test pending time min 1FEh 1FFh Checksum Test Span Selective self test log provides for the definition of up to five test spans If the starting and ending ...

Page 140: ...ve test 2 Vendor specific unused 3 When set to one off line scan after selective test is pending 4 When set to one off line scan after selective test is active 5 15 Reserved Bit l shall be written by the host and returned unmodified by the device Bit 3 4 shall be written as zeros by the host and the device shall modify them as the test progress Selective Self test pending time min The selective se...

Page 141: ...es field an aborted command error is posted FR field Command C0h DEVICE CONFIGURATION RESTORE C1h DEVICE CONFIGURATION FREEZE C2h DEVICE CONFIGURATION IDENTIFY C3h DEVICE CONFIGURATION SET 00h BFh C4h FFh Reserved At command issuance Shadow Block Registers setting contents CM 1 0 1 1 0 0 0 1 DH x x x x xx CH CL SN SC xx xx xx xx FR C0h C1h C2h C3h At command completion Shadow Block Registers conte...

Page 142: ...and F9h 37h has been specified with a value in the Host Protected Area ST 51h ER 04h 4 A SATA communication error occurred ST 51h ER 14h DEVICE CONFIGURATION FREEZE LOCK Features Field C1h The DEVICE CONFIGURATION FREEZE LOCK command prevents accidental modification of the Device Configuration Overlay settings After successful execution of a DEVICE CONFIGURATION FREEZE LOCK command all DEVICE CONF...

Page 143: ...vice is described in Table 5 23 As a result to the limitation of the function by the DEVICE CONFIGURATION SET command is reflected in IDENTIFY information When the bits in these words are cleared the device no longer supports the indicated command mode or feature set If a bit is set in the overlay transmitted by the device that is not set in the overlay received from a DEVICE CONFIGURATION IDENTIF...

Page 144: ...ture set supported Reflected in IDENTIFY information WORD82 87 Bit 15 9 Reserved Bit 8 1 48 bit Addressing feature set supported Bit 7 1 Host Protected Area feature set supported Bit 6 1 Automatic acoustic management supported Bit 5 1 READ WRITE DMA QUEUED commands supported Bit 4 1 Power up in Standby feature set supported Bit 3 1 Security feature set supported Bit 2 1 SMART error log supported B...

Page 145: ...ber of sectors in the partial block to be transferred is n where n remainder of number of sectors block count If the READ MULTIPLE command is issued when the READ MULTIPLE command is disabled the device rejects the READ MULTIPLE command with an ABORTED COMMAND error If an uncorrectable disk read error occurs the read operation stops at the sector where the error occurred even if the read operation...

Page 146: ... where read operations are allowed ST 51h ER 10h 2 The range where read operations are allowed will be exceeded by an address during a read operation ST 51h ER 10h 3 An uncorrectable disk read error occurred ST 51h ER 40h 4 The sync byte indicating the beginning of a sector was not found ST 51h ER 01h 5 The READ MULTIPLE command is disabled ST 51h ER 04h 6 A SATA communication error occurred ST 51...

Page 147: ... count xx At command completion Shadow Block Registers contents to be read ST Status information DH x L x x HDNo LBA CH CL SN SC ER End cylinder No MSB LBA End cylinder No LSB LBA End sector No LBA LSB 1 Error information 1 If the command is completed normally the number of remaining sectors is set in this field If the command is terminated because of an error the number of sectors for which data ...

Page 148: ... after a disk write operation has been attempted for the transferred blocks and partial block The write operation stops at the sector where the error occurred even if the write operation has not reached the end of the block At this time the number of remaining sectors the error sector and subsequent sectors and either cylinder head and sector addresses of the error sector CHS mode or the logical b...

Page 149: ...tart sector No LBA LSB Transfer sector count xx R Retry At command completion Shadow Block Registers contents to be read ST Status information DH x L x x HDNo LBA CH CL SN SC ER Start cylinder No MSB LBA Start cylinder No LSB LBA Start sector No LBA LSB 00 1 Error information 1 If the command was terminated because of an error the number of sectors for which data has not been written is set in thi...

Page 150: ...is then enabled If the value of the Sector Count register is not a supported block count an ABORTED COMMAND error is posted and the READ MULTIPLE and WRITE MULTIPLE commands are disabled If the contents of the Sector Count field is 0 when the SET MULTIPLE MODE command is issued the READ MULTIPLE and WRITE MULTIPLE commands are disabled When the SET MULTIPLE MODE command operation is completed the ...

Page 151: ...5 3 Host Commands C141 E203 01EN 5 77 At command completion Shadow Block Registers contents to be read ST Status information DH x x x x xx CH CL SN SC ER xx xx xx Sector count block Error information ...

Page 152: ...ctor where the error was detected is transferred The device notifies the host of the status by sending the Register DH FIS At this time the number of remaining sectors including the sector where the error was detected and either cylinder head and sector addresses CHS mode or the logical block address LBA mode of the sector where the error was detected are stored in the Shadow Block Register The ho...

Page 153: ...Start sector No LBA LSB Transfer sector count xx At command completion Shadow Block Registers contents to be read ST Status information DH x L x x HDNo LBA CH CL SN SC ER Start cylinder No MSB LBA Start cylinder No LSB LBA Start sector No LBA LSB 00 1 Error information 1 If the command is terminated due to an error the remaining number of sectors of which data was not transferred is set in this re...

Page 154: ...or where the error was detected and either cylinder head and sector addresses CHS mode or the logical block address LBA mode of the sector where the error was detected are stored in the Shadow Block Register A host system can select the following transfer mode using the SET FEATURES command however the transfer speed does not change Multiword DMA transfer mode 0 to 2 Ultra DMA transfer mode 0 to 5...

Page 155: ...BA Start sector No LBA LSB Transfer sector count xx At command completion Shadow Block Registers contents to be read ST Status information DH x L x x HDNo LBA CH CL SN SC ER Start cylinder No MSB LBA Start cylinder No LSB LBA Start sector No LBA LSB 00 1 Error information 1 If the command was terminated because of an error the number of sectors for which data has not been written is set in this fi...

Page 156: ...ter that the host system can read up to 512 bytes of data from the buffer Error reporting conditions 1 A SATA communication error occurred ST 51h ER 0Ch At command issuance Shadow Block Registers setting contents CM 1 1 1 0 0 1 0 0 DH x x x x xx CH CL SN SC FR xx xx xx xx xx At command completion Shadow Block Registers contents to be read ST Status information DH x x x x xx CH CL SN SC ER xx xx xx...

Page 157: ...ta are to be written In case a non recoverable disk write error has occurred while the data is being read the error generation address is put into the shadow block register before ending the command This error sector is deleted from the write cache data Error reporting conditions 1 A SATA communication error occurred ST 51h ER 14h At command issuance Shadow Block Registers setting contents CM 1 1 ...

Page 158: ...bytes of data is transferred from the host and the device writes the data to the buffer then reports the status Error reporting conditions 1 A SATA communication error occurred ST 51h ER 14h At command issuance Shadow Block Registers setting contents CM 1 1 1 0 1 0 0 0 DH x x x x xx CH CL SN SC FR xx xx xx xx xx At command completion Shadow Block Registers contents to be read ST Status information...

Page 159: ... the host then sends the parameter information including a 512 byte date Table 5 24 shows the values of the parameter words and the meaning in the buffer Error reporting conditions 1 A SATA communication error occurred ST 51h ER 0Ch At command issuance Shadow Block Registers setting contents CM 1 1 1 0 1 1 0 0 DH x x x x xx CH CL SN SC FR xx xx xx xx xx At command completion Shadow Block Registers...

Page 160: ...he Identify Device command Error reporting conditions 1 A SATA communication error occurred ST 51h ER 0Ch At command issuance Shadow Block Registers setting contents CM 1 1 1 0 1 1 1 0 DH x x x x xx CH CL SN SC FR xx xx xx xx xx t command completion Shadow Block Registers contents to be read ST Status information DH x x x x xx CH CL SN SC ER xx xx xx xx Error information ...

Page 161: ...3 26 Firmware revision ASCII code 8 characters left 27 46 Set by a device Model name ASCII code 40 characters left 47 X 8010 Maximum number of sectors per block on READ WRITE MULTIPLE command 48 X 0000 Reserved 49 X 2F00 Capabilities 4 50 X 4000 Capabilities 5 51 X 0200 PIO data transfer mode 6 52 X 0200 Reserved 53 X 0007 Enable disable setting of words 54 58 and 64 70 88 7 54 Variable Number of ...

Page 162: ...F8 Major version number 11 81 X 001A Minor version number 82 X 346B Support of command sets 12 83 X 7F09 Support of command sets 13 84 X 60xx Support of command sets function 14 85 15 Valid of command sets function 15 86 16 Valid of command sets function 16 87 17 Default of command sets function 17 88 X xx3F Ultra DMA transfer mode 18 89 Set by a device Security Erase Unit execution time 1 LSB 2 m...

Page 163: ...15 ATA device 0 ATAPI device 1 Bit 14 8 Undefined Bit 7 Removable disk drive 1 Bit 6 Fixed drive 1 Bit 5 3 Undefined Bit 2 IDENTIFY DEVICE Valid 0 Bit 1 0 Reserved 2 Word 1 3 6 60 61 Word MHT2080BH MHT2060BH MHT2040BH 1 X 3FFF X 3FFF X 3FFF 3 X 10 X 10 X 10 6 X 3F X 3F X 3F 60 61 X 950F8B0 X 6FC7C80 X 4A85300 3 Status of the Word 2 Identify information is shown as follows 37C8h The device requires...

Page 164: ... timer value ATA spec is 1 Bit 12 Reserved Bit 11 1 IORDY supported Bit 10 1 IORDY inhibition supported Bit 9 1 DMA supported Bit 8 1 LBA supported Bit 7 0 Undefined 5 Word 50 Device capability Bit 15 0 Bit 14 1 Bit 13 to 1 Reserved Bit 0 Standby timer value 1 Standby timer value of the device is the smallest value 6 Word 51 PIO data transfer mode Bit 15 8 PIO data transfer mode X 02 PIO mode 2 su...

Page 165: ...8 1 multiword DMA mode 0 is selected Bit 7 3 Reserved Bit 2 1 Multiword DMA mode 2 1 and 0 supported Bit 1 0 1 Bit 1 1 Multiword DMA mode 1 and 0 supported Bit 0 1 Bit 0 1 Mode 0 10 Word 64 Advance PIO transfer mode support status Bit 15 8 Reserved Bit 7 0 Advance PIO transfer mode Bit 1 1 Mode 4 supported Bit 0 1 Mode 3 supported 11 WORD 75 X 001F 32 12 WORD 76 Bit15 10 Reserved Bit 9 1 Supports ...

Page 166: ...t 3 1 Enables the Power Management initiation function from Bit 2 1 Enables the Auto Activate optimization function in the DMA Setup FIS Bit 1 1 Enables the non zero buffer offset function in the DMA Setup FIS Bit 0 Reserved 15 WORD 80 Bit 15 8 Reserved Bit 7 1 ATA ATAPI 7 supported Bit 6 1 ATA ATAPI 6 supported Bit 5 1 ATA ATAPI 5 supported Bit 4 1 ATA ATAPI 4 supported Bit 3 1 ATA 3 supported Bi...

Page 167: ...Bit 14 1 Bit 13 1 Supports the FLUSH CACHE EXT command Bit 12 1 Supports the FLUSH CACHE command Bit 11 1 Supports the Device Configuration Overlay feature set Bit 10 1 48 bit LBA feature set Bit 9 1 Automatic Acoustic Management feature set Bit 8 1 Supports the SET MAX Security extending command Bit 7 Reserved Bit 6 1 When the power is turned on spin is started by the SET FEATURES sub command Bit...

Page 168: ...gging Option customizing 19 WORD 85 Bit 15 Undefined Bit 14 1 Supports the NOP command Bit 13 1 Supports the READ BUFFER command Bit 12 1 Supports the WRITE BUFFER command Bit 11 Undefined Bit 10 1 Supports the Host Protected Area function Bit 9 1 Supports the DEVICE RESET command Bit 8 1 Enables the SERVICE interrupt From the SET FEATURES command Bit 7 1 Enables the release interrupt From the SET...

Page 169: ...me definition as WORD 83 21 WORD 87 Bit 15 0 The device always returns the fixed value indicated on the left Bit 14 1 The device always returns the fixed value indicated on the left Bits 13 0 Same definition as WORD 84 22 WORD 88 Bit 15 14 Currently used Ultra DMA transfer mode Bit 13 1 Mode 5 is selected Bit 12 1 Mode 4 is selected Bit 11 1 Mode 3 is selected Bit 10 1 Mode 2 is selected Bit 9 1 M...

Page 170: ...isplayed 26 WORD 106 Bit 15 0 The device always returns the fixed value indicated on the left Bit 14 1 The device always returns the fixed value indicated on the left Bit13 1 Each device has several logical sectors per physical sector Bit12 1 Logical sector of the device is grater than 256 Words Bit11 4 Reserved Bit3 0 Logical sector size per physical sector 27 WORD 128 Bit 15 9 Reserved Bit 8 Sec...

Page 171: ... mode X 02 Enables the write cache function X 03 Set the data transfer mode 1 X 04 Enables the automatic reassign Note X 05 Enables the advanced power management function 2 X 06 Enables the Power Up In Standby function Note X 07 Spin up the Power Up In Standby status device Note X 10 Enables the Serial ATA function 3 X 33 Undefined Note X 42 Enables the Acoustic management function 4 X 54 Undefine...

Page 172: ...the command nothing is done At power on or after COMRESET the default mode is set as follows Write cashe function Enabled Transfer mode PIO Mode 4 Multiworld DMA Mode 2 Advanced power management function Enabled Mode 1 Acoustic management function State keeping Read cashe function Enabled Serial ATA function Prohibited Error reporting conditions 1 An undefined code is specified in the FR or SC fie...

Page 173: ...ports following values in the Sector Count field value If other value than below is specified an ABORTED COMMAND error is posted Note For a serial ATA device the setting of a data transfer mode is reflected in WORD 63 and 88 in IdentifyDevice information However the actual data transfer rate depends on the serial ATA signaling rate in WORD 76 in IdentifyDevice information Transfer mode Sector Coun...

Page 174: ... APM level when the drive does not receive any commands for a specific time The sequence in which the power management level shifts is from Active Idle to Low Power Idle to Standby The Mode 2 level requires the longest shifting time depending on the APM level settings The settings of the APM level revert to their default values Mode 1 when power on or a hardware reset occurs for the drive APM Leve...

Page 175: ...FIS for the first data sector after the WRITE FP DMA QUEUED command is issued 3 This specification is prohibited when power on While this function is enabled the device perform interface power save 4 Automatic Acoustic Management AAM The host writes to the Sector Count filed with the requested acoustic management level and executes this command with subcommand code 42h and then Automatic Acoustic ...

Page 176: ...assword 32 bytes 17 Master password version number 18 to 255 Reserved Table 5 27 Relationship between combination of Identifier and Security level and operation of the lock function Identifier Level Description User High The specified password is set as a new user password The lock function is enabled after the device is turned off and then on LOCKED MODE can be canceled using the user password or...

Page 177: ...y Frozen mode ST 51h ER 04h 3 A SATA communication error occurred ST 51h ER 14h At command issuance Shadow Block Registers setting contents CM 1 1 1 1 0 0 0 1 DH x x x x xx CH CL SN SC FR xx xx xx xx xx At command completion Shadow Block Register contents to be read ST Status information DH x x x x xx CH CL SN SC ER xx xx xx xx Error information ...

Page 178: ...ared with the user password already set If the passwords are the same LOCKED MODE is canceled Otherwise the Aborted Command error is returned If the password comparison fails the device decrements the UNLOCK counter The UNLOCK counter initially has a value of five When the value of the UNLOCK counter reaches zero this command or the SECURITY ERASE UNIT command causes the Aborted Command error unti...

Page 179: ...5 3 Host Commands C141 E203 01EN 5 105 At command completion Shadow Block Register contents to be read ST Status information DH x x x x xx CH CL SN SC ER xx xx xx xx Error information ...

Page 180: ... the SECURITY ERASE UNIT command Error reporting conditions 1 An incorrect password is specified ST 51h ER 04h 2 The device is in Security Frozen mode ST 51h ER 04h 3 A SATA communication error occurred ST 51h ER 14h At command issuance Shadow Block Registers setting contents CM 1 1 1 1 0 0 1 1 DH x x x x xx CH CL SN SC FR xx xx xx xx xx At command completion Shadow Block Registers contents to be ...

Page 181: ... this command invalidates the user password the master password is retained To recover the master password issue the SECURITY SET PASSWORD command and reset the user password Error reporting conditions 1 An incorrect password is specified ST 51h ER 04h 2 The Security Erase Prepare command did not complete normally beforehand ST 51h ER 04h 3 The device is in Security Frozen mode ST 51h ER 04h 4 A S...

Page 182: ... UNIT FROZEN MODE is canceled when the power is turned off or when COMRESET is reseted If this command is reissued in FROZEN MODE the command is completed and FROZEN MODE remains unchanged The following medium access commands return the Aborted Command error when the device is in LOCKED MODE READ DMA EXT READ LONG READ MULTIPLE EXT READ SECTORS READ VERIFY SECTORS WRITE DMA EXT WRITE LONG WRITE MU...

Page 183: ...ions 1 The device is in Security Locked mode ST 51h ER 04h 2 A SATA communication error occurred ST 51h ER 14h At command issuance Shadow Block Registers setting contents CM 1 1 1 1 0 1 0 1 DH x x x x xx CH CL SN SC FR xx xx xx xx xx At command completion Shadow Block Registers contents to be read ST Status information DH x x x x xx CH CL SN SC ER xx xx xx xx Error information ...

Page 184: ...ser password the master password is retained To recover the master password issue the SECURITY SET PASSWORD command and reset the user password If the user password or master password transferred from the host does not match the Aborted Command error is returned Issuing this command while in LOCKED MODE or FROZEN MODE returns the Aborted Command error The section about the SECURITY FREEZE LOCK com...

Page 185: ... The device is in Security Frozen mode ST 51h ER 04h 4 A SATA communication error occurred ST 51h ER 14h At command issuance Shadow Block Registers setting contents CM 1 1 1 1 0 1 1 0 DH x x x x xx CH CL SN SC FR xx xx xx xx xx At command completion Shadow Block Registers contents to be read ST Status information DH x x x x xx CH CL SN SC ER xx xx xx xx Error information ...

Page 186: ... CL and SN field Then reports the status to the host system Error reporting conditions 1 A SATA communication error occurred ST 51h ER 14h At command issuance Shadow Block Registers setting contents CM 1 1 1 1 1 0 0 0 DH x L x x xx CH CL SN SC FR xx xx xx xx xx At command completion Shadow Block Registers contents to be read ST Status information DH x x x x Max head LBA MSB CH CL SN SC ER CYL No M...

Page 187: ...rrence of a hard reset When the VV bit is 0 the value set by this command becomes invalid when the power is turned on or a ComRest occurs and the maximum address returns to the value most lately set when VV bit 1 The value by VV bit 0 is held in case that this command with VV bit 1 has not been issued or had set the default value and ComRest occurs When the READ NATIVE MAX ADDRESS command has been...

Page 188: ...ssuance Shadow Block Registers setting contents CM 1 1 1 1 1 0 0 1 DH x L x x HD No LBA CH CL SN CYL No MSB LBA CYL No LSB LBA SCT No LBA LSB SC xx VV FR xx At command completion Shadow Block Registers contents to be read ST Status information DH x x x x xx CH CL SN SC ER CYL No MSB LBA CYL No LSB LBA SCT No LBA LSB xx Error information SET MAX SET PASSWORD Features Field 01h This command requests...

Page 189: ... 04h 4 A SATA communication error occurred ST 51h ER 14h At command issuance Shadow Block Registers setting contents CM 1 1 1 1 1 0 0 1 DH x x x x xx CH CL SN SC FR xx xx xx xx 01 At command completion Shadow Block Registers contents to be read ST Status information DH CH CL SN SC ER xx xx xx xx xx Error information Password information Words Contents 0 Reserved 1 to 16 Password 32 bytes 17 to 255...

Page 190: ...cle or the acceptance of SET MAX UNLOCK or SET MAX FREEZE LOCK command Error reporting conditions 1 The device is in Set Max Locked mode or Set Max Freeze Locked mode ST 51h ER 04h 2 The SET MAX ADDRESS EXT command has been issued ST 51h ER 04h 3 A SATA communication error occurred ST 51h ER 14h At command issuance Shadow Block Registers setting contents CM 1 1 1 1 1 0 0 1 DH x x x x xx CH CL SN S...

Page 191: ...ro then SET MAX UNLOCK command returns command aborted until a power cycle If the password compare matches then the device makes a transition to the Set Max Unlocked state and all SET MAX commands will be accepted Error reporting conditions 1 The device is in Set Max Locked mode or Set Max Freeze Locked mode ST 51h ER 04h 2 The device is in Set Max Unlocked mode ST 51h ER 04h 3 The SET MAX ADDRESS...

Page 192: ...PASSWORD SET MAX LOCK SET MAX UNLOCK Error reporting conditions 1 The device is in Set Max Locked mode or Set Max Freeze Locked mode ST 51h ER 04h 2 The SET MAX ADDRESS EXT command has been issued ST 51h ER 04h 3 A SATA communication error occurred ST 51h ER 14h At command issuance Shadow Block Registers setting contents CM 1 1 1 1 1 0 0 1 DH x x x x xx CH CL SN SC FR xx xx xx xx 04 At command com...

Page 193: ...ions 1 The command was issued in CHS mode ST 51h ER 04h The other error reporting conditions are the same as those of the READ SECTOR S command At command issuance Shadow Block Registers setting contents CM 0 0 1 0 0 1 0 0 DH 1 L 1 x xx CH EXP CH CL EXP CL SN EXP SN SC EXP SC FR EXP FR LBA 47 40 LBA 23 16 LBA 39 32 LBA 15 8 LBA 31 24 LBA 7 0 Sector count 15 8 Sector count 7 0 xx xx At command comp...

Page 194: ...e command was issued in CHS mode ST 51h ER 04h The other error reporting conditions are the same as those of the READ DAM command At command issuance Shadow Block Registers setting contents CM 0 0 1 0 0 1 0 1 DH 1 L 1 x xx CH EXP CH CL EXP CL SN EXP SN SC EXP SC FR EXP FR LBA 47 40 LBA 23 16 LBA 39 32 LBA 15 8 LBA 31 24 LBA 7 0 Sector count 15 8 Sector count 7 0 xx xx At command completion Shadow ...

Page 195: ...ST 51h ER 04h 2 A SATA communication error occurred ST 51h ER 14h At command issuance Shadow Block Registers setting contents CM 0 0 1 0 0 1 1 1 DH 1 L 1 x xx CH EXP CH CL EXP CL SN EXP SN SC EXP SC FR EXP FR xx xx xx xx xx xx xx xx xx xx At command completion Shadow Block Registers contents to be read ST Status information DH 1 L 1 x xx CH EXP CH CL EXP CL SN EXP SN SC EXP SC ER Native max addres...

Page 196: ... 1 The command was issued in CHS mode ST 51h ER 04h The other error reporting conditions are the same as those of the READ MULTIPLE command At command issuance Shadow Block Registers setting contents CM 0 0 1 0 1 0 0 1 DH 1 L 1 x xx CH EXP CH CL EXP CL SN EXP SN SC EXP SC FR EXP FR LBA 47 40 LBA 23 16 LBA 39 32 LBA 15 8 LBA 31 24 LBA 7 0 Sector count 15 8 Sector count 7 0 xx xx At command completi...

Page 197: ...eued protocol Read Log Ext log page 10h containing the error information is transferred This Read Log Ext log page can be read by specifying Sector offset 00h Sector count 01h and Log address 10h For the data format of Read Log Ext log page 10h see Table 5 29 If this command is not supported or if an invalid value is specified for the Log address Sector count or Sector offset the Aborted Command e...

Page 198: ...XP CH CL EXP CL SN EXP SN SC EXP SC FR EXP FR xx xx Sector offset 15 8 Sector offset 7 0 xx Log address Sector count 15 8 Sector count 7 0 xx xx At command completion Shadow Block Registers contents to be read ST Status information DH x x x x xx CH EXP CH CL EXP CL SN EXP SN SC EXP SC ER xx xx xx xx xx xx xx xx Error information ...

Page 199: ...value 07 Dev Head field value 08 Sector Number Exp field value 09 Cylinder Low Exp field value 0A Cylinder High Exp field value 0B Reserved 0C Sector Count field value 0D Sector Count Exp field value 0E to FF Reserved 100 to 1FE Vendor Unique 1FF Check sum Table 5 30 Tag field information Bit Description 0 4 If bit 7 is 0 this field has an error tag number 5 6 Reserved 7 If this bit is 0 the field...

Page 200: ...s 1 The command was issued in CHS mode ST 51h ER 04h The other error reporting conditions are the same as those of the WRITE SECTOR S command At command issuance Shadow Block Registers setting contents CM 0 0 1 1 0 1 0 0 DH 1 L 1 x xx CH EXP CH CL EXP CL SN EXP SN SC EXP SC FR EXP FR LBA 47 40 LBA 23 16 LBA 39 32 LBA 15 8 LBA 31 24 LBA 7 0 Sector count 15 8 Sector count 7 0 xx xx At command comple...

Page 201: ... 1 The command was issued in CHS mode ST 51h ER 04h The other error reporting conditions are the same as those of the WRITE DMA command At command issuance Shadow Block Registers setting contents CM 0 0 1 1 0 1 0 1 DH 1 L 1 x xx CH EXP CH CL EXP CL SN EXP SN SC EXP SC FR EXP FR LBA 47 40 LBA 23 16 LBA 39 32 LBA 15 8 LBA 31 24 LBA 7 0 Sector count 15 8 Sector count 7 0 xx xx At command completion S...

Page 202: ...ddress value is defined as the last value specified If the VV bit is not set to 1 the highest address is the default value After a power on reset is performed a host can issue the SET MAX ADDRESS EXT command only once if the VV bit is 1 If the SET MAX ADDRESS EXT command is issued twice or more an ID Not Found error occurs When the SET MAX ADDRESS EXT command is executed all SET MAX ADDRESS comman...

Page 203: ... SET MAX LBA 23 16 SET MAX LBA 39 32 SET MAX LBA 15 8 SET MAX LBA 31 24 SET MAX LBA 7 0 xx SC xx VV FR EXP FR xx xx At command completion Shadow Block Registers contents to be read ST Status information DH 1 L 1 x xx CH EXP CH CL EXP CL SN EXP SN SC EXP SC ER SET MAX LBA 47 40 SET MAX LBA 23 16 SET MAX LBA 39 32 SET MAX LBA 15 8 SET MAX LBA 31 24 SET MAX LBA 7 0 xx xx Error information ...

Page 204: ...s 1 The command was issued in CHS mode ST 51h ER 04h The other error reporting conditions are the same as those of the WRITE MULTIPLE command At command issuance Shadow Block Registers setting contents CM 0 0 1 1 1 0 0 1 DH 1 L 1 x xx CH EXP CH CL EXP CL SN EXP SN SC EXP SC FR EXP FR LBA 47 40 LBA 23 16 LBA 39 32 LBA 15 8 LBA 31 24 LBA 7 0 Sector count 15 8 Sector count 7 0 xx xx At command comple...

Page 205: ... count or Sector offset the Aborted Command error occurs Error reporting conditions 1 An error was detected during power on processing ST 51h ER 04h 2 An error was detected during wake up processing in cases where wake up processing is required before execution of this command ST 51h ER 04h 3 A write fault was detected while the write cache was disabled ST 71h ER 10h 4 While the write cache is ena...

Page 206: ...XP CH CL EXP CL SN EXP SN SC EXP SC FR EXP FR xx xx Sector offset 15 8 Sector offset 7 0 xx Log address Sector count 15 8 Sector count 7 0 xx xx At command completion Shadow Block Registers contents to be read ST Status information DH x x x x xx CH EXP CH CL EXP CL SN EXP SN SC EXP SC ER xx xx xx xx xx xx xx xx Error information ...

Page 207: ... conditions 1 The command was issued in CHS mode ST 51h ER 04h The other error reporting conditions are the same as those of the READ VERIFY SECTOR S command At command issuance Shadow Block Registers setting contents CM 0 1 0 0 0 0 1 0 DH 1 L 1 x xx CH EXP CH CL EXP CL SN EXP SN SC EXP SC FR EXP FR LBA 47 40 LBA 23 16 LBA 39 32 LBA 15 8 LBA 31 24 LBA 7 0 Sector count 15 8 Sector count 7 0 xx xx A...

Page 208: ...ions 1 A SATA communication error occurred ST 51h ER 14h At command issuance Shadow Block Registers setting contents CM 1 1 1 0 1 0 1 0 DH 1 L 1 x xx CH EXP CH CL EXP CL SN EXP SN SC EXP SC FR EXP FR xx xx xx xx xx xx xx xx xx xx At command completion Shadow Block Registers contents to be read ST Status information DH 1 L 1 x xx CH EXP CH CL EXP CL SN EXP SN SC EXP SC ER xx xx xx xx xx xx xx xx Er...

Page 209: ... the same as those of the WRITE MULTIPLE EXT command At command issuance Shadow Block Registers setting contents CM 1 1 0 0 1 1 1 0 DH 1 L 1 x xx CH EXP CH CL EXP CL SN EXP SN SC EXP SC FR EXP FR LBA 47 40 LBA 23 16 LBA 39 32 LBA 15 8 LBA 31 24 LBA 7 0 Sector count 15 8 Sector count 7 0 xx xx At command completion Shadow Block Registers contents to be read ST Status information DH 1 L 1 x xx CH EX...

Page 210: ...ame as those of the WRITE DMA EXT command At command issuance Shadow Block Registers setting contents CM 0 0 1 1 1 1 0 1 DH 1 L 1 x xx CH EXP CH CL EXP CL SN EXP SN SC EXP SC FR EXP FR LBA 47 40 LBA 23 16 LBA 39 32 LBA 15 8 LBA 31 24 LBA 7 0 Sector count 15 8 Sector count 7 0 xx xx At command completion Shadow Block Registers contents to be read ST Status information DH 1 L 1 x xx CH EXP CH CL EXP...

Page 211: ...XP CL SN EXP SN SC EXP LBA 47 40 LBA 23 16 LBA 39 32 LBA 15 8 LBA 31 24 LBA 7 0 xx SC TAG xx FR EXP FR xx xx At command completion Shadow Block Registers contents to be read ST Status information DH 1 L 1 x xx CH EXP CH CL EXP CL SN EXP SN SC EXP SC ER xx xx xx xx xx xx xx xx Error information FUA If this bit is 1 the device always reads data from media regardless of whether the data requested by ...

Page 212: ...x CH EXP CH CL EXP CL SN EXP SN SC EXP LBA 47 40 LBA 23 16 LBA 39 32 LBA 15 8 LBA 31 24 LBA 7 0 xx SC TAG xx FR EXP FR xx xx At command completion Shadow Block Registers contents to be read ST Status information DH 1 L 1 x xx CH EXP CH CL EXP CL SN EXP SN SC EXP SC ER xx xx xx xx xx xx xx xx Error information FUA If this bit is 1 the device always reports the status after data is written to a medi...

Page 213: ...V V V V V V V SEEK V V V V V V EXECUTE DEVICE DIAGNOSTIC V 1 1 1 1 INITIALIZE DEVICE PARAMETERS V V V V V DOWNLOAD MICROCODE V V V V V STANDBY IMMEDIATE V V V V V IDLE IMMEDIATE V V V V V STANDBY V V V V V IDLE V V V V V CHECK POWER MODE V V V V V SLEEP V V V V V SMART V V V V V V V DEVICE CONFIGURATION V V V V V V READ MULTIPLE V V V V V V V WRITE MULTIPLE V V V V V V SET MULTIPLE MODE V V V V V ...

Page 214: ...D DMA EXT V V V V V V V READ NATIVE MAX ADDRESS EXT V V V V V READ MULTIPLE EXT V V V V V V V WRITE LOG EXT V V V V V V WRITE SECTOR S EXT V V V V V V WRITE DMA EXT V V V V V V SET MAX ADDRESS EXT V V V V V V WRITE MULTIPLE EXT V V V V V V READ LOG EXT V V V V V V V READ VERIFY SECTOR S EXT V V V V V V V FLUSH CACHE EXT V V V V V V WRITE MULTIPLE FUA EXT V V V V V V WRITE DMA FUA EXT V V V V V V R...

Page 215: ...e following commands can be executed even if DRDY bit is 0 EXECUTE DEVICE DIAGNOSTIC INITIALIZE DEVICE PARAMETERS 5 4 1 Non data command protocol Execution of the following commands does not involve data transfer between the host and the device RECALIBRATE SEEK READ VERIFY SECTOR S EXT EXECUTE DEVICE DIAGNOSTIC INITIALIZE DEVICE PARAMETERS SET FEATURES SET MULTIPLE MODE SET MAX ADDRESS EXT READ NA...

Page 216: ...ollowing is the protocol for command execution without data transfer 1 The device receives a non data command with the Register HD FIS 2 The device executes the received command 3 Command execution is completed 4 The device reports the completion of command execution by sending to the host the Register DH FIS with 1 set in the I bit Device Host RegHD RegDH Figure 5 10 Non data command protocol ...

Page 217: ... 2 If an error remaining in the device prevents command execution the device sends the Register DH FIS with 1 set in the I bit 3 When the device is ready to send data it sets 0 in the BSY bit 1 in the DRQ bit and 1 in the I bit of the Status field of the PIO Setup FIS then sends this FIS to the host At this time if the requested data is read from the last sector to be processed the device sets 0 i...

Page 218: ...he host system to the device WRITE SECTOR S EXT WRITE MULTI EXT FUA EXT WRITE LONG WRITE BUFFER WRITE VERIFY SMART WRITE LOG SECTOR SECURITY DISABLE PASSWORD SECURITY ERASE UNIT SECURITY SET PASSWORD SECURITY UNLOCK DOWNLOAD MICROCODE WRITE LOG EXT DEVICE CONFIGRATION SET Data of one or more sectors is transferred from the host to the device With the WRITE LONG command data of 516 bytes is transfe...

Page 219: ...Setup FIS for a data transfer to the first sector while it sets 1 in the I bit for a data transfer to any sector other than the first sector Then it sends this FIS to the host In the E_Status field the device sets 1 in the BSY bit and 0 in the DRQ bit 4 The device receives the DATA FIS from the host 5 When all data has been transferred the device sends the Register DH FIS with 1 set in the I bit t...

Page 220: ...in command with the Register HD FIS 2 If an error remaining in the device prevents command execution the device sends the Register DH FIS with 1 set in the I bit 3 When the device is ready to send data it sends the Data FIS to the host 4 When all data has been transferred the device sends the Register DH FIS with 1 set in the I bit to complete execution of the command If any data remains to be sen...

Page 221: ...HD FIS 2 If an error remaining in the device prevents command execution the device sends the Register DH FIS with 1 set in the I bit 3 When the device is ready to receive data it sends the DMA Activate FIS to the host 4 The device receives the Data FIS from the host 5 When all data has been transferred the device sends the Register DH FIS with 1 set in the I bit to complete execution of the comman...

Page 222: ...the Set Device Bits FIS corresponding to the tag number of the completed command is set by the device and the device sets 0 in the Err bit and 0 in the Error register in the Set Device Bits FIS Then it sends the Set Device Bits FIS to the host 5 For the data transfer of the WRITE FP DMA QUEUED command if the DMA Setup Auto Activate function is disabled the device sends to the host the DMA Setup FI...

Page 223: ...SoftReset and COMRESET The device reports abort for other commands 10 If the device receives the READ LOG EXT command with page 10h specified queued commands are aborted Then after the device sends to the host the Set Device Bits FIS ERR 0 ERRReg 0 I 0 and SActive 0xFFFFFFFF it sends to the host the log data for the READ LOG EXT command with page 10h specified and reports the status of this comman...

Page 224: ...Interface 5 150 C141 E203 01EN Device Host RegHD RegDH DMAS SETDB DATA DMAC Figure 5 16 WRITE FP DMA QUEUED command protocol ...

Page 225: ...th the SATA interface is established the host sets 0xFFh in the Status field of the Shadow Block Register The device completes the power on sequence within 10 ms so that communication with the SATA interface can be established Device TX Host RX Host TX Device RX Host power on Host ComReset Host releases ComReset Host calibrate Host ComWake Host releases ComWake Host Align Host data Device ComInit ...

Page 226: ...Device RX Host device on Host ComReset Host releases ComReset Host calibrate Host ComWake Host releases ComWake Host Align Host data Device ComInit Device releases ComInit Device Calibrate Device ComWake Device Align Device data Figure 5 18 COMRESET sequence ...

Page 227: ...C141 E203 01EN 6 1 CHAPTER 6 Operations 6 1 Reset and Diagnosis 6 2 Power Save 6 3 Interface Power Save 6 4 Read ahead Cache 6 5 Write Cache This chapter explains each of the above operations ...

Page 228: ...lds After communication with the SATA interface is established the host sets 0xFFh in the Status field of the Shadow Block The device establishes communication with the SATA interface PHY Ready within 10 ms The device sends the FIS STS 50h to notify the host that the device is ready Note Figure 6 1 assumes that power is turned on after the power off state continued for more than five seconds Figur...

Page 229: ...6 1 Reset and Diagnosis C141 E203 01EN 6 3 Figure 6 2 Response to power on when the device is powered on earlier than the host ...

Page 230: ...as the response when power is turned on and a power on reset is then cancelled The device establishes communication with the SATA interface PHY Ready and sends the Register DH FIS STS 50h to notify the host that the device is ready Then the COMRESET sequence is completed Figure 6 3 Response to COMRESET ...

Page 231: ...o a software reset When a software reset is accepted the device performs a self diagnosis and it sends the Register DH FIS STS 50h to notify the host that the device is ready Then the software reset sequence is completed Figure 6 4 Response to a software reset ...

Page 232: ...ive mode In this mode all the electric circuit in the device are active or the device is under seek read or write operation A device enters the active mode under the following conditions The media access system is received 2 Active idle mode In this mode circuits on the device is set to power save mode The device enters the Active idle mode under the following conditions After completion of the co...

Page 233: ...me has elapsed in the low power idle state APM Mode 2 The time specified by the STANDBY or IDLE command has elapsed after completion of the command A reset is issued in the sleep mode When one of following commands is issued the command is executed normally and the device is still stayed in the standby mode Reset hardware or software STANDBY command STANDBY IMMEDIATE command INITIALIZE DEVICE PARA...

Page 234: ...Operations 6 8 C141 E203 01EN 6 2 2 Power commands The following commands are available as power commands IDLE IDLE IMMEDIATE STANDBY STANDBY IMMEDIATE SLEEP CHECK POWER MODE SET FEATURES APM setting ...

Page 235: ...t switch to Active mode from the Interface Power Down state Period in which the device must switch to Active mode Partial mode Maximum 10 µs Slumber mode Maximum 10 ms 1 Active mode The interface is in the Active state and commands can be accepted 2 Partial mode In this mode shallow Power Save mode is set for the interface circuit The device switches to Partial mode when the following occurs The d...

Page 236: ... and responds with the PMACK signal The device sends the PMREQ_S signal and the host responds with PMACK signal The device cannot switch to Slumber mode if the following condition is satisfied The device responds with the PMNAK signal because it is not waiting for commands The device returns to Active mode from Slumber mode when the following condition is satisfied The device receives the COMRESET...

Page 237: ...ccessing the disk media As the result faster data access becomes possible for the host 6 4 1 Data buffer structure This device contains a data buffer This buffer is divided into two areas one area is used for MPU work and the other is used as a read cache for another command See Figure 6 5 8MB buffer For MPU work For R W command 8 192 KB 8 388 608 bytes 336 KB 344 064 bytes 7 856 KB 8 044 544 byte...

Page 238: ... if the caching function is prohibited by the SET FEATURES command the caching operation is not performed 2 Data that is a target of caching The data that is a target of caching are as follows 1 Read ahead data that is read from disk media and saved to the data buffer upon completion of execution of a command that is a target of caching 2 Pre read data that is read from disk media and saved to the...

Page 239: ...BRATE FORMAT TRACK SET FEATURES SECURITY ERASE UNIT DEVICE CONFIGURATION DOWNLOAD MICROCODE UNSUPPORT COMMAND INVALID COMMAND 1 2Commands that partially invalidate caching data READ DMA READ MULTIPLE READ SECTOR S READ DMA EXT READ MULTIPLE EXT READ SECTOR S EXT READ FP DMA QUEUED WRITE DMA WRITE MULTIPLE WRITE SECTOR S WRITE DMA EXT WRITE MULTIPLE EXT WRITE SECTOR S EXT WRITE DMA FUA EXT WRITE MU...

Page 240: ...d HAP is set at the requested data reading position Read segment AP host address pointer DAP disk address pointer 2 During reading of read requested data the request data that has already been read is sent to the host system Read requested data Free space HAP DAP Read requested data is stored until this point 3 When reading of read requested data is completed and transfer of the read requested dat...

Page 241: ... of read requested data the request data that has already been read is sent to the host system Cache valid data Free space Read requested data DAP disk address pointer HAP host address pointer 3 When reading of read requested data is completed and transfer of the read requested data to the host system is completed the read ahead operation continues until a certain amount of data is stored Read ahe...

Page 242: ...rts while the read ahead operation is in progress 1 An example is the state shown below where the previous read command is executing sequential reading First HAP is set at the location where hit data is stored HAP It is reset to the hit data location for transfers HAP end location of the previous read command DAP end location of the previous read command Cache data Full hit data Cache data HAP DAP...

Page 243: ...he valid data TART LBA LAST LBA 1 HAP is set at the address where partial hit data is stored and Transfer is started Cache valid data Partial hit data HAP host address pointer 2 DAP and HAP are set at the head of Buffer newly allocated and insufficient data is read Read segment HAP host address pointer DAP disk address pointer 3 When reading the read requested data ends and the transmission of the...

Page 244: ...rformed when the caching function is prohibited by the SET FEATURES command 2 Invalidation of cached data If an error occurs during writing onto media write processing is repeated up to as many times as specified for retry processing If retry fails for a sector because the retry limit is reached automatic alternate sector processing is executed for the sector If the automatic alternate sector proc...

Page 245: ...COMRESET or software reset is received while cached data is stored on the data buffer data of the data buffer is written on the media and reset processing is then performed This is true for both a hard reset and soft reset 6 Cashing function when power supply is turned on The cashing function is invalid until Calibration is done after the power supply is turned on about 10 sec It is effective in D...

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Page 247: ...rive The physical specifications of the drive do not always correspond to these parameters The BIOS of a PC AT cannot make full use of the physical specifications of these drivers To make the best use of these drives a BIOS that can handle the standard parameters of these drives is required Command Commands are instructions to input data to and output data from a drive Commands are written in comm...

Page 248: ...served Reserved bits bytes and fields are set to zero and unusable because they are reserved for future standards Rotational delay Time delay due to disk rotation The mean delay is the time required for half a disk rotation The mean delay is the average time required for a head to reach a sector after the head is positioned on a track Seek time The seek time is the time required for a head to move...

Page 249: ...ter DRDY Drive ready DRQ Ddata request bit DSC Drive seek complete DWF Drive write fault E ECC Error checking and correction ER Error register ERR Error F FR Feature register H HA Host adapter HDD Hard disk drive I IDNF ID not found IRQ14 Interrupt request 14 L LED Light emitting diode M MB Mega byte MB S Mega byte per seconds MPU Micro processor unit P PCA Printed circuit assembly PIO Programmed ...

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Page 251: ...2 2 blower on rotating disk 4 3 breather filter 4 3 breather location of 3 5 buffer data 1 3 busy BSY bit 5 20 C cache read ahead 6 11 write 1 3 6 18 cache operation 6 18 cache system read ahead 1 3 cached data invalidation of 6 18 caching command for 6 12 6 18 data for 6 12 caching data invalidating 6 13 caching operation 6 12 calibration 4 13 calibration self 4 7 capability off line data collect...

Page 252: ...pinout 5 8 connector specification host system 3 10 connector device 3 9 content self calibration 4 7 control actuator motor 4 17 servo 4 12 spindle motor 4 18 controller circuit 2 3 4 4 converter D A 4 13 CSR 4 13 current attribute value 5 57 current fluctuation at 5 V power on 1 8 current fluctuation 1 8 current LBA under test 5 65 current requirement 1 7 current span under test 5 66 cylinder hi...

Page 253: ...E 5 41 DOWNLOAD MICROCODE operation 5 41 drive connection 2 3 drive error logging capability 5 59 drive system configuration 2 3 driver circuit 4 13 driver circuit spindle motor 4 3 E E_status field 5 21 ECC for error correction 1 3 ECC for retry 1 3 effect blower 2 2 electrical specification 5 6 enabling and disabling 6 19 ENDEC 4 11 environmental specification 1 8 error positioning 1 11 unrecove...

Page 254: ...lationship between 5 102 IDENTIFY DEVICE 5 85 IDENTIFY DEVICE command information to be read by 5 87 IDENTIFY DEVICE DMA 5 86 IDLE 5 46 IDLE IMMEDIATE 5 44 information to be read by IDENTIFY DEVICE command 5 87 INITIALIZE DEVICE PARAMETERS 5 40 inner guard band 4 14 input voltage 1 6 installation 3 8 installation condition 3 1 interface 1 3 5 1 logical 5 9 physical 5 2 SATA 2 3 interface power man...

Page 255: ... 12 DOWNLOAD MICROCODE 5 41 seek 4 17 track following 4 17 operation sequence power on 4 6 orientation 3 3 out of band signaling 5 4 outer guard band 4 14 outerview disk drive 2 2 outline 4 2 outline of frame information structure FIS 5 12 shadow block register 5 11 overview device 1 1 P PAD 4 16 parameter 5 22 5 139 partial hit 6 17 partial mode 6 9 password master 5 104 user 5 104 performance 1 ...

Page 256: ... equipment 3 8 recovery write read 4 16 reference cylinder moving head to 4 13 4 17 register device to host 5 13 register host to device 5 12 reliability 1 10 requirement current 1 7 power 1 6 reset 6 2 reset response 6 19 reset power on and COMRESET 5 151 resistance against shock high 1 2 response to COMRESET 6 4 response to power on 6 2 response to software reset 6 5 retry by ECC 1 3 rewriting m...

Page 257: ... regulation 5 4 signal segment 3 10 signal interface 5 2 SLEEP 5 49 sleep mode 6 7 slumber mode 6 10 SMART 5 50 SMART comprehensive error log data format of 5 63 SMART error logging 5 60 SMART self test 5 63 SMART self test log data format 5 64 SMART summary error log data format of 5 61 software reset SRST 5 21 software reset response 6 19 software reset response to 6 5 specification acoustic noi...

Page 258: ...ation 1 9 vibration specification 1 9 Viterbi detection circuit 4 11 voice coil motor 4 2 W worst case attribute value 5 57 WRITE BUFFER 5 84 write cache 1 3 6 18 write circuit 4 9 WRITE DMA 5 80 WRITE DMA EXT 5 127 WRITE DMA FUA EXT 5 136 WRITE FP DMA QUEUED 5 138 WRITE FP DMA QUEUED command protocol 5 150 WRITE LOG EXT 5 131 WRITE LONG 5 32 WRITE MULTIPLE 5 74 WRITE MULTIPLE EXT 5 130 WRITE MULT...

Page 259: ...air P Poor General appearance Technical level Organization Clarity Accuracy Illustration Glossary Acronyms Abbreviations Index Comments Suggestions List any errors or suggestions for improvement Page Line Contents Please send this form to the address below We will use your comments in planning future editions Address Fujitsu Learning Media Limited 37 10 Nishikamata 7 chome Oota ku Tokyo 144 0051 J...

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Page 261: ...MHT2080BH MHT2060BH MHT2040BH DISK DRIVES PRODUCT MANUAL C141 E203 01EN MHT2080BH MHT2060BH MHT2040BH DISK DRIVES PRODUCT MANUAL C141 E203 01EN ...

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