C156-E097-01EN
7 - 23
(1)
Asynchronous transfer
In asynchronous transfer mode, information transfer is controlled by the INIT and TARG which
are checking the status transition (from false to true and vice versa) of REQ and ACK signals
(interlock type). Asynchronous transfer can be used in all types of INFORMATION
TRANSFER phase (COMMAND, DATA, STATUS, MESSAGE). Figure 7.10 shows the
timing rule of the asynchronous transfer.
a. Transfer from TARG to INIT
The TARG specifies the information transfer direction by the I/O signal. If the I/O signal is
true, the information on the DATA BUS is transferred from the TARG to the INIT.
Information transfer processing is as follows:
1)
The TARG asserts the REQ signal at least 55 ns (Deskew Delay + Cable Skew Delay)
after sending valid information on the data bus (DB7 to DB0, P). It must maintain the
state of DB7 to DB0, P until the ACK signal becomes true on the TARG.
2)
INIT fetches the data from the data bus (DB7 to DB0, P) after the REQ signal becomes
true. It asserts the ACK signal to report the completion of reception.
3)
After the ACK signal becomes true on the TARG, the TARG negates the REQ signal.
Thereafter, the TARG can change the data of the data bus.
4)
The INIT negates the ACK signal after the REQ signal becomes false.
5)
After the ACK signal becomes false, the TARG proceeds to transfer the next byte.
b. Transfer from INIT to TARG
When the I/O signal is false, information on the data bus is transferred from the INIT to the
TARG. Information transfer processing is as follows.
1)
The TARG asserts the REQ signal to request the INIT to send information.
2)
The INIT asserts the ACK signal at least 55 ns (Deskew Delay + Cable Skew Delay)
after sending valid information of the requested type on the data bus (DB7 to DB0, P).
The information on the DATA BUS must be maintained until the REQ signal becomes
false on the INIT.
3)
The TARG fetches data from the data bus (DB7 to DB0, P) after the ACK signal
becomes true and negates the REQ signal to report the completion of reception.
4)
When the REQ signal becomes false on the INIT, the INIT negates the ACK signal.
After that, the INIT can change data on the data bus.
5)
The TARG proceeds to the transfer of the next byte after the ACK signal becomes false.
Summary of Contents for MCE3064SS
Page 1: ...C156 E097 01EN MCE3064SS MCF3064SS OPTICAL DISK DRIVES PRODUCT MANUAL ...
Page 3: ...This page is intentionally left blank ...
Page 31: ...This page is intentionally left blank ...
Page 52: ...C156 E097 01EN 2 21 Figure 2 3 Example of alternate processing ...
Page 53: ...This page is intentionally left blank ...
Page 72: ...C156 E097 01EN 3 19 Figure 3 17 SCSI cable connector ...
Page 81: ...This page is intentionally left blank ...
Page 97: ...4 16 C156 E097 01EN Figure 4 5 SCSI connection check 2 ...
Page 99: ...This page is intentionally left blank ...
Page 113: ...This page is intentinally left blank ...
Page 119: ...7 2 C156 E097 01EN Host system A Host system B Figure 7 1 Example of SCSI configuration ...
Page 133: ...7 16 C156 E097 01EN Figure 7 6 ARBITRATION phase ...
Page 135: ...7 18 C156 E097 01EN µ Figure 7 7 SELECTION phase 30 30 30 30 ...
Page 141: ...7 24 C156 E097 01EN Figure 7 10 Transfer in asynchronous mode 18 18 ...
Page 145: ...7 28 C156 E097 01EN Figure 7 11 Transfer in synchronous mode 11 11 11 11 43 18 43 18 ...
Page 146: ...C156 E097 01EN 7 29 Figure 7 12 Transfer in FAST SCSI mode ...
Page 148: ...C156 E097 01EN 7 31 Figure 7 13 Data transfer rate in asynchronous mode ...
Page 158: ...C156 E097 01EN 7 41 Figure 7 17 RESET condition ...
Page 160: ...C156 E097 01EN 7 43 Figure 7 18 Bus phase sequence 1 of 2 ...
Page 161: ...7 44 C156 E097 01EN Figure 7 18 Bus phase sequence 2 of 2 ...
Page 167: ...This page is intentionally left blank ...
Page 171: ...This page is intentionally left blank ...
Page 181: ......