FujiFilm FinePix FinePix S6500fd, Service Manual

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3-2
3. Schematics
FinePix S6000fd/S6500fd Service Manual
3-3. Description of Main Block Functions
3-3-1. Technical Overview
The FinePix S6000fd/S6500fd features the new "Face Kirei-Navi" function -- the world's fastest face detection function --
developed using the "Image Intelligence?" ultra-high quality digital image processing software. You just press a button to set
"Face Kirei-Navi" and the camera can detect up to 10 people's faces at once in as little as 0.05 seconds. It then focuses on a
person's face and automatically selects the correct brightness for that face.
Thanks to the super-efficient light capturing capacity of the "Super CCD Honeycom VI HR" and the "Real Photo Engine II"
image processing engine, the FinePix S6000fd/S6500fd can shoot full-pixel images with 6.3 million effective pixels even at
ultra-high sensitivities of ISO 3200. It also features "iFlash", which recognizes the distance to the main subject of the shot and
gauges the subject's size and position in the overall image. This enables it to automatically select the ideal flash brightness
and sensitivity setting so that features such as skin tones are captured perfectly with no flaring.
The 10.7x zoom lens provided on the FinePix S6000fd uses high-definition Fujinon optics and an ultra-wide 28-300 mm focal
range, so you can use just one lens for almost any type of shot. At 28 mm it is perfect for landscapes and snapshots while the
300 mm focal length is ideal for sporting events, concerts and portraits. The S6000fd/S6500fd is packed with functions built
around the latest FUJIFILM technology, including the popular "high sensitivity dual-shot" function, which lets you record 2
continuous images of the same shot, one taken with the flash and one without. Also included is the Picture Stabilization mode
for truly impressive telephoto images and crystal-clear shots of sporting events.
CCD signal processing/Camera circuit section
„ Analog signals output from the 1/1.7 type Super-CCD Honeycom VI HR (IC951), with an effective pixel count of 6.3
mega-pixels, undergo false color compensation processing, adaptive interpolation processing, amplification (AGC) and
signal mixing inside the CCD signal processing IC “BCS_MCM (IC102)” before being converted to 14-bit digital signals
(A/D) and sent to the signal processing LSI “NCS_L (IC201)”.
„
The CCD drive circuit, H drive, and V drive are installed in [BCS_MCM (IC102)].
Motor Circuit Section
„ The signal processing LSI “NCS_L (IC201)” that has received various operating switch commands manages the motor
drive IC (IC151) and controls the AF, SHUTTER, ZOOM and IRIS motors.
Imaging and Signal Processing Section
„ Input data from the CCD
14-bit digital image data (corresponding to 1H) that has been output from the imaging section (CCD/Camera Block) is
sent to the signal processing LSI “NCS_L (IC201)”, converted to 32-bit (16-bit x 2) data by the [internal buffer] inside this
LSI, and the image data for one frame (2848 x 2136 pix) is stored temporarily in [SD-RAM]. It is also integrated in the
[AUTO operation section] using the 32-bit the signal processing LSI “NCS_L (IC201)” image data and sent to the
BCS_MCM (IC102) to obtain the appropriate AE/AF/AWB.
„
Record processing to xD Card
Image data stored in SD-DRAM is sent one frame at a time to the internal [signal processing section] in the signal
processing LSI “NCS_L (IC201)”. In a process called unpacking, “32-bit to 12-bit conversion” and “pre-processing
including digital clamp, white balance and noise reduction processing, linear matrix processing, gamma correction and R/
G/B 14-bit to R/G/B 8-bit conversion” to “8-bit digital R/G/B signals to Y:Cb:Cr = 4:2:2 YC processing” are implemented in
this [signal processing section] and 8-bit Y/Cb/Cr image data are sent to the [internal buffer].
The “rearrangement of data in a format in which 8-bit Y/Cb/Cr signals are easily compressed” is done in the [internal
buffer] and after passing through the [JPEG operation block] to the [media controller], they are recorded on the xD card.
„ Reproduction of images from xD card
Compressed image data from the xD card is sent as 8-bit image data to the signal processing LSI “NCS_L (IC201)” then
it is sent to the [media control section], the [DMA unit] and the SD-DRAM and then it is sent to the [media controller], to
the [JPEG operation section] and to the [signal processing section].
In the [signal processing section], 8-bit Y/Cb/Cr signals are converted to 8-bit R/G/B signals and at the same time,
lettering display signals are weighted and passed through the [LCD controller to the LCD unit and displayed.
„ Image capture system adjustment data are stored in the Flash ROM.
LCD Unit
„ Digital signals from the signal processing LSI "NCS_L (IC201)" are sent directly to the LCD. And signals processed by the
EVF CONTROL IC (IC452) are sent to the EVF.
Power Supply Section
„ Power supply circuits constructed in the core of the DC IC (IC300) create the following power supplies, which are
supplied to each block.
+3.3VRUN
[IC281 (AV BLOCK), IC501 (AF LED BLOCK)]
+3.3VDOUT [IC401 (PMAN BLOCK), IC201 (NCS_L), IC457 (LCD DATA7 BLOCK), CN261 (MEDIA BLOCK),
IC271 (AV BLOCK), IC452 (EVF BLOCK), IC151 (MOTOR BLOCK)]
+3.3VAOUT [IC452 (EVF BLOCK), IC201 (NCS_L)]
+15VRUN [IC102 (CAMERA BLOCK)]
+5VAD [IC102 (CAMERA BLOCK), IC451 (LCD BLOCK), IC401 (PMAN BLOCK)]
+3.3VCAM [IC102 (CAMERA BLOCK)]
+5VRUN [Q452 (EVF BLOCK), IC451 (LCD BLOCK), IC401 (PMAN BLOCK)]
+1VNCS [IC651 (FDI BLOCK), IC401 (PMAN BLOCK)]
+3.3VNCS [IC651 (FDI BLOCK), IC401 (PMAN BLOCK)]
+5VMOT_VM1 [IC151 (MOTOR BLOCK)]
+5VMOT_VM2 [IC151 (MOTOR BLOCK)]
+2.5VRUN [IC201 (NCS_L)]
+1VRUN [IC201 (NCS_L)]
-8V [IC951 (CCD FPC BLOCK)]
15V [IC951 (CCD FPC BLOCK)]