Freescale Semiconductor SC140 DSP Core, Reference Manual

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4-8 SC140 DSP Core Reference Manual
Overview of the Combined JTAG and EOnCE Interface
Figure 4-4. Reading and Writing EOnCE Registers Via JTAG
The SC140 EOnCE has several shift registers to interface with the JTAG controller, one shift register per
functional unit. Each such shift register is used to interface with all the EOnCE registers in that unit. The
length of the each shift register is therefore equal to the length of the longest register in that unit. The list of
registers and the shift length is listed in Table 4-12. Figure 4-5 describes how to access a register whose
length is shorter than the shift register’s length (8 bits versus 32 bits, in this example). In write operations,
the last bits to be shifted in the shift register are written to the EOnCE register, the rest have no effect. In
read operations, the first bits shifted out of the shift register hold the read data. The rest of the bits are read
as zeros.
This organization shortens the access time to the EOnCE registers if the access is only to those registers,
and no other devices on the JTAG chain are accessed on that transaction. In such a case, reads and writes
can be done only to the actual register length. In case other devices participate in the transaction, the full
shift register length should be used, using the convention outlined in Figure 4-5. From the IEEE 1149.1
standard point of view, some of the EOnCE registers have different “read” and “write” views.
EOnCE is connected to the TDO.
EOnCE is ready to get command in ECR.
Write command into ECR register via shift-dr - update-dr
Execute CHOOSE_EONCE instruction in JTAG
.
Execute ENABLE_EONCE instruction in JTAG
The chosen register is selected.
Write/read data into the chosen register via shift-dr or update-dr.
The chosen register is written/read.
Bits 0-6 = offset of the chosen register.
Bits 7-8 = 00
Bit 9 = 0 when write command, and 1 when read command
Write JTAG data in order to choose the EOnCE