Freescale Semiconductor SC140 DSP Core, Reference Manual

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4-6 SC140 DSP Core Reference Manual
Overview of the Combined JTAG and EOnCE Interface
The first action that occurs when either block is entered is a Capture operation. The Capture-DR state
captures the data into the selected serial data path, and the Capture-IR state captures status information into
the instruction register. The Exit state follows the Shift state when shifting of instructions or data is
complete. The Shift and Exit states follow the Capture state so that test data or status information can be
shifted out and new data shifted in. Registers in the selected scan path hold their present state during the
Capture and Shift operations. The Update state causes the registers to update with the new data that is
shifted into the selected scan path.
4.2.3 Activating the EOnCE Through the JTAG Port
Each of the on chip EOnCE modules has an interface to a JTAG port (via the TAP controller). The
interface is active even when a reset signal to the SC140 core is asserted. However, the system reset must
be de-asserted to allow proper interface with the cores. This interface is synchronized with internal clocks
derived from the JTAG
TCK
clock. Through the JTAG-EOnCE interface, the JTAG TAP controller can
perform the following actions:
• Choose one or more EOnCE blocks (CHOOSE_EONCE instruction)
• Issue a debug request to the EOnCE (DEBUG_REQUEST instruction)
• Enable the chosen EOnCE modules.
• Write an EOnCE command to the EOnCE Command Register.
• Read and write internal EOnCE registers.
4.2.4 Enabling the EOnCE Module
The CHOOSE_EONCE mechanism allows integration of multiple SC140 cores and thus multiple EOnCE
modules on the same device. Using the CHOOSE_EONCE instruction, you can selectively activate one or
more of the EOnCE modules on the device. The EOnCE modules selected by the CHOOSE_EONCE
instruction are cascaded as shown in Figure 4-3. Only selected EOnCE modules respond to
ENABLE_EONCE and DEBUG_REQUEST instructions from the JTAG. In Motorola implementations, if
the DEBUG_REQUEST instruction is asserted during core reset, until reset de-assertion, all EOnCE
modules respond to the instruction and enter debug state when the core leaves reset. However, for driver
compatibility with non-Motorola implementations, the JTAG driver should perform CHOOSE_EONCE
also during reset for Motorola parts as well. The CHOOSE_EONCE instruction in this case will have no
effect. All EOnCE modules are deselected after reset. Since all the EOnCE modules are cascaded, the
selection procedure when not in reset is performed serially. The sequence is as follows:
1. Select the CHOOSE_EONCE instruction.
2. At Shift_DR state, enter the serial stream that specifies the modules to be selected.
The number of bits in the serial stream, that is, the number of clocks in this state, is equal to the
number of SC140 cores in the cascade. This state is indicated by the
CHOOSE_CLOCK_DR
signal.
To activate the n -th core in the cascade, which is the closest to
TDO
and the farthest from
TDI
, the
data is 1,0,0,0,...,0 (first a one, then n-1 zeros). If the data is 1,0,1,0,0....0 then both the n -th and the
n -2th cells are selected.