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Freescale Semiconductor SC140 DSP Core, Reference Manual

The Freescale Semiconductor SC140 DSP Core is a powerful digital signal processor designed for high-performance applications. To fully utilize its capabilities, make sure to download the comprehensive Reference Manual from our website, available for free. Unlock the potential of this product by accessing the user manual at manualshive.com.

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Static Programming Rules

SC140 DSP Core Reference Manual

7-21

Rule D.4

Instructions that read the PC register (implicitly or explicitly) as a source operand are not allowed in a 
RTED/RTSD/RTSTKD delay slot. This rule does not apply to the MARK instruction that reads the PC 
register for the EOnCE trace buffer.

Example 7-33.   PC Read in a Return Delay Slot

rted
adda pc,r0

;not allowed

rtsd
dosetup0 _label

;not allowed

Rule D.5

A MOVE-like instruction that writes the SR register cannot be grouped in a VLES with a BSR, BSRD, 
JSR or JSRD instruction. For mutually exclusive IFc subgroups in a VLES, this rule applies independently 
to each subgroup.

Example 7-34.   SR Write with a Subroutine Call

pop sr

jsr r0

;not allowed

Rule D.5a

A MOVE-like instruction that writes the SR register is not allowed in the delay slot of a BSRD or JSRD 
instruction.

Example 7-35.   SR Write in BSRD or JSRD Delay Slot

bsrd

_label

pop sr

;not allowed

Rule D.6

Instructions that read or write the SP register are not allowed in the delay slot of delayed return (RTSD, 
RTED, , and RTSTKD) instructions. This rule also applies to implicit SP register writes (push and pop 
instructions).

Example 7-36.   SP Use in Return Delay Slots

rtsd
tfra r0,sp

;not allowed

rted 
tfra sp,r0

;not allowed

rtsd
tfra  r0,osp

;allowed

rtstkd
tfra

osp,r0

;allowed

rtstkd 
pop d0

;not allowed

Summary of Contents for SC140 DSP Core

Page 1: ...Reference Manual Revision 4 1 September 2005 This document contains information on a new product Specifications and information herein are subject to change without notice c Freescale Semiconductor Inc 2005 All rights ...

Page 2: ...ts LICENSOR does not convey any license under its patent rights nor the rights of others LICENSOR products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support life or for any other application in which the failure of the LICENSOR product could create a situation where personal injury or death...

Page 3: ...umulate MAC Unit 2 3 2 1 1 3 Bit Field Unit BFU 2 3 2 1 1 4 Shifter Limiters 2 3 2 1 2 Address Generation Unit AGU 2 3 2 1 2 1 Stack Pointer Registers 2 4 2 1 2 2 Bit Mask Unit BMU 2 4 2 1 3 Program Sequencer Unit PSEQ 2 5 2 1 4 Enhanced On Chip Emulator EOnCE 2 5 2 1 5 Instruction Set Accelerator Plug in ISAP Interface 2 5 2 1 6 Memory Interface 2 5 2 2 DALU 2 6 2 2 1 DALU Architecture 2 6 2 2 1 ...

Page 4: ...2 Address Register Indirect Modes 2 38 2 3 3 3 PC Relative Mode 2 40 2 3 3 4 Special Addressing Modes 2 41 2 3 3 5 Memory Access Width 2 42 2 3 3 6 Memory Access Misalignment 2 42 2 3 3 7 Addressing Modes Summary 2 43 2 3 4 Address Modifier Modes 2 45 2 3 4 1 Linear Addressing Mode 2 45 2 3 4 2 Reverse carry Addressing Mode 2 45 2 3 4 3 Modulo Addressing Mode 2 45 2 3 4 4 Multiple Wrap Around Modu...

Page 5: ...tate 4 11 4 3 4 Debug Exception 4 12 4 3 5 Executing an Instruction while in Debug State 4 12 4 3 6 Software Downloading 4 12 4 3 7 EOnCE Events 4 14 4 3 8 EOnCE Actions 4 15 4 3 9 Event and Action Summary 4 15 4 4 EOnCE Enabling and Power Considerations 4 16 4 5 EOnCE Module Internal Architecture 4 16 4 5 1 EOnCE Controller 4 16 4 5 2 Event Counter 4 18 4 5 3 Event Detection Unit EDU 4 20 4 5 3 1...

Page 6: ...gister ECNT_EXT 4 53 4 8 4 EC Signals 4 53 4 9 Event Detection Unit EDU Channels and Registers 4 54 4 9 1 Address Event Detection Channel EDCA 4 54 4 9 1 1 EDCA Control Registers EDCAi_CTRL 4 54 4 9 1 2 EDCA Reference Value Registers A and B EDCAi_REFA EDCAi_REFB 4 57 4 9 1 3 EDCA Mask Register EDCAi_MASK 4 57 4 9 2 Data Event Detection Channel EDCD 4 58 4 9 2 1 EDCD Control Register EDCD_CTRL 4 5...

Page 7: ...3 1 3 Bit Mask Instruction Timing 5 16 5 3 2 Change Of Flow Instruction Timing 5 17 5 3 2 1 Direct PC Relative and Conditional COF 5 18 5 3 2 2 Delayed COF 5 19 5 3 2 3 COF Execution Cycles 5 19 5 3 3 Memory Access Timing 5 21 5 3 3 1 Memory Access Examples 5 22 5 3 3 2 Implicit Push Pop Memory Timing 5 24 5 3 3 3 Memory Stall Conditions 5 24 5 4 Hardware Loops 5 25 5 4 1 Loop Programming Model 5 ...

Page 8: ...5 48 5 8 1 1 Vector Base Address Register 5 48 5 8 1 2 Programming Exception Routine Addresses 5 48 5 8 2 Return From Exception Instructions 5 49 5 8 3 Maskable Interrupts 5 50 5 8 3 1 Interrupt Priority Level 5 50 5 8 3 2 Controlling All Interrupt Sources 5 50 5 8 4 Non Maskable Interrupts NMI 5 50 5 8 5 Internal Exceptions 5 50 5 8 5 1 Illegal Exception 5 51 5 8 5 2 DALU Overflow 5 52 5 8 5 3 TR...

Page 9: ...7 4 1 Grouping Rules 7 3 7 4 1 1 Prefix Instructions 7 3 7 4 1 2 Conditional Subgroups 7 3 7 4 1 3 Assembler Reordering 7 3 7 4 2 Sequencing Rules 7 4 7 4 2 1 Cycle Counts 7 4 7 4 2 2 Conditional Execution 7 4 7 4 2 3 Simulator Execution Counts 7 4 7 4 3 Register Read Write 7 4 7 4 3 1 Register Names 7 4 7 4 3 2 B Register Aliasing 7 5 7 4 4 Status Bit Updates 7 5 7 4 5 Instruction Words 7 5 7 4 6...

Page 10: ...ry Code Practices 7 50 7 7 2 3 Software Development Practices 7 51 7 8 LPMARK Rules 7 51 7 8 1 LPMARK Instruction Type 7 51 7 8 2 Static Programming Rules 7 52 7 8 2 1 General Grouping Rules 7 52 7 8 2 2 Prefix Grouping Rules 7 52 7 8 3 Dynamic Programming Rules 7 52 7 8 3 1 LPMARK Notation 7 52 7 8 3 2 Loop Nesting Rules 7 53 7 8 3 3 Loop LA Rules 7 53 7 8 3 4 Loop Sequencing Rules 7 55 7 8 3 5 L...

Page 11: ...A 7 A 1 5 1 One Word Low Register Prefix A 8 A 1 5 2 Two Word Prefix A 9 A 1 6 Instruction Types A 12 A 1 6 1 Instruction Sub types A 12 A 2 Instructions A 19 A 2 1 Instruction Definition Layout A 19 Appendix B StarCore Registry B 1 Using the StarCore Registry B 1 ...

Page 12: ...xii SC140 DSP Core Reference Manual ...

Page 13: ... 2 37 2 15 Modulo Addressing Example 2 46 2 16 Integer Move Instructions 2 53 2 17 Fractional Move Instructions 2 54 2 18 Bit Allocation in MOVE L D0 e D1 e 2 55 2 19 Endian Example 2 56 2 20 Basic Connection between SC140 Core and Memory 2 57 2 21 Memory Organization of Big and Little Endian Mode 2 57 2 22 Data Transfer in Big and Little Endian Modes 2 59 2 23 Multi Register Transfer in Big and L...

Page 14: ...er ESEL_CTRL 4 62 4 24 Event Selector Mask Debug State ESEL_DM 4 63 4 25 Event Selector Mask Debug Exception ESEL_DI 4 64 4 26 Event Selector Mask Enable Trace ESEL_ETB 4 64 4 27 Event Selector Mask Disable Trace ESEL_DTB 4 65 4 28 Trace Buffer Control Register TB_CTRL 4 67 5 1 Instruction Pipeline Stages 5 2 5 2 Instruction Grouping Methods 5 6 5 3 Low Register Prefix Selection Algorithm 5 11 5 4...

Page 15: ... 17 Address Modifier AM Bits 2 37 2 18 Access Width Support for Address and Register Update Calculations 2 42 2 19 Memory Address Alignment 2 43 2 20 Addressing Modes Summary 2 43 2 21 Modulo Register Values for Modulo Addressing Mode 2 47 2 22 Modulo Register Values for Wrap Around Modulo Addressing Mode 2 48 2 23 AGU Arithmetic Instructions 2 48 2 24 AGU Bit Mask Instructions BMU 2 50 2 25 AGU M...

Page 16: ...on 4 54 4 20 EDCD_CTRL Description 4 58 4 21 ESEL_CTRL Description 4 62 4 22 Allowed tracing mode combinations 4 66 4 23 TB_CTRL Description 4 67 5 1 Pipeline Example 5 3 5 2 Pipeline Stages Overview 5 3 5 3 Prefix Instructions 5 9 5 4 Conditional IFc Syntax 5 9 5 5 Instruction Categories Timing Summary 5 15 5 6 Non Loop Change of Flow Instructions 5 17 5 7 Loop Change Of Flow Instructions 5 18 5 ...

Page 17: ... Notation for the EA Operand A 5 A 6 Addressing Mode Notation for the ea Operand A 5 A 7 DALU Arithmetic Instructions MAC A 13 A 8 DALU Logical Instructions BFU A 14 A 9 AGU Arithmetic Instructions A 15 A 10 AGU Move Instructions A 15 A 11 AGU Stack Support Instructions A 16 A 12 AGU Bit Mask Instructions BMU A 17 A 13 AGU Non Loop Change of Flow Instructions A 17 A 14 AGU Loop Control Including L...

Page 18: ...xviii SC140 DSP Core Reference Manual ...

Page 19: ...ction 5 23 5 11 Execution Set Containing a Bit Mask and a Pop Instruction 5 24 5 12 Long Loop 5 30 5 13 Long Loop Disassembly 5 30 5 14 Short Loop Two Execution Sets 5 30 5 15 Short Loop One Execution Set 5 31 5 16 Nested Loop 5 31 5 17 Basic Exception Timing 5 53 6 1 ISAP memory access 6 61 6 2 ISAP Core register transfers 6 62 6 3 ISAP Core register transfers 6 62 6 4 Single ISAP coding 6 63 6 5...

Page 20: ...Subgroups 7 14 7 22 IFA Subgroup Must Be Last Instructions 7 14 7 23 Core AGU instructions on same VLES as ISAP instructions 7 15 7 24 ISAP instructions in same IFc group 7 15 7 25 MCTL Write to R0 R7 Use 7 16 7 26 Rn Nn Mn Write to AGU Use 7 17 7 27 Rn or Nn Write to MOVE like Use 7 18 7 28 LCn Write to MOVE like Use 7 18 7 29 NMID Update to EMR Read 7 19 7 30 Instructions in a Delay Slot 7 19 7 ...

Page 21: ... LCn Write at the Start of Short Loop n 7 34 7 61 LCn Write to CONT D Instruction 7 34 7 62 SAn Write at the End of Long Loop n 7 35 7 63 SAn Write to CONT D Instruction 7 35 7 64 LCn Read at the Start of Short Loop n 7 35 7 65 COF Destination to Loop Delay Slots 7 36 7 66 COF Instructions at LA 2 of a Long Loop 7 36 7 67 Bc Jc at SA 1 of a Short Loop 7 36 7 68 Bc Jc at LA 3 of a Long Loop 7 37 7 ...

Page 22: ... Enabled During Loop Body n 7 49 7 91 LFn Enabled at LPA or LPB 7 53 7 92 Instructions at the End of Long Loops 7 53 7 93 Active LCn Write at the End of Long Loops 7 54 7 94 Instructions in Short Loops 7 54 7 95 Active LCn Write at the Start of a Loop 7 55 7 96 Active SAn Write at the End of Long Loops 7 55 7 97 Active LCn Read at the Start of a Loop 7 56 7 98 COF Instructions at LPB of a Long Loo...

Page 23: ...pers hardware designers and application developers Organization This book is organized into six chapters and one appendix as follows Chapter 1 Introduction describes key features of the SC140 architecture This chapter also illustrates a typical system using the SC140 core Chapter 2 Core Architecture describes the main functional blocks and data paths of the SC140 core Chapter 3 Control Registers d...

Page 24: ...nal processor ECR EOnCE control register EDU Event detection unit with respect to the EOnCE EE EOnCE event pins EMCR EOnCE monitor and control register EMR Exception and mode register EOnCE Enhanced on chip emulator ERCV EOnCE receive register ES Event selector with respect to the EOnCE ESP Exception mode stack pointer ESR EOnCE status register ETRSMT EOnCE transmit register EXT Extension portion ...

Page 25: ...s per second MMACS Million multiply and accumulate operations per second MSB Most significant bits MSP Most significant portion Nn AGU offset register n NMI Non maskable interrupt NSP Normal mode stack pointer OS Operating system PAB Program address bus PAG Program address generator PC Program counter register PCU Program control unit PDB Program data bus PDU Program dispatch unit PIC Programmable...

Page 26: ...ue bit UI Unsigned integer VBA Interrupt vector base address register VLES Variable length execution set instruction grouping XABA Data memory address bus A XABB Data memory address bus B XDBA Data memory data bus A XDBB Data memory data bus B Table 2 Revision History Revision Date Description 4 0 31 Aug 2004 Fourth release of SC140 4 1 20 Sep 2005 Misc corrections restored missing IADDNC W instru...

Page 27: ... platform that fulfills the constantly increasing computational requirements of DSP applications due to New communication standards and services Wideband channels and data rates New user interfaces and media Currently software configurable wireless terminals are already required to accommodate multiple air interfaces and frequency bands for cellular phones PCs paging devices cordless phones wirele...

Page 28: ... units AAUs A high frequency of operation is achieved at low voltage providing four million multiply and accumulate MAC operations per second 4 MMACS for each megahertz of clock frequency Support exists for application specific accelerators providing a performance boost and reduction in power consumption High Code Density for Minimized Cost 16 bit wide instruction encoding A rich and orthogonal in...

Page 29: ... for fractional and integer data operand storage Sixteen 32 bit address registers eight of which can be used as 32 bit base address registers Four address offset registers and four modulo address registers Hardware support for fractional and integer data types Up to six instructions executed in a single clock cycle Very rich 16 bit wide orthogonal instruction set Support for application specific i...

Page 30: ...ction caches operating with zero wait states in case of cache hit Unified M1 memory supporting both program and data and hence connected to both the program and data buses of the core The M1 memory operates with no wait states It could be either RAM or ROM or a mix of both The RAM depending on its size may be connected as a slave to an external DMA Program interrupt controller PIC Interfaces trans...

Page 31: ...s are encoded in 16 bits Since atomic operations need fewer bits to encode the 16 bit instruction set becomes fully orthogonal and very rich in the functionality it supports In order to execute signal processing kernels a set of SC140 instructions can be grouped to be executed in parallel The PSEQ performs this automatically with up to four DALU instructions and two AGU instructions executed at th...

Page 32: ...1 6 SC140 DSP Core Reference Manual Core Architecture Features ...

Page 33: ...ion unit AGU Program sequencer unit PSEQ To provide data exchange between the core and the other on chip blocks the following buses are implemented Two data memory buses address and data pairs XABA and XDBA XABB and XDBB that are used for all data transfers between the core and memory Program data and address buses PDB and PAB for carrying program words from the memory to the core Special buses to...

Page 34: ...en the DALU register file and the memory are each 64 bits wide This enables a very high data transfer speed between memory and registers by allowing two data moves in parallel each up to 64 bits in width The move instructions vary in access width from 8 bits to 64 bits and can transfer multiple words within the 64 bit constraint With every MOVE instruction affecting the memory one of four signals ...

Page 35: ...iplicand The 32 bit product is right justified sign extended and may be added to the 40 bit contents of one of the 16 data registers 2 1 1 3 Bit Field Unit BFU The BFU contains a 40 bit parallel bidirectional shifter with a 40 bit input and a 40 bit output a mask generation unit and a logic unit The BFU is used in the following operations Multi bit left right shift arithmetic or logical One bit ro...

Page 36: ...es and updates the stack pointers as needed 2 1 2 1 Stack Pointer Registers Two special registers with special addressing modes are used for software stacks These are the Normal mode stack pointer NSP and the Exception mode stack pointer ESP Both the ESP and the NSP are 32 bit read write address registers with pre decrement and post increment updates Both are offset with immediate values to allow ...

Page 37: ...ule greatly aids the development of hardware and software on the SC140 core processor EOnCE interfacing with the debugging system through on chip JTAG TAP controller pins Refer to Chapter 4 Emulation and Debug EOnCE for details 2 1 5 Instruction Set Accelerator Plug in ISAP Interface A user defined instruction set accelerator plug in ISAP module provides a means of enhancing the SC140 basic instru...

Page 38: ...r from data registers or from immediate data The results of all DALU operations are stored in the data registers All DALU operations are performed in one clock cycle Up to parallel arithmetic operations can be performed in each cycle The destination of every arithmetic operation can be used as a source operand for the operation immediately following without any time penalty The components of the D...

Page 39: ... addition one limit tag bit is associated with each data register L0 L15 are concatenated to D0 D15 respectively Table 2 1 DALU Programming Model LIMIT EXT HP LP L0 D0 e D0 h D0 l L1 D1 e D1 h D1 l L2 D2 e D2 h D2 l L3 D3 e D3 h D3 L5 D5 e D5 h D5 l L6 D6 e D6 h D6 l L7 D7 e D7 h D7 l L8 D8 e D8 h D8 l L9 D9 e D9 h D9 l L10 D10 e D10 h D10 l L11 D11 e D11 h D11 l L12 D12 e D12 h D12 l L13 D13 e D1...

Page 40: ...ed with the arithmetic saturation mode as described in Section 2 2 2 7 Arithmetic Saturation Mode Limiting is performed after the contents of the register have been shifted according to the scaling mode Shifting and limiting are performed only for MOVES instructions when a fractional operand is specified as the source for a data move over XDBA or XDBB When an integer operand is specified as the so...

Page 41: ...r fractional long word can be written to memory with or without limiting and shifting See MOVE F and MOVES F in Appendix A SC140 DSP Core Instruction Set The register file architecture and the 64 bit wide data buses XDBA and XDBB support wide data transfers between the memory and the data registers Up to four 16 bit words or two 32 bit long words can be transferred between the register file and th...

Page 42: ...cription of each multiplication operation is given in Section 2 2 2 3 Multiplication The adder executes addition and subtraction of two 40 bit operands All MAC instructions are executed in one clock cycle Table 2 5 lists the arithmetic instructions that are executed in the MAC unit A more detailed description of each instruction is given in Appendix A SC140 DSP Core Instruction Set Table 2 4 Data ...

Page 43: ...PYSU Multiply signed integer and unsigned integer IMPYUU Multiply unsigned integer and unsigned integer INC Increment a data register INC F Increment a data register as fractional data MAC Multiply accumulate signed fractions MACR Multiply accumulate signed fractions and round MACSU Multiply accumulate signed fraction and unsigned fraction MACUS Multiply accumulate unsigned fraction and signed fra...

Page 44: ...truction is given in Appendix A SC140 DSP Core Instruction Set NEG Negate RND Round SAT F Saturate fractional value in data register to fit in high portion SAT L Saturate value in data register to fit in 32 bits SBC Subtract long with carry SBR Subtract and round SUB Subtract SUB2 Subtract two words SUBL Shift left and subtract SUBNC W Subtract with no carry bit generation TFR Transfer data regist...

Page 45: ...gical Instructions BFU Instruction Description AND Logical AND ASLL Multi bit arithmetic shift left ASLW Word arithmetic shift left 16 bit shift ASRR Multi bit arithmetic shift right ASRW Word arithmetic shift right 16 bit shift CLB Count leading bits ones or zeros EOR Bit wise exclusive OR EXTRACT Extract signed bit field EXTRACTU Extract unsigned bit field INSERT Insert bit field LSLL Multi bit ...

Page 46: ...tions and not for any other fractional moves such as MOVE F These instructions move data from DALU register s to memory The limiting operation takes place in two steps first calculating the Ln bit when a previous ALU instruction wrote to a register and second transferring the data from that register with a MOVES instruction The transferred data is limited if the Ln bit is set 2 2 1 6 1 Calculating...

Page 47: ...te the Ln bit before the value is written to memory using a MOVES x operation 2 2 1 6 2 Limiting with the MOVES Instructions The second stage of limiting occurs with the execution of a MOVES instruction A limited value is substituted for the transferred data if the Ln bit of that register was set The data in the register is not changed only the data transferred Having four limiters for each bus al...

Page 48: ...uction Memory Register New Value Comments move w 0030 r0 r0 0000 0020 R0 holds the address for the first move to memory moveu w 7fff d0 h d0 7fff 0000 d0 h set with the most positive 2 s complement number moveu w 7fff d1 h d1 7fff 0000 d1 h set with the most positive 2 s complement number add d0 d1 d3 d3 1 00 fffe 0000 L3 bit set from overflow move f d3 r0 0020 fffe No limiting from the move instr...

Page 49: ...he decimal or binary point is always located immediately to the right of the most significant bit of the high portion For integer values it is always located immediately to the right of the least significant bit LSB of the value Figure 2 3 shows the location of the decimal point binary point bit weighting and operand alignment for different fractional and integer representations supported on the S...

Page 50: ...stent with the size of the destination the sign of the register and the MSB of the extension 2 2 2 2 1 Signed Fractional In this format without extension bits 39 32 the N bit operand is represented using the 1 N 1 bit format 1 sign bit N 1 fractional bits Signed fractional numbers lie in the following range 1 0 SF 1 0 2 N 1 For words and long word signed fractions the most negative number that can...

Page 51: ...s 239 represented by 80 0000 0000 2 2 2 2 3 Unsigned Integer Unsigned integer numbers may be thought of as positive only The unsigned numbers have nearly twice the magnitude of a signed number of the same length Unsigned integer numbers lie in the following range 0 UI 2N 1 The binary word is interpreted as having a binary point immediately to the right of the LSB The most positive 16 bit unsigned ...

Page 52: ...ion 2 2 2 4 Division Fractional division of both positive and signed values is supported using the DIV instruction The dividend numerator is a 32 bit fraction and the divisor denominator is a 16 bit fraction For a detailed description of the DIV instruction see Appendix A SC140 DSP Core Instruction Set 2 2 2 5 Unsigned Arithmetic Unsigned arithmetic can be performed on the SC140 core architecture ...

Page 53: ...isabled if arithmetic saturation mode is selected 2 2 2 6 1 Convergent Rounding Convergent rounding also called round to nearest even number is the default rounding mode It is selected when the rounding mode RM bit in the SR is cleared The traditional rounding method rounds up any value greater than one half and rounds down any value less than one half However the question arises as to which way o...

Page 54: ...SB of Do h 1 then round up add 1 to D0 h D0 l is always clear performed during RND MPYR and MACR X X X X X X X X X X 0 1 0 0 0 1 1 X X X X X X 39 32 31 16 15 0 D0 e D0 h D0 l 0 X X X X X X X X X X 0 1 0 0 0 0 0 0 0 0 39 32 31 16 15 0 D0 e D0 h D0 l Before Rounding After Rounding X X X X X X X X X X 0 1 0 0 1 1 1 0 X X X X X 39 32 31 16 15 0 D0 e D0 h D0 l 1 X X X X X X X X X X 0 1 0 1 0 0 0 0 0 0 ...

Page 55: ...less than one half are rounded down Therefore a small positive bias is introduced For no scaling the higher portion HP of the register is bits 39 16 the low portion LP is bits 15 0 The HP is incremented by one bit if the LP was 1 2 The HP is left alone if the LP was 1 2 After rounding the LP is cleared If scaling down is selected the HP is bits 39 17 and the LP is bits 16 0 If scaling up is select...

Page 56: ... the LSB of D0 h 1 then round up add 1 to D0 h D0 l is always cleared performed during RND MPYR and MACR X X X X X X X X X X 0 1 0 0 0 1 1 X X X X X X 39 32 31 16 15 0 D0 e D0 h D0 l 0 X X X X X X X X X X 0 1 0 0 0 0 0 0 0 0 39 32 31 16 15 0 D0 e D0 h D0 l Before Rounding After Rounding X X X X X X X X X X 0 1 0 0 1 1 1 0 X X X X X 39 32 31 16 15 0 D0 e D0 h D0 l 1 X X X X X X X X X X 0 1 0 1 0 0 ...

Page 57: ... dependent on arithmetic saturation mode to the extent that scaling is not considered in the Ln bit calculation if arithmetic saturation mode is on See Section 2 2 1 7 Scaling and Arithmetic Saturation Mode Interactions on page 2 16 for more information The arithmetic saturation mode is always disabled during the execution of the following instructions TFR TFRT TFRF MAX MAXM MIN ADD2 SUB2 DIV SBC ...

Page 58: ...C Implementation Table 2 15 Fractional Signed and Unsigned Two s Complement Multiplication Instruction Description MPYSU MACSU Fractional multiplication and multiply accumulate with signed unsigned operands MPYUS MACUS Fractional multiplication and multiply accumulate with unsigned signed operands MPYUU MACUU Fractional multiplication and multiply accumulate with unsigned unsigned operands DMACSS ...

Page 59: ...recision number with the unsigned low portion of the other double precision number The Signed x Signed operation is used to multiply or multiply accumulate the two signed high portions of two signed double precision numbers The TFRx instructions in parentheses are optional instructions that are used only in case all 64 bits of the result are needed Otherwise the result is truncated to a 32 bit fra...

Page 60: ...ion 2 2 2 8 2 Integer Multi Precision Arithmetic A set of DALU operations is provided for integer multi precision multiplications When these instructions are used the multiplier accepts some combinations of two s complement signed and unsigned formats Both signed and unsigned multi precision multiplication are supported Table 2 16 lists these instructions Table 2 16 Integer Signed and Unsigned Two...

Page 61: ...cision number with the unsigned low portion of the other double precision number The Signed x Unsigned and Unsigned x Signed operations are used to multiply or multiply accumulate the signed high portion of one double precision number with the unsigned low portion of the other double precision number This example generates only a 32 bit integer Figure 2 10 Signed Integer Double Precision Multiplic...

Page 62: ...rations is provided for Viterbi decoding kernels A special MAX2VIT operation is defined This instruction functions as a regular MAX2 instruction and is used to transfer two 16 bit maximum signed values In addition the MAX2VIT instruction updates two Viterbi flags VFs which reside in the status register as described in Section 3 1 1 Status Register SR on page 3 1 Complementary AGU move operations a...

Page 63: ...er SP whenever needed 2 3 1 AGU Architecture The major components of the AGU are listed below Eight low bank address registers R0 R7 Eight high bank address registers R8 R15 or alternatively eight base address registers B0 B7 Two stack pointers NSP ESP only one of which is active at a time SP Four offset registers N0 N3 Four modifier registers M0 M3 A modifier control register MCTL Two address ari...

Page 64: ... as setting clearing changing or testing bits in a destination according to an immediate mask operand Data is loaded into the BMU over the data memory buses XDBA or XDBB The result is written back over XDBA or XDBB to the destinations in the next cycle All bit mask instructions are typically executed in two cycles and work on 16 bit data This data can be a memory location or a portion high or low ...

Page 65: ...e identical Each contains a 32 bit full adder called an offset adder which can perform the following Add or subtract two AGU registers Add an immediate value Increment or decrement an AGU register Add the PC Add with reverse carry The offset adder can also perform compare or test operations as well as arithmetic and logical shifts The offset values added in this adder can be pre shifted left by 1 ...

Page 66: ...regular or multiple wrap around and reverse carry addressing Automatic updating of address registers is available when using address register indirect addressing Figure 2 13 AGU Programming Model ADDRESS REGISTERS OFFSET MODIFIER and MCTL REGISTERS 0 31 N0 N1 0 31 N2 N3 R0 R2 R3 R1 R4 R5 R6 R7 SP NSP ESP 0 31 M0 M1 M2 MCTL M3 ADDRESS REGISTERS BASE ADDRESS REGISTERS 0 31 R8 B0 R10 B2 R11 B3 R9 B1 ...

Page 67: ...register can be post updated according to the addressing mode selected If an address register is updated one of the modifier registers Mj can be used to specify the type of update arithmetic Offset registers Ni are used for post incrementing and indexing by offset The address register modification can be performed by either of the two AAUs Most addressing modes modify the selected address register...

Page 68: ...of an offset register can specify the offset into a table or the base of the table for indexed addressing or can be used to step through a table at a specified rate for example five locations per step for waveform generation Each address register can be used with each offset register For example R0 can be used with N0 N1 N2 or N3 for offset address calculations The signed value in an offset regist...

Page 69: ...ddressing modes can also be used freeing the B register to be used as an additional linear address register The high bank of the address register file R8 R15 can only be used in linear addressing mode Each Rn n 8 15 is available only if the corresponding Bn 8 register is not used since both Rn and Bn 8 are mapped to the same physical register MCTL is initialized to zero at reset setting a default ...

Page 70: ...es specify that the address register is used to point to a memory location The term indirect is used because the register contents are not the operand itself but rather the operand address These addressing modes specify that an operand is in a memory location and specify the effective address of that operand These references are classified as memory references The term index refers to an offset st...

Page 71: ... is determined by programming the MCTL register The contents of the Rn and Rm registers are unchanged An example is move l r0 r2 d6 Here the access width is four so the value in r2 is shifted left two bits before adding to the address in r0 Note that only address registers R0 R7 can be used as Rm Short Displacement Rn x The operand address is the sum of the contents of the address register Rn and ...

Page 72: ...ches BRA In the PC relative addressing mode the instruction encoding contains a signed displacement operand The operand address is obtained by left shifting multiplying by two the displacement and adding the result to the value of the program counter PC The operand is left shifted because the addresses of the program instructions are word aligned and memory addressing is in units of bytes The arit...

Page 73: ... This addressing mode requires a two word instruction extension The immediate data is a 32 bit operand This reference is classified as a program reference An example is move l f00d0d01 n0 The 32 bit unsigned value is moved to the general register n0 Absolute Word Address This addressing mode requires a one word instruction extension The operand address occupies 16 bits in the instruction operation...

Page 74: ...alignment Each access to the memory generated by the core should be aligned according to the access type If the alignment rule is violated erroneous data may be fetched from the memory In addition an exception may be generated to identify that an unaligned access occurred For more information see Section 5 8 Exception Processing on page 5 46 Table 2 18 Access Width Support for Address and Register...

Page 75: ... Program Control Unit Register Reference D DALU Register Reference A AGU Register Reference P Program Memory Reference X Data Memory Reference Access Type Aligned Address Byte access Any address Word access Multiple of 2 Long word access Multiple of 4 Two long word access Multiple of 8 Table 2 20 Addressing Modes Summary Addressing Modes R0 R7 Uses MCTL Operand Reference Assembler Syntax S C D A P...

Page 76: ...rt Displacement Rn x Word Displacement Rn xxxx Yes Rn x Rn xxxx SP Short Displacement SP xx SP xx SP Word Displacement SP xxxx SP xxxx PC Relative PC Relative with Displacement xx 8 bits xxx 10 bits xxxx 16 bits xxxxx 20 bits Special Immediate Short Data Immediate Word Data Immediate Long Data xx 5 6 or 7bits xxxx 16 bits xxxxxxxx 32 bits Absolute Word Address Absolute Long Address xxxx 16 bits xx...

Page 77: ...TL register Address modification is performed in the hardware by propagating the carry from each pair of added bits in the reverse direction from the MSB end toward the LSB end For the Ni addressing mode reverse carry is equivalent to Bit reversing the contents of Rn redefining the MSB as the LSB the next MSB as bit 1 and so on Shifting the offset value in Ni left by 0 1 2 or 3 according to the ac...

Page 78: ...er boundary The following constraints apply 1 For proper modulo addressing if an offset Ni is used in the address calculation the 32 bit absolute effective value Ni must be less than or equal to Mj where effective means the programmed Ni is multiplied by the access width For example move w r0 n0 d0 translates to the restriction 2 n0 Μj and move l r0 d0 translates to 4 Mj If effective Ni Mj the res...

Page 79: ...the lower and upper boundaries The upper boundary is the lower boundary plus the modulo size minus one base address M 1 The size of the modulo buffer must be aligned to be a multiple of the access width If the modulus is less than the access width the data accessed as well as the address calculations are undefined If an offset Ni is used in the address calculations it is not required to be less th...

Page 80: ...led description of the operations is provided in Appendix A SC140 DSP Core Instruction Set Table 2 22 Modulo Register Values for Wrap Around Modulo Addressing Mode Modifier Mj Address Calculation Arithmetic 0000 0001 Multiple Wrap around Modulo 2 0000 0003 Multiple Wrap around Modulo 4 0000 0007 Multiple Wrap around Modulo 8 7FFF FFFF Multiple Wrap around Modulo 231 FFFF FFFF Linear Table 2 23 AGU...

Page 81: ...since only one execution unit exists for these instructions A subgroup of the bit mask instructions BMTSET supports hardware semaphores For more information see Section 2 3 6 1 Bit Mask Test and Set Semaphore Support Instruction DECGEA AGU Decrement and set T if result is equal to or greater than zero INCA AGU Increment register affected by the modifier mode LSRA AGU Logical shift right 32 bit SUB...

Page 82: ...memory subsystem signals the core of a write failure if a memory access that is initiated by another master source intervenes between the read and the write accesses of the BMTSET operation As a result of the non exclusive write indication the T bit is set signalling that the resource may not be available thereby avoiding a hazard condition Table 2 24 AGU Bit Mask Instructions BMU Instruction Desc...

Page 83: ...dress phase of the read and write accesses associated with the BMTSET instruction an output of the core is asserted This assertion indicates that the read and the following write are part of a read modify write sequence During the data phase of the write access a core input provides the core with the result of the access de asserted write failed 2 3 7 Move Instructions The SC140 instruction set su...

Page 84: ...ctional word to from memory MOVE L Move long MOVE W Move integer word to from memory or immediate to register or memory MOVEc Conditional move between address registers MOVES 2F Move two fractional words to memory with scaling and limiting enabled MOVES 4F Move four fractional words to memory with scaling and limiting enabled MOVES F Move fractional word to memory with scaling and limiting enabled...

Page 85: ...ut in the high portion of the data register sign extended to the extension and zero filled in the low portion MOVE L and MOVE 2L may also be considered fractional moves since alignment in the destination register is the same for integer long moves and fractional long moves A schematic representation of fractional moves from memory to 40 bit data registers is shown in Figure 2 17 0 39 8 MOVE B sign...

Page 86: ...2 D3 In this case let the address in R0 be noted as A0 The fractional word in location A0 then goes to D0 the word in A0 2 goes to D1 the word in A0 4 goes to D2 and the word in A0 6 goes to D3 The addresses increment by two since the addressing unit is always a byte Moves to or from more than one register are treated according to the same principle A special MOVE L instruction supports moving dat...

Page 87: ...address bus B XABB and 64 bit data memory data bus B XDBB Control signals such as read and write access strobes as well as access width control The SC140 does not specify a memory subsystem architecture only the minimum requirements for correct execution of SC140 code Listed below are requirements for all memory designs that interface with the SC140 core The SC140 core supports only unified memory...

Page 88: ...re illegal and the result is undefined The memory subsystem can issue an imprecise interrupt to the core The use of this interrupt is optional 2 4 1 SC140 Endian Support The term little endian is defined as a computer architecture such that given a multi byte operand representation bytes at lower addresses have lower numeric significance Each word is stored little end first In little endian mode t...

Page 89: ...s the data busses between the SC140 core and the memory Figure 2 20 Basic Connection between SC140 Core and Memory 2 4 1 2 Memory Organization Different types of data are stored differently in memory for each of the two endian modes However the data retains the same meaning For example 64 bits of data can be represented by any of the following Eight 8 bit bytes Four 16 bit numbers Two 32 bit numbe...

Page 90: ... accessed with three types of data Long type access writing or reading 32 bit operands Word type access writing or reading 16 bit operands Byte type access writing or reading 8 bit operands Figure 2 22 shows an example of data transfer in big and little endian modes Table 2 26 Data Representation in Memory Representation Type Value Eight 8 bit bytes A0 0a A1 0b A2 0c A3 0d A4 0e A5 0f Four 16 bit ...

Page 91: ... bus bytes to different memory addresses for each supported endian mode Big Endian Little Endian MOVE B A0 D0 MOVE B A2 D0 MOVE W A8 D0 MOVE L A16 D0 xxxx xxxx xxxx xx0a xxxx xxxx xxxx xx0c xxxx xxxx xxxx 0102 xxxx xxxx 1122 3344 64 bit XB BUS 64 bit XA BUS SC140 Core Memory Instructions Data Bus Contents 8 16 10 24 18 32 20 0 1 2 3 4 5 6 7 0 0a 0b 0c 0d 0e 0f 01 02 03 04 05 06 07 08 11 22 33 44 c...

Page 92: ...treats them both like a string of eight bytes The bus structure for the little endian mode corrects for both cases to ensure that register data is stored at the same address for both modes As an example of the problem that arises if a correction is not made consider the following case The instruction move 2w d0 d1 a8 transfers two integer words from data registers d0 and d1 to memory at address a8...

Page 93: ...n big and little endian modes For more information about the VSL instructions refer to Table 2 27 on page 2 64 and Appendix A Viterbi Shift Left Move AGU VSL on page A 422 Big Endian Little Endian a MOVE 2W A8 D0 D1 b MOVE 4W A8 D0 D1 D2 D3 c MOVE 2L A16 D0 D1 64 bit XB BUS 64 bit XA BUS xxxx xxxx 0102 0304 0102 0304 0506 0708 1122 3344 ccdd eeff xxxx xxxx 0304 0102 0708 0506 0304 0102 ccdd eeff 1...

Page 94: ...dress 0a instruction e1f1 word address 0c instruction a2b2 word address 0e instruction c2d2 word address 10 instruction e2f2 These are to be placed in memory as shown in the following figure Figure 2 24 Program Memory Organization in Big and Little Endian Modes The assembler outputs a byte stream to the loader and therefore corrects for the byte address reversal inside each 16 bit instruction to a...

Page 95: ...ittle Endian Big Endian a0b0 c0d0 e0f0 a1b1 c1d1 e1f1 a2b2 c2d2 e2f2 a3b3 c3d3 e3f3 a1b1 e0f0 c0d0 a0b0 c2d2 a2b2 e1f1 c1d1 e3f3 c3d3 a3b3 e2f2 Memory MOVE 4W from address 00 MOVE L from address 08 64 bit XB BUS 64 bit XA BUS Instructions Data Bus Contents Data Bus Contents 64 bit XB BUS 64 bit XA BUS SC140 Core 128 bit P BUS c2d2_a2b2_e1f1_c1d1_a1b1_e0f0_c0d0_a0b0 Memory System Changes Big Endian...

Page 96: ...ord shifted left by one bit See Appendix A for more detailed information Table 2 27 Move Instructions in Big and Little Endian Modes Instruction Register Operands Big Endian Little Endian MOVE B MOVEU B A0 A A0 A MOVE W MOVEU W A0 A A1 B A0 B A1 A MOVE 2W A0 A A1 B A2 C A3 D A0 B A1 A A2 D A3 C MOVE 4W A0 A A1 B A2 C A3 D A4 E A5 F A6 G A7 H A0 B A1 A A2 D A3 C A4 F A5 E A6 H A7 G MOVE L MOVEU L M...

Page 97: ...A3 C MOVE 4F MOVES 4F A0 A A1 B A2 C A3 D A4 E A5 F A6 G A7 H A0 B A1 A A2 D A3 C A4 F A5 E A6 H A7 G Table 2 27 Move Instructions in Big and Little Endian Modes Continued Instruction Register Operands Big Endian Little Endian 0 39 32 A 16 B L1 L0 Example MOVE L D0 E D1 E A0 D0 D1 0 39 32 A B C D E F G H Example MOVE 2L D0 D1 R0 D0 D1 0 39 32 16 A B Example MOVE F D0 R0 D0 0 39 32 16 A B C D Examp...

Page 98: ... A6 E A7 F A0 B A1 A A2 D A3 C A4 F A5 E A6 H A7 G VSL 4F A0 C A1 D A2 A A3 B A4 G A5 H A6 E A7 F A0 B A1 A A2 D A3 C A4 F A5 E A6 H A7 G VSL 2W A0 C A1 D A2 A A3 B A0 B A1 A A2 D A3 C VSL 2F A0 C A1 D A2 A A3 B A0 B A1 A A2 D A3 C Table 2 27 Move Instructions in Big and Little Endian Modes Continued Instruction Register Operands Big Endian Little Endian 0 39 16 A B C D E F G H Example VSL 4W D2 D...

Page 99: ...tack Support Instructions in Big and Little Endian Modes Instruction Register Operands Big Endian Little Endian Single POP POPN PUSH PUSHN A0 A A1 B A2 C A3 D A0 D A1 C A2 B A3 A Double POP POPN PUSH PUSHN A0 A A1 B A2 C A3 D A4 E A5 F A6 G A7 H A0 D A1 C A2 B A3 A A4 H A5 G A6 F A7 E Table 2 29 Bit Mask Instructions in Big and Little Endian Modes Instruction Register Operands Big Endian Little En...

Page 100: ...ed that the stack access is to address A0 Table 2 31 Control Instructions in Big and Little Endian Modes Table 2 30 Non Loop Change of Flow Instructions in Big and Little Endian Modes Instruction Register Operands Big Endian Little Endian BSR BSRD JSR JSRD RTE RTED A0 A A1 B A2 C A3 D A4 E A5 F A6 G A7 H A0 D A1 C A2 B A3 A A4 H A5 G A6 F A7 E RTS RTSD RTSTK RTSTKD A0 A A1 B A2 C A3 D A0 D A1 C A2...

Page 101: ... It reflects and controls the following Core working mode Normal or Exception State of the four hardware loops and type of the currently executing loop Current interrupt priority level IPL of the core Overflow exceptions enabled or disabled Interrupts enabled or disabled Viterbi flags Scaling rounding and arithmetic saturation modes Numeric range of moved data after scaling Result true or false of...

Page 102: ...RESET 0 0 0 0 0 0 0 0 1 1 1 0 0 1 0 0 BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 BIT 0 VF3 VF2 VF1 VF0 S S1 S0 RM SM T C TYPE rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 3 1 Status Register Description Name Description Settings SLF Bit 31 Short Loop Flag Indicates when set that the active loop is a short loop which means that it contains only one or two...

Page 103: ...ore reset 0 Hardware loop 1 not enabled 1 Hardware loop 1 enabled R Bits 26 24 Reserved I2 I0 Bits 23 21 Interrupt Mask Bits Reflect the current interrupt priority level IPL of the core Only non maskable interrupts or interrupts with an IPL higher than the current interrupt mask value can interrupt the core The current IPL of the core can be changed under software control At the start of an ISR th...

Page 104: ...ich ensures that interrupts are masked immediately and can be cleared with the EI instruction This bit is cleared at core reset 0 Interrupts enabled 1 Interrupts disabled EXP Bit 18 Exception Mode Bit Selects the active stack pointer and working mode of the core This bit is set at core reset 0 Normal working mode active SP is NSP 1 Exception working mode active SP is ESP R Bits 17 12 Reserved VF3 ...

Page 105: ... instructions See Section 2 2 1 5 Scaling and Section 2 2 1 6 Limiting for more information The scaling mode also affects the MAC rounding bit position Correct rounding is maintained when different portions of the registers are read out to the data memory buses For more information see Section 2 2 2 6 Rounding Modes During arithmetic saturation mode the scaling bits are ignored for most DALU instr...

Page 106: ...endix A SC140 DSP Core Instruction Set lists arithmetic saturation as a condition if appropriate This bit is cleared at core reset 0 Arithmetic saturation mode not selected 1 Arithmetic saturation mode selected T Bit 1 True Bit Indicates whether the condition being tested by a compare or test instruction is true or false The T bit is affected by all instructions that check a condition such as CMPx...

Page 107: ...nipulation as well as rotate and shift instructions The carry bit usually holds the value of the last shifted bit If more than one instruction in an execution set affects the carry bit according to the instruction definition then the carry bit is updated by the last instruction in assembly source order that actually executes while the other instructions do not affect the carry bit If no carry affe...

Page 108: ...plained in Section 3 1 2 1 Clearing EMR Bits The NMI bit cannot be set by the user It is cleared at reset 0 No NMI service executing 1 NMI service executing DOVF Bit 2 DALU Overflow Bit Indicates that an overflow from 40 bits occurred during a DALU operation or that arithmetic saturation occurred in arithmetic saturation mode overflow from 32 bits Whenever there is an overflow an exception is gene...

Page 109: ... No execution set rule violated 1 Execution set rule violated ILIN Bit 0 Illegal Instruction Indicates that one or more of the instruction opcodes received from program memory are not in the SC140 instruction set Holes in operand tables are detected as illegal Both opcodes for instructions considered reserved and holes in operand tables are determined to be illegal Whenever an illegal instruction ...

Page 110: ... BMCLR instruction in the interrupt service routine of an overflow exception which is activated when DOVF is set Example 3 1 Clearing an EMR Bit BMCLR fffb EMR L This instruction writes back a zero to every bit in EMR L except for DOVF which is written with the same value it contained when it was read Because DOVF was set to begin with it is now cleared Other bits set in EMR L are not affected Due...

Page 111: ...umber of different actions determined by a developer Non destructive access to the core and its peripherals Various means of profiling Program tracing 4 1 Debugging System With the JTAG or EOnCE interface the user can insert the SC140 core into a target system while retaining debug control The EOnCE module is used in DSP devices that are based on the SC140 to debug application software in real tim...

Page 112: ... lists the JTAG or EOnCE interface signals 4 2 1 Cascading Multiple SC140 EOnCE Modules in a SoC A typical SC140SoC uses the JTAG TAP controller for standard defined testing compatibilities and for single multi core EOnCE control and EOnCE interconnection control In a multi core device the EOnCE modules interconnect in a chain and are configured and controlled by the JTAG port see Figure 4 1 Table...

Page 113: ...nt JTAG instruction exist in the Jtag IR register Table 4 2 JTAG Instructions B4 B3 B2 B1 B0 Instruction Description 0 0 0 0 0 EXTEST Selects the Boundary Scan Register Forces a predictable internal state while performing external boundary scan operations 0 0 0 0 1 SAMPLE PRELOAD Selects the Boundary Scan Register Provides a snapshot of system data and control signals on the rising edge of TCK in ...

Page 114: ...tion the ENABLE_EONCE and the CHOOSE_EONCE instructions should be performed 0 1 0 0 0 RUNBIST Selects the BIST registers Allows you to generate a built in self test for checking the system circuitry 0 1 0 0 1 CHOOSE_EONCE Selects the EOnCE registers Allows to select EOnCE targets in devices with multiple EOnCE modules This instruction is activated before the ENABLE_EONCE and DEBUG_REQUEST instruct...

Page 115: ...tate an instruction register scan or a data register scan can be issued to transition through the appropriate states Table 4 3 JTAG Scan Paths Select DR Scan Path Select IR Scan Path Select DR_SCAN Select IR_SCAN Capture DR Capture IR Shift DR Shift IR Exit1 DR Exit1 IR Update DR Update IR Test Logic Reset Run Test Idle Select DR Scan Capture DR Shift DR Exit1 DR Pause DR Exit2 DR Update DR Select...

Page 116: ...r Read and write internal EOnCE registers 4 2 4 Enabling the EOnCE Module The CHOOSE_EONCE mechanism allows integration of multiple SC140 cores and thus multiple EOnCE modules on the same device Using the CHOOSE_EONCE instruction you can selectively activate one or more of the EOnCE modules on the device The EOnCE modules selected by the CHOOSE_EONCE instruction are cascaded as shown in Figure 4 3...

Page 117: ...llowing steps see Figure 4 4 1 Execute the CHOOSE_EONCE command in the JTAG 2 Send the data showing which EOnCE is chosen This command enables the JTAG to manage multiple EOnCE modules in a device 3 Execute the ENABLE_EONCE command in the JTAG 4 Write the EOnCE command into the EOnCE Command register ECR That is the host enters the JTAG TAP state machine into the shift dr state and then gives the ...

Page 118: ...ister hold the read data The rest of the bits are read as zeros This organization shortens the access time to the EOnCE registers if the access is only to those registers and no other devices on the JTAG chain are accessed on that transaction In such a case reads and writes can be done only to the actual register length In case other devices participate in the transaction the full shift register l...

Page 119: ...EOnCE registers through JTAG A EOnCE register write operation through JTAG 0 7 TDO TDI don t care bits relevant bits B EOnCE register read capture operation through JTAG 0 7 TDO TDI bits captured as zero relevant bits 0 23 EOnCE register EOnCE register 24 zeros internal shift register internal shift register ...

Page 120: ...d EOnCE event signals EE0 EE5 are available as well as one data event EED signal and two event counter EC signals The two event counter signals EC0 and EC1 allow the event counter to count off core events such as cache hits misses memory contention external wait states etc These inputs are assumed synchronous to the core clock and support a counting rate up to the core frequency EC0 and EC1 use is...

Page 121: ...etermine whether they continue to operate in debug state Two actions are possible in debug state Execute a Single Step The core leaves debug state for one cycle The currently fetched execution set is executed after which the core then returns to debug state and the PSEQ proceeds to the next execution set Insert an Instruction from the JTAG port or EOnCE A MOVE JMP or BRA instruction can be inserte...

Page 122: ...ter is read by JTAG and the TRSINT bit in the EMCR register is set The IME bit in the EMCR register is set enabling any of the cases that cause the core to enter debug state 4 3 5 Executing an Instruction while in Debug State When the core is in debug state the host connected to the JTAG port can execute a subgroup of the SC140 instruction set in the core This is done by eliminating the fetch and ...

Page 123: ... memory of the ERCV register The ERCV register is written with the program data Write a command into the ECR register with the address of the CORE_CMD register The CORE_CMD register is selected Write into the CORE_CMD register with a MOVE instruction from the ERCV register to a core register The core register is written with the program data Write into the CORE_CMD register with a MOVE instruction...

Page 124: ...ST command from the host through the JTAG port EE An EE signal EE0 EE5 or EED is asserted when programmed as an input Counter The 31 bit event counter reaches zero EDCD The data event detection channel EDCD detects specified values on the data memory data buses EDCA An address event detection channel EDCA0 EDCA5 detects specified values on the data memory address buses or in the program counter Ex...

Page 125: ...D Enable EDCAs 4 3 9 Event and Action Summary Table 4 5 summarizes the events and their possible actions they may cause depending on the EOnCE programming Table 4 5 EOnCE Event and Action Summary Event type Counted trace trigger Debug state Debug exception Enable tracing Disable tracing Other actions DEBUG DEBUGEV JTAG DEBUG_REQ EE Controls when corresponding EDCD and EDCAs are enabled Enable the ...

Page 126: ...e to read and write the EOnCE registers Event Counter Counts various events Event Detection Unit EDU Generates events when it detects predefined values on the data memory address buses the program counter the data memory data buses Event Selector Controls what action is taken when events or a combination of simultaneous events occurs Trace Unit Performs non intrusive program tracing during program...

Page 127: ... register set is shown in Table 4 6 Table 4 6 EOnCE Controller Register Set Register Name Description ECR EOnCE command register ESR EOnCE status register EMCR EOnCE monitor and control register ERCV EOnCE receive register ETRSMT EOnCE transmit register EE_CTRL EE signals control register CORE_CMD EOnCE core command register PC_EXCP PC of the execution set causing illegal or overflow exception TCK...

Page 128: ...nnel Tracing into the trace buffer Execution of the DEBUGEV instruction Off core events from the EC input signals When the core is in debug state the event counter does not count core clocks The event counter programming model includes three registers Event counter register ECNT_CTRL Downcount event counter value register ECNT_VAL Extension counter value register ECNT_EXT PC_NEXT PC of the next ex...

Page 129: ...on the event selector Extended count When the counter reaches zero it wraps around to 7FFF FFFF and continues to count The extension counter is incremented No EOnCE event is generated Table 4 7 shows the event counter register set The functionality of the event counter registers is described in Section 4 8 Event Counter Registers Table 4 7 Event Counter Register Set Register Name Description ECNT_...

Page 130: ... six instances of an Address Event Detection Channel EDCA one Data Event Detection Channel EDCD and an event selector ES In addition the EDU has an interface that supports adding two additional EDCAs as external modules outside the EOnCE thus enabling to expand the EOnCE address detection capabilities The possible events generated by the EDU are Signal to the event selector entry to debug state de...

Page 131: ...nd failed Figure 4 10 shows the event detection unit block diagram Figure 4 10 Event Detection Unit Block Diagram Address Buses Data Buses EDCA 5 EDCA 2 EDCA 1 EDCA 0 EDCD EventD Event0 Event1 Event2 Event5 Count event Count event from Counter EED EE 5 0 Event Selector Debug State Debug Exceptio Enable Trace Disable Trace XDBxx PC XABA XABB Event6 7 external from EDCA6 7 ext ...

Page 132: ...11 shows the EDCA block diagram Figure 4 11 EDCA Block Diagram Two 32 bit comparators are used to compare the core address buses and the reference values programmed into the reference value registers EDCAi _REFA and EDCAi _REFB Each comparator is capable of detecting one of the following four conditions Equal Not equal Less than XABA XABB Memory Bus and Reference Value Register A Comparator A Even...

Page 133: ...own in Table 4 8 The functionality of the EDCA registers is described in Section 4 9 1 Address Event Detection Channel EDCA Table 4 8 EDCA Register Set Register Name Description EDCAi_CTRL EDCA control register EDCAi_REFA EDCA reference value register A EDCAi_REFB EDCA reference value register B EDCAi_MASK EDCA mask register ...

Page 134: ... Figure 4 12 EDCD Block Diagram The EDCD register set is shown below Table 4 9 EDCD Register Set The functionality of the EDCD registers is described in Section 4 9 2 Data Event Detection Channel EDCD Register Name Description EDCD_CTRL EDCD control register EDCD_MASK EDCD mask register EDCD_REF EDCD reference value register XDBAW XDBAR Control Register Reference Value Register Two Comparators XDB...

Page 135: ...binations with other events in the event selector Setting the debug reason bits in ESR and the event status bits in EMCR EDCA6 and EDCA7 do not have an EE pin associated with them 4 5 4 Event Selector ES The ES selects the source for various debugging operations The possible sources that can be selected are Outputs of EDCA instances Outputs of optional external EDCA events Output of the EDCD Outpu...

Page 136: ... the event selector registers is described in Section 4 10 Event Selector ES Registers 4 5 5 Trace Unit The trace unit is used to store information about a running application without halting its execution The user can select the addresses to be stored in the trace unit from a wide selection that includes Change of flow instructions All Change of flow instructions Call return from subroutine instr...

Page 137: ...terrupts Operates during real time processing Can be read by the debugging hardware during execution state as well as debug state when the trace buffer is disabled The trace buffer can be enabled by the host core software or by an EOnCE event generated by various ES configurations The following addresses can be traced The PC of an execution set containing a taken change of flow instruction followe...

Page 138: ...ddresses of the change of flow event are traced In case of a delayed change of flow instruction the source address is also that of the change of flow instruction The following change of flow instructions are those that can be traced BT BF BTD BFD BRA BRAD JMP JMPD JT JF JTD JFD JSR JSRD BSR BSRD RTS RTSD RTSTK RTSTKD RTE RTED Address Strobes Data Trace Unit Trace Unit Controller Control Register R...

Page 139: ...e location pointed to by the TB_RD register The TB_RD pointer is incremented after every read access to the trace buffer and is cleared when the trace buffer is enabled Due to a pre fetch mechanism when the user reads the location pointed to by the TB_RD register by reading the TB_BUFF register the TB_RD pointer is already three stages ahead As a result of this pre fetch mechanism there is a restr...

Page 140: ...a is the derivative dependent register base address Most EOnCE memory mapped registers allow only 32 bit accesses except the status monitor and control registers ESR EMCR EE_CTRL EDCA 0 5 _CTRL EDCD_CTRL ECNT_CTRL ESEL_CTRL and TB_CTRL The latter support 16 bit accesses which enable the use of bit mask operations There is only one access per execution set for all EOnCE registers When a 16 bit acce...

Page 141: ...CTRL EE signals control register 07 R 32 32 PC_EXCP PC of VLES causing Illegal or Overflow exception 08 NO 32 32 PC_NEXT PC of next execution set 09 NO 32 32 PC_LAST PC of last execution set 0A R 32 32 PC_DETECT PC breakpoint detection register Reserved addresses 10 R W 16 32 EDCA0_CTRL EDCA0 control register 11 R W 16 32 EDCA1_CTRL EDCA1 control register 12 R W 16 32 EDCA2_CTRL EDCA2 control regi...

Page 142: ...31 R W 32 32 EDCA1_MASK EDCA1 mask register 32 R W 32 32 EDCA2_MASK EDCA2 mask register 33 R W 32 32 EDCA3_MASK EDCA3 mask register 34 R W 32 32 EDCA4_MASK EDCA4 mask register 35 R W 32 32 EDCA5_MASK EDCA5 mask register 36 Reserved address 37 Reserved address 38 R W 16 32 EDCD_CTRL EDCD control register 39 R W 32 32 EDCD_REF EDCD reference value 3A R W 32 32 EDCD_MASK EDCD mask register Reserved a...

Page 143: ...nCE command may be lost due to a long core stall To ensure correct execution of a command the user should read a special ACK bit by shifting out the JTAG IR register together with the core status bits If the bit is set this indicates that the last EOnCE command was successfully executed This bit is reset each time a new command is shifted from the JTAG port to the EOnCE 49 R W 16 16 ESEL_DM Select...

Page 144: ...n the ESR For more information see Section 4 7 2 EOnCE Status Register ESR This bit can be polled by the core to see when the data is ready in the ERCV register or the application can configure EOnCE to generate a debug exception when the data is ready in the ERCV register See Section 4 7 4 EOnCE Receive Register ERCV for more information The RCV bit is automatically cleared by the EOnCE after the...

Page 145: ...G is the same as from software with the following exceptions The ETRSMT register is only readable only using the JTAG port The ERCV registers are only writable using the JTAG port PC_LAST and PC_NEXT can only be read by the JTAG port The CORE_CMD register can only be written by the JTAG port in debug state ...

Page 146: ... configuration of the ECR The shaded bits are reserved and should be initialized with zeros for future software compatibility Figure 4 15 EOnCE Command Register ECR Table 4 13 describes the ECR fields BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 BIT 0 R W GO EX REGSEL TYPE w w w w w w w w w w w w w w w w RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 4 13 ECR Description Name Description Settings R Bits 1...

Page 147: ...In this single step mode the core leaves debug state for one instruction cycle in order to execute the instruction If the EX bit is also set the core continues normal operation after executing the instruction When used together with writing to the CORE_CMD register the instruction written to the CORE_CMD register is executed and the core remains in debug state If the EX bit is set as well debug st...

Page 148: ...iting for a bus state indicates that the core is waiting for data on the bus to be transferred or that the core is disabled by the external system for example during memory BIST The core could be waiting for a bus in any of the processing states In such a case the CORES field will show waiting for a bus R Bit 29 Reserved PCKILL Bit 28 PC Killed This bit signifies that the last executed VLES was ab...

Page 149: ...nerally identifies the basic instruction set revision of the core It identifies the availability of new instructions and corrections to existing instructions along a binary upward compatible roadmap Changes in REVNO imply a software tools switch different software simulator and different host debugger Cores of different revisions can differ in their EOnCE programming model R Bit 20 Reserved CORETP...

Page 150: ...y the EOnCE when the core exits debug state or when the DIS bit in EMCR is reset by the user DREDCA6 Bit 6 Debug Reason is EDCA6 Set when the core enters debug state or executes a debug exception as a result of detection by the optional external EDCA6 It is cleared by the EOnCE when the core exits debug state or when the DIS bit in EMCR is reset by the user DREDCA5 Bit 5 Debug Reason is EDCA5 Set ...

Page 151: ...ondition that would have caused a debug exception the EOnCE will assert an external pin to an external interrupt controller When reset the core generates an internal debug exception for the same event This bit is for the use of the system engineer TRSINT Bit 24 Transmit Interrupt Can be set for interrupt driven data messaging If this bit is set and the TRSMT bit is reset by the EOnCE a debug excep...

Page 152: ...ceptions If they are used the interrupt request should be kept asserted until the core acknowledges it to the driver by some agreed SW protocol The core then must acknowledge that the interrupt was de asserted before the driver may assert it again DIS Bit 15 Debug Interrupt Status Sticky bit that is set by the EOnCE when a debug exception is generated When a user resets this bit all the debug reas...

Page 153: ...ue of the RCV bit informing the host when further data can be transmitted 4 7 5 EOnCE Transmit Register ETRSMT ETRSMT is a 64 bit shift register that can be read by the TDO output signal The register can be written by software as two 32 bit registers The ETRSMT register must be written in a specific order with the Least Significant Part first The Least Significant Part write is optional but the Mo...

Page 154: ... chip there may be limitations on the frequency of events that could be reflected on these pins due to the fact that I O pad frequency is usually substantially lower then the core frequency The logic definition of the behavior of the EE pins outputs assumes that the frequency of the I O pad is no less than 4 times slower than the core frequency In order to support this a toggle cannot occur in two...

Page 155: ...ta detection channel The user can configure EE0 to enable EDCA0 EE1 to enable EDCA1 EE2 to enable EDCA2 and so on EED can also be configured to enable EDCD For a description of how address event detection channels can be configured to be enabled upon an appropriate EE assertion see Section 4 9 1 1 EDCA Control Registers EDCAi_CTRL and Section 4 9 2 1 EDCD Control Register EDCD_CTRL 4 7 6 2 2 Using...

Page 156: ...e EDCA5 0 Output detection by EDCA5 1 Input enables EDCA5 EE4DEF Bits 9 8 EE4 Definition Programs the EE4 signal Programmed as an output of the EOnCE EE4 can indicate detection by EDCA4 working as a toggle It can also indicate that the ETRSMT register was written by the core Programmed as an input to the EOnCE according to the programming of the EDU and the ES EE4 can be programmed to enable EDCA4...

Page 157: ...E events 00 Output detection by EDCA1 01 Debug acknowledgement 10 Reserved 11 Input enables EDCA1 or generates an EOnCE event EE0DEF Bits 1 0 EE0 Definition Programs the EE0 signal Programmed as an output of the EOnCE EE0 can indicate detection by the EDCA0 working as a toggle Programmed as an input to the EOnCE according to the programming of the EDU and the ES the EE0 can be programmed to enable...

Page 158: ... The two prefix bits allow the instruction to use the high bank of registers Bits 15 and 14 in the second and third words encode the grouping word partition used by the core for execution set parsing In the case of a single instruction they do not need to be part of the CORE_CMD word For further details see Appendix A SC140 DSP Core Instruction Set In general core commands should not perform illeg...

Page 159: ...s are not defined This register is not affected by the operations performed during debug state When single stepping the value of PC_NEXT is valid after every step PC_NEXT will sample data only if the EOnCE is enabled see Section 4 4 EOnCE Enabling and Power Considerations If the EOnCE enters debug state without being enabled first the value of PC_NEXT is undefined PC_NEXT is read only and read thr...

Page 160: ... modes of event counter operation are determined by the ECNT_CTRL register 1 In the regular mode of operation the extension counter is disabled Thus when the event counter reaches zero the count event is generated and the counter stops its operation The maximum value that can be counted before generating the count event is 8000 0000 This can be achieved by writing 0000 0000 to the ECNT_VAL registe...

Page 161: ...destination address that is put into the trace buffer is followed by the value of the counter register The trace buffer can also be configured to write both the values of the counter and extension counter with each trace package For more information see Section 4 11 1 Trace Buffer Control Register TB_CTRL The counter can be configured to count the number of traced entries In case the tracing inclu...

Page 162: ...he EDCA1 0011 The event counter is disabled but is enabled when an event is detected by the EDCA2 0100 The event counter is disabled but is enabled when an event is detected by the EDCA3 0101 The event counter is disabled but is enabled when an event is detected by the EDCA4 0110 The event counter is disabled but is enabled when an event is detected by the EDCA5 0111 The event counter is disabled ...

Page 163: ...is register Software can write the register when new counting is started The MSB is always zero so the count is from 0000 0000 to 7FFF FFFF When the register is written the MSB should be written to zero for software compatibility 4 8 4 EC Signals The two event counter signals EC0 and EC1 allow the event counter to count off core events such as cache hits misses memory contention external wait stat...

Page 164: ...ity of these registers is described in the following sections 4 9 1 1 EDCA Control Registers EDCAi_CTRL EDCAi_CTRL is a 16 bit register used to control the behavior of the corresponding EDCA The following sections describe the functionality of each bit in the EDCAi_CTRL register Figure 4 21 displays the configuration of the EDCAi_CTRL register Figure 4 21 EDCA Control Register EDCAi_CTRL Table 4 1...

Page 165: ...ed by EDCA4 0110 EDCAi is disabled but is enabled when an event is detected by EDCA5 0111 EDCAi is disabled but is enabled when an event is detected by the optional external EDCA6 1000 EDCAi is disabled but is enabled when an event is detected by the optional external EDCA7 1001 EDCAi is disabled but is enabled when an event is detected by EDCD 1010 EDCAi is disabled but is enabled when a count ev...

Page 166: ...s Type Selection These bits are used to select the type of memory access that should be detected by the event detection channel The possible memory access types are Read access Write access Read or write access 00 Read access 01 Write access 10 Read or write access 11 Reserved BS Bits 1 0 Bus Selection Used to select which address bus or buses should be sampled for comparison by comparator A and o...

Page 167: ...address 0x101 in which case the EDCA will also identify it when the core is performing a MOVE W MOVE L etc to address 100 When detection occurs status bit EDCASTi is set by the EOnCE in the EMCR register Refer to Table 4 15 on page 4 41 4 9 1 2 EDCA Reference Value Registers A and B EDCAi_REFA EDCAi_REFB EDCAi_REFA and EDCAi_REFB are 32 bit registers used to hold reference values that are to be co...

Page 168: ...RL as the last action The following sections describe the functionality of these registers 4 9 2 1 EDCD Control Register EDCD_CTRL Figure 4 22 displays the configuration of EDCD_CTRL The shaded bits are reserved and should be initialized with zeros for future software compatibility Figure 4 22 EDCD Control Register EDCD_CTRL Table 4 20 describes the EDCD_CTRL fields BIT 15 14 13 12 11 10 9 8 7 6 5...

Page 169: ...on byte or quad byte When word access width is chosen the sixteen LSB bits of the EDCD_REF register are compared with each of the sixteen bits of the masked data One two or four comparisons are performed with logical OR among them depending on the access resolution word double word or quad word When long access width is chosen then the 32 LSB bits of the EDCD_REF register are compared with each of...

Page 170: ...s detected by the optional external EDCA6 1000 EDCD is disabled but is enabled when an event is detected by the optional external EDCA7 1001 EDCD is disabled but is enabled when a count event is detected 1010 EDCD is disabled but is enabled when EED is asserted and EED is programmed as input in the EE_CTRL register 1011 EDCD is enabled but will be disabled when EED is negated in both cases EED is ...

Page 171: ...e is 16 or 8 bits long the mask value must be duplicated 2 or 4 times respectively to fill the mask register Since data buses are 64 bits the 32 bit EDCD_MASK register is masked on both 32 LSB and 32 MSB bits of the sampled bus value EDCD_MASK is initialized to all ones at reset 4 10 Event Selector ES Registers ES selects the source for various operations used by the EOnCE It contains the followin...

Page 172: ...er 1 Trace is disabled upon detection of the event by all the sources ANDed selected on the ESEL_DTB register SELETB Bit 3 Selection Bit for Trace Enable Determines how the enabled sources enable trace 0 Trace is enabled upon detection of the event by any one of the sources ORed selected on the ESEL_ETB register 1 Trace is enabled upon detection of the event by all the sources ANDed selected on th...

Page 173: ...espect to core activity AND ed with other EOnCE events if used as an enabling event that is asserted continuously for extended periods In this case the assertion and de assertion transitions of EDCA6 7 events should be controlled by the system in SW or HW since the transition edge cases could be problematic to detect AND ed with an EDCD event intended to detect an address data pair on the same bus...

Page 174: ...ster has one bit for every source of the ES Setting the appropriate bit configures the related source to enable trace Figure 4 26 displays the bit configuration of ESEL_ETB Figure 4 26 Event Selector Mask Enable Trace ESEL_ETB If multiple sources are configured to enable trace they are ANDed or ORed according to the value of the SELETB bit in the ESEL_CTRL If all the bits are set to zero the ES do...

Page 175: ...gister TB_BUFF 4 11 1 Trace Buffer Control Register TB_CTRL The TB_CTRL register controls the operation of the trace unit The following tracing modes are possible all which trace the PC of execution sets that answer some conditions TEXEXT trace the PC of every execution set TMARK trace the PC of execution sets that includes the MARK instruction TCHOF trace the source and destination PC of executio...

Page 176: ...equires one core clock cycle Requesting multiple trace buffer actions such as setting TLOOP TCOUNT and TCNEXT in TB_CTRL will require a core clock cycle for each write in this case four clocks If a long loop with only three execution sets is encountered with the above TB_CTRL configuration there are not enough cycles to write all the data The value of the extension counter register will be lost In...

Page 177: ... is disabled Tracing could be enabled again after no less than 5 VLES from when it has been disabled Figure 4 28 displays the bit configuration of TB_CTRL Shaded areas are reserved Figure 4 28 Trace Buffer Control Register TB_CTRL The TB_CTRL fields are described in the following table BITS 15 8 7 6 5 4 3 2 1 BIT 0 TCNTEXT TCOUNT TLOOP TEN TMARK TEXEC TINT TCHOF TYPE rw rw rw rw rw rw rw rw rw RES...

Page 178: ...f every issued execution set 0 Execution set tracing is disabled 1 Execution set tracing is enabled All other mode bits should be cleared Tracing includes the PC of every issued execution set TINT Bit 1 Trace Interrupts Enable Mode Used to enable tracing the addresses of interrupt vectors When the bit is set each service of an interrupt puts the address of the last executed or aborted execution se...

Page 179: ... is enabled 4 11 3 Trace Buffer Write Pointer Register TB_WR TB_WR is a 16 bit register that points to the next location available for writing into the buffer The register is reset when the trace buffer is enabled 4 11 4 Trace Buffer Register TB_BUFF This 32 bit register is used to read the contents of the trace buffer For details see Section 4 5 5 3 Reading the Trace Buffer TB_BUFF It is a pipeli...

Page 180: ...4 70 SC140 DSP Core Reference Manual Trace Unit Registers ...

Page 181: ...according to the SC140 programming rules When the assembler compiles the DSP code it specifies in the encoding whether an instruction stands alone or whether it is grouped with other instructions In each clock cycle the dispatch logic detects how many instructions are grouped Each group of instructions issued to the execution units on a given clock cycle is called an execution set Each line of eig...

Page 182: ...ntains four ALUs and two AAUs and thus execution set can contain up to four DALU instructions and two AGU instructions with a maximum of eight words For many instructions an execution set takes only one clock cycle For a detailed description of SC140 core instruction timing see Section 5 3 Instruction Timing on page 5 14 5 1 1 Instruction Pipeline Stages Figure 5 1 illustrates the five instruction...

Page 183: ... i6 Execution i1 i2 i3 i4 i5 i6 Table 5 2 Pipeline Stages Overview Pipeline Stage Description Pre fetch Generate addresses for program fetch Update fetch counter FC Fetch Read fetch set from memory Dispatch Dispatch instructions Decode AGU instructions Address Generation Decode DALU instructions Generate addresses for data load and store operations Perform address calculations normal and change of...

Page 184: ...set can be consumed anywhere between 1 cycle in case the VLES is 8 words long and 8 cycles in case it contains 8 VLES of 1 word each The fetch unit tries to keep this buffer full as much as it can After reset and after every change of flow COF a series of 4 fetch requests is issued to the memory Upon dispatch of the last instruction in the fetch set another fetch request is issued to the memory In...

Page 185: ... 5 1 Four SC140 Instructions in an Execution Set In the execution set above the four SC140 instructions are grouped When executed the following occurs 1 The contents of the D0 and D1 registers are multiplied fractionally The result is subtracted from the D7 data register The final result is then rounded and stored in the D7 data register 2 The contents of the D4 and D5 registers are ANDed together...

Page 186: ...back in the R0 register 7 The 32 least significant bits of the D0 register are moved to the R1 register 5 2 1 Grouping Types The SC140 grouping includes two types of encoding Serial non prefix grouping which encodes in the two most significant bits MSB of instructions Prefix grouping which encodes a one word or two word prefix at the start of the execution set The Program Dispatch Unit PDU in the ...

Page 187: ...ons which may be one or two words long The serial grouping options for an execution set are One to six Type 1 instructions One Type 2 instruction grouped with up to five Type 1 instructions on condition that a Type 2 instruction can be the last in VLES Refer to Section 7 4 1 3 Assembler Reordering on page 7 3 One Type 3 instruction grouped with up to five Type 1 instructions on condition that a Ty...

Page 188: ...e loop information Specify conditional execution of the VLES or sub groups of the VLES Encode high register banks D8 D15 R8 R15 The SC140 16 bit instruction encoding has a three bit field for specifying each data register or address pointer register On their own these instructions can encode eight DALU registers D0 D7 and eight address pointers R0 R7 In order to specify operands that belong to the...

Page 189: ...nd MOVE instructions is executed only if the T bit is set The instructions in the subgroups may themselves be conditional For example using MOVEc TFRc and Jc can add further conditional control However the subgroups themselves may not contain another IFc instruction If no IFc instructions exist in the execution set the default is the unconditional execution of the whole set For finer control it is...

Page 190: ...refix is generated A two word prefix is generated only when high register banks are used in the execution set The assembler encodes the execution set according to these principles as shown in Figure 5 3 IFT inst inst IFF inst inst Execution of subgroup1 if T 1 Execution of subgroup2 if T 0 IFT inst inst Execution of the whole group if T 1 IFF inst inst Execution of the whole group if T 0 IFT inst ...

Page 191: ...Yes Use a one word low register prefix No Continue Does the execution set contain only one instruction Yes No prefix is needed No Continue Does the set contain all Type 1 instructions except for a single Type 2 or Type 3 instruction Yes No Continue Are registers D8 D15 or R8 R15 used in the execution set Use a one word low register prefix No prefix is needed Can a Type 2 or a Type 3 instruction be...

Page 192: ...ering may be necessary concerning instruction positions within an execution set In general execution set reordering is transparent to application developers The assembler appropriately reorders the instruction encoding in an execution set However the assembler s behavior may become apparent upon disassembly of the binary code when the order of instructions in the set may be different from the sour...

Page 193: ...Instructions encode in the even word positions Subgroup2 Instructions encode in the odd word positions This means that in any subgroup one cannot have more then one two word instruction since according to the previous bullet one two word instruction should be in even place and the other in odd In this example instructions of the IFT subgroup encode in subgroup1 even word positions while instructio...

Page 194: ...write BMU instructions take two or three cycles Change of flow COF instructions take three or more cycles to execute They include direct PC relative conditional delayed jumps and branches and loop control instructions Parallel execution takes place when two or more instructions grouped into an execution set execute simultaneously Instructions belonging to an execution set always start execution co...

Page 195: ...OVE L d0 Rn 5 MOVE L d0 Rn Rm MOVE L d0 SP 100 All bit mask BMU instructions execute in two cycles on registers and memory zero wait states without contention with simple addressing modes However if a pre calculation is required such as an SP offset a third cycle is added Basic Instruction Category Example Condition Number of Clock Cycles DALU MAC D0 D1 D2 1 Data move with simple addressing MOVE W...

Page 196: ... two word long word four word and two long word operands signed or unsigned Data can be moved between memory and register or between registers 5 3 1 3 Bit Mask Instruction Timing The SC140 core includes various instructions for bit mask operations These instructions are helpful when several bits need to be changed or tested at the same time The bit mask instructions include the following Bit mask ...

Page 197: ...access time to memory as well as the number of stages in the pipeline In order to use time more efficiently most of the COF instructions have a delayed version that enables the execution of one execution set while the pipeline is filling up The delayed instruction effectively saves one or more cycles over the non delayed version The suffix D indicates the delayed version of an instruction as in JM...

Page 198: ...mined as not taken meaning the condition is false there are no additional cycles JMPD Jump delayed JSR Jump to subroutine JSRD Jump to subroutine delayed JT Jump if true JTD Jump if true delayed RTE Return from exception RTED Return from exception delayed RTS Return from subroutine RTSD Return from subroutine delayed RTSTK Restore PC from the stack updating SP RTSTKD Restore PC from the stack upda...

Page 199: ...rsion was used The delay slot lasts for the full execution time of the set in the delay slot which may be more than one cycle The minimum execution time of a delayed instruction is one cycle For example JMPD dest takes 1 cycle 3 2 1 because the next instruction MOVE W d0 sp xxx takes 2 cycles Stalls that originate in delay slot instructions and are caused by a memory access wait state or contentio...

Page 200: ... 5 7 Subroutine Call Timing JSRD _subr MOVE W R0 2 D0 Cj 3 Cjn 2 ADDA R0 R1 Cd 1 Table 5 8 summarizes the cycle count for change of flow instructions In the Number of Cycles column Cd represents the length of the delay slot in cycles The technique of subtracting the cycles of the delay slot instructions from the cycle count of the delayed change of flow instruction assumes that the delay slot inst...

Page 201: ...escribe the timing for memory accesses generated by instructions in the same execution set In some examples no problems arise since the memory accesses fall into different cycles In other examples memory contention can occur RTE 5 6 Shadow SP is valid Shadow SP is not valid RTED 5 Cd 6 Cd Shadow SP is valid Shadow SP is not valid RTS 3 5 6 RAS is valid RAS is not valid and shadow SP is valid RAS i...

Page 202: ...nds on the validity of the stack pointer SP shadow register that holds a pre decremented value of the SP in order to avoid the need for pre calculation If shadow SP is not valid for example after an explicit SP update another cycle is needed for the first pop in order to perform the pre calculation The following rules apply to cases of contention due to dual access to the same physical memory modu...

Page 203: ...he memory accesses are made to addresses that cause contention In Case A the read and write operations scheduled for Cycle 1 will cause contention In Case B the two write operations in Cycle 2 will cause contention Example 5 9 Execution Set Containing a Bit Mask and a Move Instruction A BMSET W 0008 R1 MOVE W D0 8200 Cycle 1 read from R1 write to 8200 Cycle 2 write to R1 B BMSET W 0010 R1 MOVE W D...

Page 204: ...in the execution set have been performed Delayed instructions with implicit push memory access such as JSRD access memory after all other accesses in the delay slot have been performed Delayed instructions with implicit pop memory access such as RTSD and so on access memory before accesses in the delay slot are performed Consequently these instructions do not cause contention when they are execute...

Page 205: ...onality of each register pair is described in the sections that follow Figure 5 4 shows the hardware loop programming model This programming model holds the full loop state and can be saved and restored for exception service routines context switches or spill fill operations to support additional nesting levels Figure 5 4 Hardware Loop Programming Model 5 4 1 1 Loop Start Address Registers SAn The...

Page 206: ... terminates The short loop can only be used in the inner most nesting level 5 4 2 Loop Notation and Encoding The notation used in the loop definitions is as follows Loop Body The execution sets that are iterated during loop execution Long Loop A loop body that consists of three or more execution sets Short Loop A loop body that consists of one or two execution sets Start address SA The address of ...

Page 207: ...ruction provides the additional flexibility of skipping the steps in the loop completely if the loop count is zero initially After the LCn is loaded and the LFn bit is set with the DOENn or DOENSHn instruction the hardware loop is ready for operation In long loops whenever the program reaches the execution set marked by LPMARKB which appears two execution sets before the last execution set of the ...

Page 208: ...the active loop In the first iteration of Loop 2 Loop 3 is enabled and now becomes the active loop Loop 3 is active until it has finished repeating at which time Loop 2 becomes active When Loop 2 stops repeating including further complete cycles of Loop 3 Loop 0 becomes the active loop When Loop 0 stops repeating no loops are active 5 4 5 Loop Iteration and Termination The CONT instruction causes ...

Page 209: ...mmediately before SA LOOPENDn Placed immediately after LA By definition a loop body n is enveloped by the LOOPSTARTn and LOOPENDn directives In disassembled code the LOOPSTART and LOOPEND directives are not available The start address information is encoded as an offset in the DOSETUPn instruction for long loops or in the LPMARK prefix bits for short loops The last address information is encoded i...

Page 210: ...es SA0 with address corresponding to _start0 doen0 10 Activates loop0 puts 16 into LC0 sets LF0 move w r3 d1 Puts data into d1 skipls _end0 Skips loop if LC0 0 loopstart0 Assembler directive denoting loopstart _start0 mac d0 d1 d2 move w r0 d0 add d5 d6 d4 move w r1 d5 sub d3 d2 d4 inc d5 mac d0 d1 d6 move w r0 d7 sub d5 d4 d4 inc d7 loopend0 _end0 Loop body SA LA LPMARKB p 00380000 2803 800c dose...

Page 211: ...e loopstart or loopend information if necessary In disassembly these LPMARK bits if used appear preceding the normal disassembled mnemonics of the set doensh0 10 loopstart0 mac d0 d1 d2 move w r0 d0 loopend0 Loop body LPMARKA SA LA dosetup0 _start0 dosetup1 _start1 doen0 10 loopstart0 _start0 bmset ff01 d0 doen1 d7 clr d2 skipls _end1 loopstart1 _start1 mac d0 d1 d2 move w r0 d0 add d5 d6 d4 move ...

Page 212: ...me The SC140 core has many features that help software designers implement a software stack and more efficiently support a multitasking real time operating system RTOS These features include Two stack pointers one for the normal stack NSP and one for the exception stack ESP only one of which is active at a time referenced as SP Separate user normal and exception working modes Push and pop instruct...

Page 213: ...d in the exception working mode by the RTOS and interrupts Since the RTOS and interrupts have their own stack pointer memory for the RTOS and interrupts can be allocated separately Thus the RTOS and interrupt code can be modified independently of the tasks Figure 5 7 shows the stack structure Figure 5 7 SC140 Memory Use with Dual Stack Pointers The core uses the exception working mode whenever it ...

Page 214: ...n odd register operand A push instruction always pushes one 32 bit register into the stack Any execution set that includes one or two push instructions increments the stack pointer by eight In the case of a single push a single operand is written to the memory while the adjacent memory location remains unchanged Table 5 11 Stack Push Pop Instructions Instruction Description POP Pre decrement the s...

Page 215: ...pop operands should match the corresponding push operands In addition to the push and pop instructions the stack can be accessed directly with move or bit mask instructions The available addressing modes are shown in Table 5 14 The two addressing modes differ in the instruction word count Note that the user cannot use addressing modes that update SP during the access but only short or word displac...

Page 216: ...utine and the execution of the RTS then RTS executes in three cycles Upon RTS the RAS is invalidated until the next JSR or BSR instruction The user is not allowed to create a situation where upon using RTS the RAS is valid but the return address does not match the one that is stored in the stack This situation may occur if the user explicitly changed the return address in the stack See Rule J 4 in...

Page 217: ...ask data structures The core stays in this mode unless An exception is encountered as described in A hardware reset occurs as described in Section 5 7 4 Reset Processing State An RTE like instruction RTE D is issued 5 6 2 Exception Working Mode This mode uses the Exception Stack Pointer ESP It is intended for the RTOS kernel interrupt service routines peripheral device drivers etc Also application...

Page 218: ...k 5 6 3 1 Dual stack RTOS Figure 5 8 illustrates the working mode transitions for dual stack operating systems Figure 5 8 Working mode Transitions Unprotected Dual stack RTOS The dual stack operating system kernel executes in the Exception working mode User task context is initialized while in the Exception working mode User task invocation occurs when an RTE D instruction is executed that restore...

Page 219: ...tion is to be taken to a new task that is not on the stack the stack must be pre loaded with suitable values before performing the RTE The following explicit actions must be taken The address of the first VLES for the task must be stored in the memory location representing the PC on the active ESP stack The memory location representing SR on the active ESP stack must be set with EXP 0 An RTE D ins...

Page 220: ...mps to the Vector Base Address VBA Exception Offset Address For example executing a TRAP instruction causes the core to enter an Exception state and begin executing instructions at VBA 0x00 since the TRAP instruction has an exception offset address of 0x00 If choosing to prepare the return values on the stack explicitly to perform this transition the programmer should be aware that in Normal mode ...

Page 221: ...ere may be different for certain products that utilize a SC140 core Consult the product specific manuals for details of actions in each processing state 5 7 1 Processing State Change Instructions Processing state changes can be initiated by hardware or software means Table 5 16 lists the instructions that can initiate a processing state change Table 5 16 Processing State Change Instructions Instru...

Page 222: ...ssing State Transitions The transitions between the states are summarized in the following figure Figure 5 10 Core State Diagram Table 5 17 describes the processing state transitions shown in Figure 5 10 EXECUTION RESET STOP WAIT DEBUG 1 2 3 4 5 6 7 8 9 10 11 12 13 14 ...

Page 223: ...he exception working mode as part of the execution state and program execution begins at a derivative dependent program memory address Processing State Transitions Description 1 2 3 4 Assertion of one of the core hardware reset input signals 5 De assertion of reset if EE0 or a JTAG debug command is asserted during reset 6 7 Entering debug state through an external request JTAG EE pin or system inp...

Page 224: ...nsumption state entered by the execution of the WAIT instruction After a system specific delay of some cycles from the issue of the WAIT instruction the core s global clock is turned off Peripherals can continue to operate but all internal processing is halted until one of the following actions occurs An interrupt with enabled priority is issued1 A non maskable interrupt NMI request is issued A lo...

Page 225: ...l for further details If the Stop Processing State is exited by assertion of the RESET signal the core enters the reset processing state If the stop processing state is exited during the assertion of an external interrupt request the core enters the exception mode and services the highest priority pending interrupt If no interrupt is pending the core enters the execution state and executes the ins...

Page 226: ... of the address to which the program jumps to perform a particular routine in response to the exception Non Maskable External Interrupts These have the next highest priority level four A non maskable external interrupt is driven from the external interrupt controller Its offset address vector is either the AUTO VEC 0x180 or the value on the 6 bit Interrupt Offset bus Maskable External Interrupts T...

Page 227: ...t offset or the value driven by the user on the 8 bit INTERRUPT OFFSET bus This selection affects both maskable and non maskable interrupts INTERRUPT OFFSET This 6 bit value can be the offset address applied to the interrupt vector address table It is selected if the AUTO_VEC above does not select the default offset The complete address of the interrupt vector is defined by a number of fields For ...

Page 228: ... register with the lower 12 bits always zero The upper twenty bits 31 12 are automatically used to form the base address bits 31 12 of the exception vector address The upper twenty bits of VBA are initialized at reset with a derivative dependent address pointing to the initial Vector Address Table After reset VBA may be programmed to relocate the Vector Address Table anywhere in memory Care must b...

Page 229: ...pendix A SC140 DSP Core Instruction Set for details on return from exception usage in the RTE and RTED instructions The RTE D instructions do not affect the shadow return address of subroutines see Section 5 5 5 Fast Return from Subroutines In this way the interrupts interfere less with the interrupted task allowing it to continue and enjoy the reduced cycle count when performing an RTS if applica...

Page 230: ...that are not masked by the IPL bits The DI and EI instructions do not affect the IPL bits 5 8 4 Non Maskable Interrupts NMI An NMI request is serviced regardless of the current IPL and DI bit values The only time an NMI request remains pending is when another NMI is already being serviced When an NMI service routine enters execution namely the NMI vector is fetched the NMI disable NMID bit in the ...

Page 231: ...not block subsequent illegal instruction exceptions Multiple illegal instructions will cause multiple illegal exceptions regardless of the ILIN state However illegal instructions that occur close together may share the same illegal exception In particular additional illegal events that occur between the first event and its illegal exception service routine will share the same exception If an illeg...

Page 232: ... is entered This exception is precise It occurs immediately after the execution set that contains the TRAP instruction The TRAP instructionis typically used for RTOS calls 5 8 5 4 Debug Exception A debug exception can be initiated as a result of a debug event as configured in the EOnCE It is also possible to configure the DEBUG and DEBUGEV instructions to generate a debug exception This exception ...

Page 233: ...ase that does not include delayed instructions or core stalls but does include exceptions occurring near change of flow instructions In this example the JUMP instruction represents all change of flow instructions in Table 5 8 excluding delayed instructions and TRAP It also represents the DI disable interrupt instruction Example 5 17 Basic Exception Timing Let ES0 ES4 be a sequence of execution set...

Page 234: ...ion vector is executed after ES1 and the address of ES2 is pushed as a return address to the stack 2 cycles are added Else if ES1 is JUMP Then The execution set from the target of the exception vector is executed after ES0 and the address of ES1 is pushed as a return address to the stack 3 cycles are added End ...

Page 235: ... 5 17 Figure 5 12 Flowchart for Exception Timing Yes Execute ES0 Store ES1 address Add three cycles Execute exception vector No Is ES2 a JUMP No Execute ES2 Store ES3 address Add one cycle Execute exception vector Yes Yes Execute ES1 Store ES2 address Add two cycles Execute exception vector Is ES1 a JUMP ...

Page 236: ... and ES2 are not change of flow instructions And I1 is the first instruction at the exception vector address The exception request is initiated in cycle 4 Table 5 21 Pipeline Example Operation Instruction Cycle 1 2 3 4 5 6 7 8 9 10 11 12 Pre fetch ES0 ES1 ES2 I1 Fetch ES0 ES1 ES2 I1 Decode ES0 ES1 ES2 push I1 Address Generation ES0 ES1 ES2 push I1 Execute ES0 ES1 ES2 push I1 ...

Page 237: ...ng capabilities etc ISAP support is integral to the SC140 development tools so the SC140 assembler simulator and compiler can all be modularly configured to support the specific ISAP s definition This enables the programmer to effectively use ISAP instructions in the source code like any other SC140 instruction with minor modifications However the specific ISAP instruction set and programming rule...

Page 238: ...the data memory via the same two data buses XDBA and XDBB as the core in both read and write directions The SC140 core is the only address generating master of the data buses The ISAP does not send address information to the Data memory hence the ISAP does not need an AGU A data access to or from the ISAP requires a parallel core AGU MOVE instruction that generates the access on the address and co...

Page 239: ...ispatched ISAP instruction an ISAP controller decodes the ISAP select bits and enables the respective ISAP The other ISAPs are therefore disabled for this cycle The system designer must put these bits in the MSB of the opcode of the ISAP instruction Further operation is similar to a single ISAP The connections of the ISAPs with the data memory are not shown in Figure 6 2 Proper muxing should be im...

Page 240: ...LU without activation of simultaneous core AGU instructions Data move instructions Instructions that transfer data between the ISAP and its environment external Data memory or SC140 core The core has the capability of providing the ISAP with data addressing so that the ISAP designer need not incorporate an AGU in the ISAP This requires certain conventions which are detailed in Section 6 4 ISAP Mem...

Page 241: ...SAP instruction simply will not drive or sample the D register In effect the d0 in this instruction becomes a dummy source which the core therefore ignores and in our case only the address found in r1 is driven to on the data address bus In a complementary manner the ISAP move_special instruction only drives the data in k0 on the appropriate data bus and not handle the addressing of the access In ...

Page 242: ...sembler translate the ISAP instructions into two instructions one core instruction that writes an immediate value to a dummy core register and an ISAP instruction that samples the data to an ISAP register The assembler can use any move immediate core instruction to a DALU register for example MOVE L s32 D0 See Appendix MOVE L on page A 272 When executed in parallel with an ISAP instruction the cor...

Page 243: ...hould be informed which ISAP is to be used so that it can verify that it is using the correct assembler extension The core assembler supports two methods to do this Setting a default ISAP name and prefixing the ISAP brackets with the ISAP name 6 7 1 1 Working with One ISAP When working with a single ISAP we recommend defining a default ISAP name An assembly directive is used to do this The followi...

Page 244: ...nstruction storing ISAP register k2 to a memory location pointed by core register r1 The assembler generates an implicit AGU instruction move l d0 r1 As explained in Section 6 4 ISAP Memory Access the d0 register is a dummy register which is not driven on the memory data bus rather the ISAP stores its k2 register by driving the k2 register data on the data bus and the address is set by the core as...

Page 245: ..._instruction k0 k1 k2 mac d0 d1 d3 FP isap_instruction k0 k1 k2 In this example in the first execution set the core performs a parallel MAC instruction and the Floating Point ISAP executes its own instruction In the second execution set the core performs a MAC instruction and the Image Processing ISAP executes its own instruction 6 7 2 An Example of the Definition Flexibility of an ISAP When assem...

Page 246: ...redicating only an ISAP clause as in the case of the iff in the above example There can be two ISAP clauses per VLES each belonging to a different IFc group ISAP ALU instructions must all be in the same IFc group Implicit Core AGU instructions generated to support ISAP move instructions are subject to the same limitations as other core AGU instructions This means for example If the VLES includes t...

Page 247: ...scribed in the following sections Read data from the data memory to ISAP register s An implicit SC140 AGU MOVE instruction is needed for this function Write data from to ISAP register s to the data memory An implicit SC140 AGU MOVE instruction is needed for this function Exchange data between core registers and ISAP register s An implicit SC140 AGU MOVE instruction is needed for this function Acce...

Page 248: ...tten inside the ISAP brackets the core assembler creates an implicit MOVE instruction that will send the required address to the data memory The ramification of this is that when there is a MOVE like instruction inside the ISAP brackets all the rules that apply for original core MOVE like instructions apply for the implicit MOVE like instructions as well An example from Rule A 2 for an ISAP instru...

Page 249: ...itional core instructions is larger for non DALU instructions T 2a One VLES required between an ISAP instruction that updates the T bit and a conditional COF instruction T 2b 2 VLES required between an ISAP instruction that updates the T bit and a MOVET F instruction T 2c 2 VLES required between an ISAP instruction that updates the T bit and an AGU instruction conditioned by IFT F In addition ISAP...

Page 250: ...6 70 SC140 DSP Core Reference Manual Programming Rules ...

Page 251: ...ons finish execution after the delay slot This means The results of one VLES are immediately available to the next sequential VLES The latency of various SC140 instructions is not exposed in the assembly source code The number of cycles for a VLES is the number of cycles taken by its longest instruction Even though the SC140 pipeline overlaps the execution of several VLES the assembly source order...

Page 252: ... its condition is false the instruction does not execute becomes a NOP The IFc instruction conditionally executes all instructions that follow it in assembly source order until the next IFc instruction or the end of the VLES Multiple IFc instructions in a VLES form subgroups of instructions that are conditionally executed based on their associated IFc condition Multiple IFc subgroups having the sa...

Page 253: ...ecify that instruction A cannot be in a VLES at a specific location They use the notation that A cannot be in a delay slot in a short loop at LA of the same long loop n or in the first VLES of an exception service routine and so on 7 4 1 1 Prefix Instructions Prefix instructions are a unique instruction type because they are encoded in a VLES prefix and are not dispatched to execution units Any un...

Page 254: ...is true If A and B have mutually exclusive execution conditions their execution cannot violate a sequencing rule The simulator knows if A and B execute from its simulation trace and detects programming rules considering their conditional execution However the assembler cannot know the T bit state when A or B execute So the assembler detects sequencing rules independent of conditional execution Tha...

Page 255: ...luding All explicit MOVE instructions listed in Table A 10 AGU Move Instructions on page A 16 VSL instructions listed in Table A 10 AGU Move Instructions on page A 16 Pop push instructions listed in Table A 11 AGU Stack Support Instructions on page A 16 Bit mask instructions listed in Table A 12 AGU Bit Mask Instructions BMU on page A 17 COF instructions that have implicit push pop operations are ...

Page 256: ...hardware interrupts as described in Section 5 8 Exception Processing 7 4 8 1 COF Instructions A COF instruction specifies a usually non sequential destination address that may implicitly write the program counter PC register The COF result may be conditional on the T bit All references to COF instructions in this manual include both the non loop COF instructions listed in Table A 13 AGU Non Loop C...

Page 257: ...rrounds or contains loop B This definition is relative to each loop pair If another loop C is nested inside loop B loop C becomes the nested loop and loop B becomes the enveloping loop for this loop pair Loops A and B are required to have ordered but not adjacent loop indexes The assembler s static rule detection assumes the boundaries of loop n are from the VLES after the VLES having the DOENn DO...

Page 258: ...7 DALU Arithmetic Instructions MAC on page A 13 and Table A 8 DALU Logical Instructions BFU on page A 14 Two AGU instructions including All AGU arithmetic instructions listed in Table A 9 AGU Arithmetic Instructions on page A 15 All AGU move instructions listed in Table A 10 AGU Move Instructions on page A 16 All AGU stack support instructions listed in Table A 11 AGU Stack Support Instructions on...

Page 259: ...jmp r1 ifa jf r2 not allowed ift bra _label1 iff brad _label2 not allowed ift jmpd r1 iff jmp r2 not allowed Multiple writes of the same address pointer register Rn cannot be grouped in a VLES The no update addressing mode Rn is not considered an address register write Example 7 6 Duplicate Address Pointer Register Destinations move w r0 d0 move w d1 r0 not allowed move w r0 r0 not allowed move l ...

Page 260: ... in SR cannot be grouped in a VLES Example 7 10 Duplicate Status Bit Destinations cmpeq d0 d1 tstgea l r0 not allowed multiple T bit updates cmpeq d0 d1 bmtstc 3 d0 l not allowed multiple T bit updates Note that BMSET 3 SR H reads and writes the 32 bit SR register while BMTSTC 3 D0 L affects only the T status bit in SR Rule G G 4 also applies to core vs ISAP instructions in addition to ISAP vs ISA...

Page 261: ...ed DI and S updates doen0 5 max2vit d4 d2 allowed LF and VF updates Multiple instructions that affect the C or S status bits in SR or the DOVF status bit in EMR can be grouped in a VLES S and DOVF are sticky status bits are set by the logical OR of all executed instructions in a VLES that affect them C is updated by only one instruction in a VLES the last in the assembly source order carry affecti...

Page 262: ...ther two word instruction and or one word instructions Example 7 17 Two Word Instructions Exceed Two move f 1234 d0 1st extension word extract 8 16 d0 d2 2nd extension word extractu 8 24 d0 d3 not allowed 3rd extension word zxt b d0 d0 The second and third words of an instruction are called extension words An extension word can occur in the following cases Some immediate values Some absolute addre...

Page 263: ... Exclusive Instructions stop wait not allowed mark mark not allowed stop mark allowed ift doen1 5 iff doen2 4 allowed ift debug iff debugev allowed ift stop iff wait not allowed ift wait iff bra _label not allowed Rule G P 4 An RTE D instruction cannot be Grouped in a VLES with another AGU instruction In a VLES having two IFc subgroups Example 7 19 RTE Uses Both AAU rted inca r3 not allowed ift cl...

Page 264: ...e assembler adds implicit AGU instructions to support ISAP memory accesses and register transfers this rule does apply to these implicit AGU instructions For more details on how this works see Section 6 4 ISAP Memory Access on page 6 60 Note that the overall number of DALU instructions in the entire VLES is restricted by Section Rule G G 3 Example 7 21 IFc Having Two Subgroups ift add d0 d2 d3 iff...

Page 265: ...re AGU instructions on same VLES as ISAP instructions move l r0 d0 INC K0 not allowed INC K0 is an ISAP instruction add d0 d1 d2 INC K0 allowed add is not an AGU instruction MOVE L D0 K0 allowed The core assembler generates an implicit AGU move from d0 Rule G P 9 All ISAP ALU instructions in a VLES must belong to the same IFc group ISAP instructions that generate implicit AGU instructions are subj...

Page 266: ...use MCTL not allowed move l 12345678 mctl change MCTL nop nop move w r0 d0 use MCTL allowed move l d0 mctl change MCTL adda r0 r1 use MCTL not allowed move l d0 mctl change MCTL move w d1 r0 n0 use MCTL not allowed bmclr 0 mctl l change MCTL move w r0 d0 use MCTL not allowed bmclr 0 mctl l change MCTL move w r1 d0 use MCTL not allowed bmclr 0 mctl l change MCTL move w r5 d0 use MCTL not allowed mo...

Page 267: ...te to AGU Use move l d0 r0 jmp r0 not allowed move l d0 r0 move w r0 d1 not allowed move l d0 b0 move w r8 d1 not allowed b0 is alias of r8 move l d0 b0 move w r0 d1 allowed but may contradict Rule A 2a due to r0 post inc move l d0 r0 bmclr w 4 r0 not allowed move l d0 b0 move w r0 d1 allowed no Rn write move l d0 b0 adda r9 d0 not allowed move l d0 b3 adda r11 d2 not allowed b3 is alias of r11 mo...

Page 268: ...owed tfra osp r0 move l r0 d0 not allowed move w r0 r0 not allowed move w d0 r8 move l r8 d1 not allowed move w d0 r8 move l b0 d1 not allowed b0 alias vsl 2w d1 d3 r0 n0 move l r0 d0 not allowed move w r2 r0 move w r0 r1 allowed move w r0 r0 allowed no Rn write adda 28 r6 r0 move l r0 r2 allowed adda 28 r6 r0 move l r2 r0 allowed adda 5 n0 move l d0 r0 n0 allowed adda 5 n0 move l r0 n0 d0 allowed...

Page 269: ...R register For mutually exclusive IFc subgroups in a VLES this rule applies independently to each subgroup Example 7 29 NMID Update to EMR Read rtstk move l emr d0 not allowed 7 5 5 Delayed COF Rules Rule D 1 The following instructions are not allowed in a delay slot COF instructions STOP and WAIT DI DEBUG Example 7 30 Instructions in a Delay Slot jmpd r1 jmp r2 not allowed ...

Page 270: ...not allowed rted rol d0 not allowed affected by SR C rted push d0 not allowed affected by SR EXP rted bmclr w 64 sp 8 not allowed affected by SR EXP rted bmtsts w 64 r0 not allowed affects SR T rted tfra r0 osp not allowed affected by SR EXP rted tfra sp r0 not allowed affected by SR EXP rted ift clr d0 not allowed affected by SR T rted tfra r0 r1 allowed rted tsteq k0 changes T bit based on ISAP ...

Page 271: ...xclusive IFc subgroups in a VLES this rule applies independently to each subgroup Example 7 34 SR Write with a Subroutine Call pop sr jsr r0 not allowed Rule D 5a A MOVE like instruction that writes the SR register is not allowed in the delay slot of a BSRD or JSRD instruction Example 7 35 SR Write in BSRD or JSRD Delay Slot bsrd _label pop sr not allowed Rule D 6 Instructions that read or write t...

Page 272: ...struction Example 7 38 EMR Use in Return Delay Slots rtstkd move l emr d0 not allowed rted bmclr fffb emr l not allowed 7 5 6 Status Bit Rules Rule T 1 At least one VLES is required between an instruction that affects the T status bit in SR and an AGU instruction in an IFT IFF group or subgroup This rule does not apply to AGU instructions in an IFA subgroup Example 7 39 T Bit Update to IFT IFF AGU...

Page 273: ... Bit Update by ISAP and MOVET MOVEF tsteq k0 tsteq is an ISAP instruction that updates the T bit movet r0 r1 not allowed tsteq k0 nop nop movet r1 r2 allowed Rule T 2 c At least two VLES are required between an ISAP instruction that affects the T status bit in SR and an AGU instruction in an IFT IFF group or subgroup This rule does not apply to AGU instructions in an IFA subgroup Example 7 42 T Bi...

Page 274: ...tatus bit A MOVE like instruction that writes the SR register may be followed by a MOVE like instruction that reads the SR register if not affected by a SR status bit The assembler mapped instruction CLR Dn is never affected by SR status bits even though it is implemented as SUB Da Da Dn Therefore this rule applies to the SUB instruction but not to CLR SUB Da Da Dn is taken as CLR in this context ...

Page 275: ...by SR EXP bmclr 1 sr h change SR nop ift clr d0 not allowed affected by SR T bmtstc 0001 sr l read SR affects SR T not a SR write add d1 d5 d1 allowed pop sr bmset a sr l allowed move l d0 sr move l sr d5 allowed bmset a sr h and w 1234 sp 8 not allowed bmset a sr l and w 1234 sp 8 not allowed bmset a sr l bmset b sr h allowed move l d1 sr move l d0 sp 4 not allowed move l d1 sr move l d0 r0 4 all...

Page 276: ...us Bit Update move l 1 sr di not allowed bmclr ffff sr h doen0 10 not allowed pop sr cont _next not allowed Rule SR 4 At least two VLES are required between an instruction that affects the DOVF status bit in EMR and a MOVE like instruction that reads or writes the EMR register The assembler mapped instruction CLR Dn never affects the DOVF status bit even though it is implemented as SUB Da Da Dn Th...

Page 277: ...lowed sub d1 d1 d0 This is a CLR The DOVF bit is not affected move l emr d3 allowed Rule SR 4a Instructions that affect the DOVF status bit in EMR can t be grouped with a MOVE like instruction to SR or with an RTE like instruction RTE D The only exception for this rule is for Bit Mask instructions on SR for which it is ensured that the value of the OVE bit in SR is not changed Example 7 46 DOVF Up...

Page 278: ...DI and EI DOENn and DOENSHn SKIPLS For mutually exclusive IFc subgroups in a VLES this rule applies independently to each subgroup Example 7 47 Status Bit Update with SR Read doen0 5 move l sr d0 not allowed di push sr not allowed skipls _dest bmtsts 4 sr h not allowed 7 5 7 Loop Nesting Rules Rule L N 1 Nested loops cannot have the same LA Example 7 48 Nested Loops with the Same LA move w r3 r4 L...

Page 279: ...impyuu d1 d2 d3 move w d3 r1 loopend0 nop loopend1 Rule L N 3 A DOENn DOENSHn instruction having a different loop index and any LOOPEND directive cannot come between the DOENn DOENSHn instruction and LOOPSTARTn directive of loop n Also it is not allowed to place a DOENSH instruction with any index between the DOENn and its respective LOOPSTARTn directive or a DOEN instruction with any index betwee...

Page 280: ...tion should be in the loop but isn t loopend0 Example 7 52 LOOPEND between DOEN and LOOPEND doen2 3 dosetup2 L_1 nop L_1 loopstart2 nop nop doen3 3 not allowed problem created here dosetup3 L_2 nop nop nop loopend2 problem becomes apparent here nop L_2 loopstart3 nop nop nop loopend3 Example 7 53 Changing a loop type doensh0 3 doen0 3 not allowed to change loop type dosetup0 _loop_start nop nop _l...

Page 281: ...Instructions at the End of Long Loops move w count2 d6 dosetup0 label2 doen0 d6 move w 1 d1 move w 2 d2 move w 3 d3 move w 4 d4 loopstart0 label2 inc d1 inc d2 inc d3 inc d4 wait not allowed loopend0 Rule L L 2 A DOENn or MOVE like instruction that writes a LCn register is not allowed at LA 2 LA 1 or LA of the same long loop n Example 7 55 LCn Write at the End of Long Loop n doen1 5 not allowed mo...

Page 282: ...te the SR register This rule does not apply to other instructions that affect status bits in SR Example 7 56 Instructions in Short Loops doensh0 10 nop loopstart0 jmp end not allowed loopend0 doensh1 count2 move w num d2 loopstart1 doen1 5 not allowed loopend1 Rule L L 4 The LA of a short loop cannot be at LA 1 of a long loop Example 7 57 Short Loop LA at the End of a Long Loop dosetup0 label1 doe...

Page 283: ...PLS instruction Any DOENn Dn data register Any DOENSHn Dn data register MOVE like instruction that writes any LCn register Example 7 58 LCn Write to SKIPLS Instruction doen0 d2 skipls label4 not allowed Rule L D 2 The minimum number of VLES between the following instructions that write a LCn register and LA of the same long loop n is DOENn Rn or x three VLES address register or immediate value DOE...

Page 284: ...sh0 r0 allowed move l d1 lc0 not allowed move w 2 d2 loopstart0 inc d1 loopend0 Rule L D 5 The minimum number of VLES between an instruction that writes any LCn register and a CONT CONTD instruction is Any DOENn Rn or x one VLES address register or immediate value Any DOENn Dn two VLES data register MOVE like instruction that writes any LCn register two VLES Example 7 61 LCn Write to CONT D Instru...

Page 285: ...ction doen1 5 dosetup1 label1 loopstart1 label1 cont label2 not allowed inc d0 move w 23 d2 move w beef d3 loopend1 label2 inc d1 Rule L D 8 A MOVE like instruction that reads a LCn register is not allowed at the LA 3 LA 2 LA 1 and LA of the same long loop Rule L D 9 At least one VLES is required between a MOVE like instruction that reads a LCn register and SA of the same short loop n Example 7 64...

Page 286: ...ots doensh1 5 cmpeq w 3 d0 jf _dest not allowed inc d0 loopstart1 inc d0 _dest add d1 d2 d3 loopend1 Rule L C 2 COF instructions WAIT and STOP are not allowed at LA 2 of a long loop Example 7 66 COF Instructions at LA 2 of a Long Loop dosetup1 label1 doen1 n2 move l mem_l1 r1 move l mem_l2 r0 loopstart1 label1 inc d1 jsr r1 LA 2 not allowed add d1 d2 d3 LA 1 move w d3 r0 LA loopend1 bra label2 Rul...

Page 287: ...nce Manual 7 37 Rule L C 5 A Bc or Jc instruction is not allowed at LA 3 of a long loop Example 7 68 Bc Jc at LA 3 of a Long Loop dosetup1 label7 move w 0 d1 doen1 5 loopstart1 label7 inc d1 bf label6 LA 3 not allowed inc d2 inc d3 inc d4 loopend1 ...

Page 288: ...ame Loop dosetup3 label1 doen3 5 loopstart3 label1 inc d1 inc d2 break label2 not allowed inc d3 inc d4 label2 inc d5 loopend3 dosetup3 label1 doen3 d0 nop skipls label2 allowed loopstart3 label1 inc d1 inc d2 inc d3 inc d4 inc d5 loopend3 label2 nop dosetup2 label1 doen2 6 nop loopstart2 label1 cont next not allowed nop inc d0 dosetup3 label2 doen3 5 loopstart3 label2 inc d1 next inc d2 inc d3 in...

Page 289: ... doen1 10 loopstart1 doen2 d0 skipls _dest not allowed loopstart2 loopend2 _dest nop nop last address of long loop 1 loopend1 nop last address of long loop 0 loopend0 Rule L C 10 A BSR BSRD JSR or JSRD instruction cannot have a COF destination that is LA 2 of a long loop or SA of a short loop Example 7 71 Subroutine Call to End of Loops dosetup0 label1 doen0 d1 nop nop loopstart0 label1 nop nop js...

Page 290: ...wed loopstart0 nop loopend0 7 5 11 General Looping Rules Rule L G 3 A MOVE like instruction that reads the SR register is not allowed at the LA 3 LA 2 LA 1 and LA of any long loop Example 7 74 SR Read to LA of Any Long Loop dosetup1 label1 doen1 5 loopstart1 label1 inc d1 move l sr d0 not allowed inc d2 move l mem_l1 r1 move l mem_l2 r0 loopend1 Rule L G 4 At least one VLES is required between a M...

Page 291: ...ion depends on the test coverage of the programmer s test suite Programmers should exercise all COF destinations exception service routines and system configurations such as conditional assembly directives in the simulation trace so the simulator detects all dynamic programming rules The simulation trace should also exercise all data dependencies of conditional COF instructions such as Bc and Jc c...

Page 292: ... a pre calculated address to the same memory location These memory accesses must write to different locations so the order that multiple accesses occur does not change the memory results If this is not done the memory contents of the accessed locations are undefined For mutually exclusive IFc subgroups in a VLES this rule applies independently to each subgroup Example 7 79 Pre Calculated Memory Ac...

Page 293: ... and builds on the return address using RAS Example 7 81 Illegal use of RAS value move ld6 sp 8 adda 8 sp rts move l d7 sp c not allowed since RAS may be valid 7 6 4 Loop Rules The loop COF instructions produce undefined results if all loops are disabled Since the assembler cannot know the LFn state when these instructions execute the simulator detects this programming rule Good loop programming p...

Page 294: ...ulator can detect it from the simulation trace Example 7 82 SR 2 Across a COF Boundary pop sr bra fred fred add d1 d2 d3 not allowed by SR 2 The assembler cannot detect the A 2 violation between the delay slot and the COF destination shown below but the simulator can detect it from the simulation trace Example 7 83 A 2 from a Delay Slot to a COF Destination jmpd _dest bmset 3 r0 l 2 cycle instruct...

Page 295: ...execution flow including the delay slot and the instructions in the destination flow The relevant VLES based rules that the simulator detects across COF boundaries are Non loop COF rules T 1 SR 2 SR 4 Loop COF rules L L 5 L L 6 L D 1 L D 2 L D 3 L D 5 L D 6 L D 7 L D 8 L D 9 L C 10 L G 3 L G 4 Example 7 84 Set condition during a COF and use it at the destination T 1 bt _des1cmpeq d0 d1 _des1 ift t...

Page 296: ...on service routine This rule does not apply to instructions that are affected by the EXP status bit in SR The assembler mapped instruction CLR Dn is never affected by the SR status bits even though it is implemented as SUB Da Da Dn Therefore this rule applies to the SUB instruction but not to CLR SUB Da Da Dn is taken as CLR in this context Rule SR 4b MOVE like instructions that reads or writes th...

Page 297: ...t move w r0 d0 use MCTL not allowed ISR Start nop move w r0 d0 use MCTL not allowed ISR Start nop nop move w r0 d0 use MCTL allowed ISR Start adda r0 r1 use MCTL not allowed ISR Start move w d1 r0 n0 use MCTL not allowed ISR Start move w r0 d0 use MCTL not allowed ISR Start move w r1 d0 use MCTL not allowed ISR Start move w r5 d0 use MCTL not allowed ISR Start adda r8 r1 use MCTL not allowed ISR S...

Page 298: ...lowed _dest mac d0 d1 d2 mac d3 d4 d5 The assembler evaluates the address of a VLES label as the start lowest address of a VLES regardless of its source position in the VLES Good programming practice always places COF destination labels before or at the start of a VLES Programmers should be careful that computed COF destinations are the start of a VLES This will ensure that rule J 1 is enforced Ru...

Page 299: ... Loop COF Instructions on page A 18 for enabling and terminating loops The programmer should not change the LFn and SLF status bits in SR while a loop is enabled This will ensure that rule L N 5 is enforced 7 7 1 Rules Not Detected Across COF Boundaries The simulator cannot detect all rules across COF boundaries This may be due to limited analysis of the execution trace or missing information in t...

Page 300: ...d parameter values may produce undefined results Also observe address pointer alignments specific to the selected modifier mode MOVES should be preceded by an instruction that updates the Ln bit based on the data Otherwise the data moved may be modified by a Ln bit not associated with the data Do not explicitly modify the SR register to change the loop flags LFn and SLF in SR Use the loop control ...

Page 301: ...n in Section 7 5 1 Hardware Loop Detection on page 7 7 Do not reassemble disassembled code The disassembled code may contain hardware loop LPMARKx prefix instructions that are not supported in SC140 source code Use one LOOPSTARTn and LOOPENDn directive to mark the hardware loop body n in the assembly source code Write endian independent code wherever possible Document code that is endian specific ...

Page 302: ...ly source order 7 8 3 Dynamic Programming Rules The LPMARK rules in this section are alternate forms of SC140 programming rules detectable from the prefix encoding Source code that complies with the assembly notation rules is by definition compliant with LPMARK rules These LPMARK rules allow the simulator to detect dynamic programming rules that are not detectable by the assembler 7 8 3 1 LPMARK N...

Page 303: ... 7 8 3 2 Loop Nesting Rules LPMARK Rule L N 5 At least one LFn status bit in SR must be set at LPA or LPB of a loop Example 7 91 LFn Enabled at LPA or LPB dosetup1 label1 doen1 5 pop sr pop clears all LFn label1 nop lpmarkb set not allowed nop nop 7 8 3 3 Loop LA Rules LPMARK Rule L L 1 The following instructions are not allowed at LPB 1 or LPB 2 of a long loop COF instructions STOP and WAIT DI DE...

Page 304: ...DEBUG DOENn DOENSHn MOVE like instructions that read any LCn register MOVE like instructions that write any LCn register MOVE like instructions that read the SR register MOVE like instructions that write the SR register This rule does not apply to other instructions that affect status bits in SR Example 7 94 Instructions in Short Loops move w count2 r6 doensh0 r6 move w 3 d3 inc d3 lpmarkb set wai...

Page 305: ...n that writes the active LCn register two VLES Example 7 95 Active LCn Write at the Start of a Loop move w 3 d0 doensh0 d0 allowed move l d1 lc0 not allowed move w 2 d2 inc d1 lpmarka set move w 3 r8 dosetup1 label1 doen1 r8 not allowed label1 inc d3 lpmarkb set inc d4 inc d5 LPMARK Rule L D 6 At least one VLES is required between an instruction that writes the active SAn register and LPA or LPB o...

Page 306: ...ount2 d6 dosetup0 label2 doen0 d6 move w 1 d1 move w 2 d2 move w 3 d3 move w 4 d4 label2 inc d1 move l lc0 d0 not allowed inc d2 lpmarkb set inc d3 inc d4 move w count2 d6 dosetup0 label2 doen0 d6 move w 1 d1 move w 2 d2 move w 3 d3 move w 4 d4 label2 inc d1 move l lc1 d0 allowed inc d2 lpmarkb set inc d3 inc d4 7 8 3 5 Loop COF Rules LPMARK Rule L C 2 COF instructions are not allowed at LPB of a ...

Page 307: ...markb set not allowed add d1 d2 d3 move w d3 r0 LPMARK Rule L C 3 L C 5 A Bc or Jc instruction is not allowed at LPA 1 or LPB 1 of a loop Example 7 99 Bc Jc at the Start of a Loop cmpgt d4 d3 nop iff doensh3 count2 bt _dest not allowed inc d2 lpmarka set _dest inc d2 dosetup1 label7 move w 0 d1 doen1 5 move w 10 d2 label7 inc d1 bf label6 not allowed inc d2 lpmarkb set inc d3 inc d4 ...

Page 308: ...dest not allowed nop ift break label nop nop lpmarkb set nop nop nop lpmarkb set _dest nop lpmarkb set label nop lpmarka set last address of long loop 1 nop last address of long loop 0 LPMARK Rule L C 10 A BSR BSRD JSR or JSRD instruction cannot have a COF destination that is at LPA or LPB of a loop Example 7 101 Subroutine Call to End of Loops dosetup0 label1 doen0 d1 nop nop label1 nop nop jsr l...

Page 309: ... register and LPA or LPB of a loop Example 7 103 SR Read to LPA or LPB of a Loop dosetup1 label1 doen1 5 label1 inc d1 move l sr d0 not allowed inc d2 lpmarkb set move l mem_l1 r1 move l mem_l2 r0 doensh0 10 push sr not allowed inc d0 lpmarka set 7 8 3 7 Rule Detection Across Exception Boundaries LPMARK Rule SR 6 LPA or LPB cannot be the first two VLES of an exception service routine 7 8 4 LPMARK ...

Page 310: ... the CRM In this discussion an assembler generated NOP encoding not present in the source code will be called a PAD 2 A NOP is defined in the CRM Appendix A as a source syntax having a 1W prefix encoding that can be used in a standalone NOP only VLES or embedded in a baseline VLES having a prefix The binary encoding of the standalone NOP is a 1W prefix having the VLES size in the aaa field and the...

Page 311: ...roup1 IFA NOP IFT prefix ccc 010 group1 NOP IFF subgroup1 IFA NOP IFF prefix ccc 011 group1 NOP IFT subgroup1 IFF NOP IFT prefix ccc 010 group1 NOP IFT NOP IFF subgroup2 IFF prefix ccc 011 group2 NOP This mapping converts each NOP only conditional group or subgroup to embedded NOPs concatenated with a conditional group no subgroups This is necessary to ensure that each NOP adds exactly one word to...

Page 312: ...ix 2W MOVE PAD 2W MOVE NOP NOP 4 If a VLES has only NOPs the first source NOP is encoded as the VLES prefix For example NOPNOP NOP is encoded as 1W prefix NOP NOP 5 If a baseline VLES has a NOP as the only instruction in a conditional subgroup a 1W embedded NOP is encoded for each source NOP For example IFT CLR D0IFF NOP is assembler mapped to the IFT prefix and encoded as 1W IFT prefix CLR NOP an...

Page 313: ...FF CLR D8IFT INC D1 IFT NOP is encoded ignoring the NOP subgroup as 2W IFT IFF prefix CLR INC NOP 7 If a baseline VLES has multiple NOPs in a conditional subgroup a 1W embedded NOP is encoded for each source NOP For example IFT CLR D0IFT NOP IFT NOP is encoded as 1W IFT prefix CLR NOP NOP ...

Page 314: ...7 64 SC140 DSP Core Reference Manual NOP Definition ...

Page 315: ...dix Each non prefix instruction activates one functional unit in the SC140 architecture The architecture can be viewed as several functional units operating in parallel Four arithmetic logic units ALUs Two address arithmetic units AAUs One bit mask unit BMU One program controller PSEQ Several instructions can be grouped together for parallel execution The instruction set has been designed to enabl...

Page 316: ...gle source data register De Even numbered data core register Dn Destination data register Do Odd numbered data core register DR Data or address register Ea Effective address HP High portion bits 31 16 of a register Ln Limit tag bit LP Low portion bits 15 0 of a register rc Rounding constant Rn Address register rx AGU source register Rx AGU source destination register If used at the end of a line t...

Page 317: ...rithmetic right shift sign bits shifted right Arithmetic or logical left shift functionally the same Logical right shift Compare for greater than Rnd Rounding function x y Concatenation of x and y Table A 3 Register Abbreviations Abbreviation Register Name D0 D15 General purpose data register R0 R15 General purpose address register EMR Exception and mode register VBA Vector base address register S...

Page 318: ... these numbers is 0 u3 25 L The values for u3 in the source code and disassembled code will be multiples of four from 0 to 28 The 3 bit encoded values in the instruction will be zero to seven Other notations for address alignment are W for word multiples of two Q for quad multiples of eight The ranges shown in the brackets are always for the source code addressing The ranges may or may not reflect...

Page 319: ...n N3 Table A 5 Addressing Mode Notation for the EA Operand Addressing Mode Definition Notation in the Instruction Field Indexed by offset in N0 Rn N0 Post decrement Rn No update Rn Post increment Rn Post update by offset in N0 Rn N0 Post update by offset in N1 Rn N1 Post update by offset in N2 Rn N2 Post update by offset in N3 Rn N3 Note Rn is taken from the Rn RRR table found in the instruction d...

Page 320: ...e to the definition of the field For example in the MOVE B instruction the encoding for the opcode is The order of bits for a16 AAA A is the MSB in the first bit at the left most position in word 1 The LSB is the right most position in word 2 If written out fully the encoding would be A more complicated example is for BSR where two fields are intermixed The order for each field is maintained monot...

Page 321: ...ding bits are needed These bits are allocated in the two word prefix A two word prefix includes a field for each execution unit in the SC140 four fields for DALU instructions and two fields for AGU instructions DALU instructions have a maximum of three operands so each DALU field is 3 bits wide AGU instructions have a maximum of two operands so each AGU field is two bits wide This provides an enco...

Page 322: ...ally executed 001 If true D0 D2 A0 If false D1 D3 A1 010 If true all the set 011 If false all the set 100 Reserved 101 Reserved 110 If true D0 D2 A0 always D1 D3 A1 111 If false D0 D2 A0 always D1 D3 A1 p lpmarkB bit In the case of a loop with three or more execution sets the lpmarkB bit is a one in the execution set that is two before the last execution set in the loop Example lpmarkB set LA 2 se...

Page 323: ...s to signify that more prefix words are concatenated to support architectures with 3 or more prefix words Use of a 2 w prefix in the middle of the set is reserved for future encoding such as accelerator or predication instructions and should not be placed as a NOP ccc Conditional execution of the entire execution set In the following table true false relates to the state of the T bit in SR D0 D1 D...

Page 324: ...ll DALU instructions For three operand instructions inst op1 op2 op3 1 high data register is used for the op3 field E3 is set 1 high data register is used for the op1 field E2 is set 1 high data register is used for the op2 field E1 is set In case of two operand MAC unit instructions only E1 and E3 are used In case of one operand MAC unit instructions only E3 is used In case of four operand instru...

Page 325: ...tions Rx operand defined with RRRR field Df operand defined with hhh field of MOVE L Df C4 and MOVE L C4 Df instructions The h bit is used for all the operands other then the above The expansion encoding have no effect if the register decoded in the instruction is not R0 R7 e g SP in RRRR field for Rx decoding Fields representing multiple registers used in some MOVE like instructns are affected to...

Page 326: ...ing They are decoded by the dispatcher but are not dispatched to an execution unit All PREFIX instructions are listed in Table A 16 A 1 6 1 Instruction Sub types The instruction types can be further divided into sub types as follows DALU Instruction Sub types Data arithmetic including multiply accumulate instructions are listed in Table A 7 and described in Section 2 2 1 2 Multiply Accumulate MAC ...

Page 327: ...ply accumulate unsigned integers first source from low portion second from high portion IMACUS Multiply accumulate unsigned integer and signed integer IMPY Multiply signed integers in data registers IMPY W Multiply signed immediate and signed integer in data register IMPYHLUU Multiply unsigned integer and unsigned integer first source from high portion second from low portion IMPYSU Multiply signe...

Page 328: ...r transfer if the T bit is clear TFRT Conditional data register transfer if the T bit is set TSTEQ Test for equal to zero TSTGE Test for greater than or equal to zero TSTGT Test for greater than zero Table A 8 DALU Logical Instructions BFU Instruction Description AND Logical AND ASLL Multi bit arithmetic shift left ASLW Word arithmetic shift left 16 bit shift ASRR Multi bit arithmetic shift right ...

Page 329: ...t ASLA Arithmetic shift left 32 bit ASRA Arithmetic shift right 32 bit CMPEQA Compare for equal CMPGTA Compare for greater than CMPHIA Compare for higher unsigned DECA Decrement register DECEQA Decrement and set T if zero DECGEA Decrement and set T if equal or greater than zero INCA Increment register LSRA Logical shift right 32 bit SUBA Subtract affected by the modifier mode SXTA B Sign extend by...

Page 330: ... two fractional words to memory with scaling and limiting enabled MOVES 4F Move four fractional words to memory with scaling and limiting enabled MOVES F Move fractional word to memory with scaling and limiting enabled MOVES L Move long to memory with scaling and limiting enabled MOVEU B Move unsigned byte from memory MOVEU L Move unsigned long from immediate VSL 2F Viterbi shift left special move...

Page 331: ...he T bit if every bit position that has the value 1 in the mask is 0 in an operand BMTSTS Bit mask test if set Sets the T bit if every bit position that has the value 1 in the mask is 1 in an operand BMTSTS W Bit mask test if set in memory Sets the T bit if every bit position that has the value 1 in the mask is 1 in an operand EOR Logical Exclusive OR on a 16 bit operand NOT Binary inversion of a ...

Page 332: ...op n as a short loop DOSETUPn Setup loop start address n SKIPLS Test the active LC and skip the loop if LCn is equal or smaller than zero Table A 15 AGU Program Control Instructions Instruction Description DEBUG Enter debug mode DEBUGEV Signal debug event DI Disable interrupts sets the DI bit in the status register EI Enable interrupts clears the DI bit in the status register ILLEGAL Trigger an im...

Page 333: ...embler syntax One to three words 16 bits per word of bits defining the opcode as the core decodes it Number of words in memory used by this instruction The number of cycles used in execution of this instruction Addressing modes and the machine s state The instruction s type relevant to non prefix grouping See Instruction Fields Optional section added when the instruction has one or more operands E...

Page 334: ...hmetic saturation mode SR 5 4 S 1 0 Scaling mode bits determine which bits in the result are used in the Ln bit calculation Register Address Bit Name Description EMR 2 DOVF Set if the result cannot be represented in 40 bits or if the result saturates to 32 bits in arithmetic saturation mode Ln L If not in arithmetic saturation mode SR SM 0 calculates and updates the Ln bit in the destination regis...

Page 335: ...rouping encoding Instruction Fields Dn FFF Single Source Destination Data Register Instruction Words Cycles Type Opcode 15 8 7 0 ABS Dn 1 1 1 0 1 0 0 1 F F F 1 1 0 0 1 1 0 000 D0 010 D2 100 D4 110 D6 001 D1 011 D3 101 D5 111 D7 Note This instruction can specify D8 D15 as operands by using a prefix ...

Page 336: ...s set correctly for multiple precision arithmetic using long word operands if the extension of the destination data register is the sign extension of bit 31 Register Address Bit Name Description SR 0 C Added as a carry bit to the LSB SR 5 4 S 1 0 The scaling mode bits determine which bits in the result are used in the Ln bit calculation Register Address Bit Name Description EMR 2 DOVF Set if the r...

Page 337: ...encoding Instruction Fields Dc Dd ee Data Register Pairs EMR 0000 0000 Instruction Words Cycles Type Opcode 15 8 7 0 ADC Dc Dd 1 1 1 0 1 0 1 1 e e 0 1 1 1 1 0 1 0 00 D0 D1 01 D2 D3 10 D4 D5 11 D6 D7 Note This instruction can specify D8 D15 as operands by using a prefix Register Memory Address Before After ...

Page 338: ...b Dn Adds two source data registers Da and Db and stores the result in a destination data register Dn Register Address Bit Name Description SR 2 SM If set selects 32 bit arithmetic saturation mode SR 5 4 S 1 0 Scaling mode bits determine which bits in the result are used in the Ln bit calculation Register Address Bit Name Description SR 0 C Calculates and updates the C bit in the status register E...

Page 339: ...s serial grouping encoding L2 D2 0 00 0000 0007 EMR 0000 0000 Register Memory Address Before After SR 00E0 0000 D1 00 72E3 8F2A D0 00 7216 EE3C L2 D2 1 00 E4FA 7D66 EMR 0000 0000 Instruction Words Cycles Type Opcode 15 8 7 0 ADD u5 Dn 1 1 1 0 1 1 1 0 F F F 1 0 i i i i i 15 8 7 0 ADD Da Db Dn 1 1 1 0 1 0 1 1 F F F 1 0 J J J J J 15 8 7 0 ADD Da Da Dn 1 1 1 0 1 0 0 0 F F F 1 1 0 0 0 j j Register Memo...

Page 340: ... D1 D6 01110 D3 D6 10110 D4 D6 11110 D6 D6 00111 D1 D7 01111 D3 D7 10111 D4 D7 11111 D6 D7 Notes 1 This instruction can specify D8 D15 as operands by using a prefix 2 Register pair order can be reversed for clarity because the order of operation is not important for add operations 3 The JJJJJ encoding does not include the pairs D1 D1 D3 D3 D5 D5 D7 D7 These are covered in the jj encoding 00 D1 D1 ...

Page 341: ...rforms a 32 bit addition of source registers Da and Dn with carry disabled between bits 15 and 16 so that the high and low words of each register are added separately The result is stored back in Dn The extension byte of the result is undefined Register Address Bit Name Description Ln L Clears the Ln bit in the destination register Register Memory Address Before After D0 00 1100 1100 L1 D1 0 00 22...

Page 342: ...Data Register Instruction Words Cycles Type Opcode 15 8 7 0 ADD2 Da Dn 1 1 2 1 1 0 1 0 0 F F F 1 0 0 0 J J J 000 D0 010 D2 100 D4 110 D6 001 D1 011 D3 101 D5 111 D7 Note This instruction can specify D8 D15 as operands by using a prefix 000 D0 010 D2 100 D4 110 D6 001 D1 011 D3 101 D5 111 D7 Note This instruction can specify D8 D15 as operands by using a prefix ...

Page 343: ... the stack pointer is the destination operand then the immediate value must be a multiple of eight as its three LSBs are forced to zero ADDA s16 rx Rn Adds an immediate signed 16 bit integer and the contents of a source AGU register rx and stores the result in a destination address register Rn The 16 bits of the signed integer are right aligned and the upper bits are sign extended to form a 32 bit...

Page 344: ...ore After MCTL 0000 0000 R0 0000 1100 R1 0000 2200 0000 3300 Register Memory Address Before After MCTL 00000008 R0 0000000c R1 00000000 00000004 Instruction Words Cycles Type Opcode 15 8 7 0 ADDA u5 Rx 1 1 2 1 1 1 0 R R R R 0 1 0 i i i i i 15 8 7 0 ADDA s16 rx Rn 2 1 4 0 0 1 0 r r r r i i i 0 1 R R R 1 0 0 i i i i i i i i i i i i i 15 8 7 0 ADDA rx Rx 1 1 2 1 1 1 0 R R R R 0 0 0 1 r r r r 000 R0 0...

Page 345: ... N3 0111 SP 1011 R3 1111 R7 Note This instruction can specify R8 R15 as operands by using a high register prefix 0000 N0 0100 1000 R0 1100 R4 0001 N1 0101 1001 R1 1101 R5 0010 N2 0110 1010 R2 1110 R6 0011 N3 0111 SP 1011 R3 1111 R7 Note This instruction can specify R8 R15 as operands by using a high register prefix u5 iiiii 5 bit unsigned immediate data s16 iiiiiiiiiiiiiiii 16 bit signed immediate...

Page 346: ...econd source AGU register Rx The sum is stored back in Rx For R0 R7 destinations the operation is affected by the modifier mode selected in MCTL Register Address Bit Name Description SR 18 EXP Determines which stack pointer is used when the stack pointer is an operand Otherwise the instruction is not affected by SR MCTL 31 0 AM3 AM0 Address modification bits when updating R0 R7 Otherwise the instr...

Page 347: ...0 R R R R 0 0 0 0 r r r r 0000 N0 0100 1000 R0 1100 R4 0001 N1 0101 1001 R1 1101 R5 0010 N2 0110 PC 1010 R2 1110 R6 0011 N3 0111 SP 1011 R3 1111 R7 Note This instruction can specify R8 R15 as operands by using a high register prefix 0000 N0 0100 1000 R0 1100 R4 0001 N1 0101 1001 R1 1101 R5 0010 N2 0110 1010 R2 1110 R6 0011 N3 0111 SP 1011 R3 1111 R7 Note This instruction can specify R8 R15 as oper...

Page 348: ... to another AGU source register Rx and stores the sum in the destination second register Rx For R0 R7 destinations the operation is affected by the modifier mode selected in MCTL Register Address Bit Name Description SR 18 EXP Determines which stack pointer is used when the stack pointer is an operand Otherwise the instruction is not affected by SR MCTL 31 0 AM3 AM0 Address modification bits when ...

Page 349: ...0 R R R R 0 0 1 0 r r r r 0000 N0 0100 1000 R0 1100 R4 0001 N1 0101 1001 R1 1101 R5 0010 N2 0110 PC 1010 R2 1110 R6 0011 N3 0111 SP 1011 R3 1111 R7 Note This instruction can specify R8 R15 as operands by using a high register prefix 0000 N0 0100 1000 R0 1100 R4 0001 N1 0101 1001 R1 1101 R5 0010 N2 0110 1010 R2 1110 R6 0011 N3 0111 SP 1011 R3 1111 R7 Note This instruction can specify R8 R15 as oper...

Page 350: ...n The carry bit is not affected by this instruction Register Address Bit Name Description SR 2 SM If set selects 32 bit arithmetic saturation mode SR 5 4 S 1 0 The scaling mode bits determine which bits in the result are used in the Ln bit calculation Register Address Bit Name Description EMR 3 DOVF Set if the result cannot be represented in 40 bits or if the result saturates to 32 bits in arithme...

Page 351: ...e Opcode 15 8 7 0 ADDNC s16 Da Dn 2 1 4 0 0 1 1 J J J 1 i i i 0 0 F F F 1 0 0 i i i i i i i i i i i i i 000 D0 010 D2 100 D4 110 D6 001 D1 011 D3 101 D5 111 D7 Note This instruction can specify D8 D15 as operands by using a prefix 000 D0 010 D2 100 D4 110 D6 001 D1 011 D3 101 D5 111 D7 Note This instruction can specify D8 D15 as operands by using a prefix s16 iiiiiiiiiiiiiiii 16 bit signed immedia...

Page 352: ...two modes of the round function Rnd are described on page A 359 Register Address Bit Name Description SR 2 SM If set selects 32 bit arithmetic saturation mode SR 3 RM Rounding mode SR 5 4 S 1 0 The scaling mode bits determine which bits in the result are used in the Ln bit calculation and which bits are used in rounding Register Address Bit Name Description EMR 2 DOVF Set if the result cannot be r...

Page 353: ...e Source Destination Data Register Instruction Words Cycles Type Opcode 15 8 7 0 ADR Da Dn 1 1 1 0 1 1 0 0 F F F 1 0 0 0 J J J 000 D0 010 D2 100 D4 110 D6 001 D1 011 D3 101 D5 111 D7 Note This instruction can specify D8 D15 as operands by using a prefix 000 D0 010 D2 100 D4 110 D6 001 D1 011 D3 101 D5 111 D7 Note This instruction can specify D8 D15 as operands by using a prefix ...

Page 354: ...re used here for clarity For example given an immediate value of 27A6 using D0 as the source data register and using D1 as the destination data register this instruction would be written as and 027a6 d0 d1 AND u16 0000 Da Dn A 40 bit operand is formed with zeros in bits 15 0 the immediate word in bits 31 16 and bit 31 copied to bits 39 32 sign extended This operand is then ANDed with the contents ...

Page 355: ...o ffff2e0000 before the AND operation with D2 Register Address Bit Name Description Ln L Clears the Ln bit in the destination register Register Memory Address Before After D2 FF CE66 47F2 L1 D1 0 FF D859 6705 0 FF C840 4700 Register Memory Address Before After immediate 00 0000 FF2E D2 00 27A6 98FB L1 D1 0 00 0000 982A Register Memory Address Before After immediate FF FF2E 0000 D2 F0 27A6 98FB L1 ...

Page 356: ... i i i i i i i i 15 8 7 0 AND Da Dn 1 1 2 1 1 0 1 1 1 F F F 0 0 0 0 J J J 000 D0 010 D2 100 D4 110 D6 001 D1 011 D3 101 D5 111 D7 Note This instruction can specify D8 D15 as operands by using a prefix 000 D0 010 D2 100 D4 110 D6 001 D1 011 D3 101 D5 111 D7 Note This instruction can specify D8 D15 as operands by using a prefix 0 u16 0000000000000000 iiiiiiiiiiiiiiii 16 bit unsigned immediate data i...

Page 357: ...ress register DR The HP of the register is unaffected Note This instruction is assembler mapped to BMCLR u16 DR L where u16 is the bitwise complement of u16 AND u16 DR H Performs a bitwise AND on an immediate unsigned word and the contents of the HP of a data or address register DR Stores the result in the HP of the data or address register DR The LP of the register is unaffected Note This instruc...

Page 358: ...H H 1 0 1 i i i i i i i i i i i i i 15 8 7 0 AND u16 DR H 2 2 3 0 0 0 0 1 0 0 0 i i i 1 H H H H 1 0 1 i i i i i i i i i i i i i 0000 D0 0100 D4 1000 R0 1100 R4 0001 D1 0101 D5 1001 R1 1101 R5 0010 D2 0110 D6 1010 R2 1110 R6 0011 D3 0111 D7 1011 R3 1111 R7 Note This instruction can specify D8 D15 or R8 R15 as operands by using a a prefix prefix u16 iiiiiiiiiiiiiiii One s complement of 16 bit unsign...

Page 359: ... same memory address Note This instruction is assembler mapped to BMCLR W u16 Rn where u16 is the one s complement of u16 AND W u16 SP u5 Performs a bitwise AND on a 16 bit unsigned immediate value and the contents of a memory address pointed to by a 5 bit unsigned offset subtracted from SP Stores the result in the same memory address The address offset must be even Note This instruction is assemb...

Page 360: ...ample and w 54a1 r7 Register Address Bit Name Description SR 18 EXP Determines which stack pointer is used when the stack pointer is an operand Otherwise the instruction is not affected by SR Register Memory Address Before After immediate 54A1 R7 50 50 15AF 14A1 In binary 54A1 0101010010100001 15AF 0001010110101111 and 14A1 0001010010100001 ...

Page 361: ... 1 0 0 0 A A A i i 0 0 1 0 0 1 A A A A A A A A A A A A A 1 0 i i i i i i i i i i i i i i 15 8 7 0 AND W u16 SP s16 3 3 3 0 0 1 1 1 0 0 0 A A A i i 0 1 1 0 0 1 A A A A A A A A A A A A A 1 0 i i i i i i i i i i i i i i 000 R0 010 R2 100 R4 110 R6 001 R1 011 R3 101 R5 111 R7 Note This instruction can specify R8 R15 as operands by using a high register prefix a16 AAAAAAAAAAAAAAAA 16 bit unsigned absol...

Page 362: ...umbered data register and ADD Da Da Dn if Da is an odd numbered data register Register Address Bit Name Description SR 2 SM If set selects 32 bit arithmetic saturation mode SR 5 4 S 1 0 Scaling mode bits determine which bits in the result are used in the Ln bit calculation Register Address Bit Name Description SR 0 C Bit Da 39 is stored in the carry bit Ln L If not in arithmetic saturation mode SR...

Page 363: ...00 D2 D2 00101 D1 D5 01101 D3 D5 10101 D4 D5 11101 D2 D3 00110 D1 D6 01110 D3 D6 10110 D4 D6 11110 D6 D6 00111 D1 D7 01111 D3 D7 10111 D4 D7 11111 D6 D7 Notes 1 This instruction can specify D8 D15 as operands by using a prefix Each register of a pair can be separately encoded as the higher register For example D0 D4 can be changed to D8 D4 by use of a prefix 2 Register pair order can be reversed f...

Page 364: ...two bits Bits 29 0 are copied into bits 31 2 Bits 1 0 are cleared Register Address Bit Name Description SR 18 EXP Determines which stack pointer is used when the stack pointer is an operand Otherwise the instruction is not affected by SR Register Memory Address Before After R0 e001 0002 8004 0008 Instruction Words Cycles Type Opcode 15 8 7 0 ASL2A Rx 1 1 2 1 1 1 0 R R R R 1 1 1 1 1 1 1 0 0000 N0 0...

Page 365: ...one bit Bits 30 0 are copied into bits 31 1 Bit 0 is cleared Register Address Bit Name Description SR 18 EXP Determines which stack pointer is used when the stack pointer is an operand Otherwise the instruction is not affected by SR Register Memory Address Before After R0 e001 0002 c002 0004 Instruction Words Cycles Type Opcode 15 8 7 0 ASLA Rx 1 1 2 1 1 1 0 R R R R 1 1 1 1 1 1 0 0 0000 N0 0100 10...

Page 366: ...n else Dn Da 6 0 Dn ASLL Da Dn 40 Da 6 0 40 ASLL u5 Dn Shifts left by u5 an immediate unsigned 5 bit integer The vacated positions to the right are zero filled ASLL Da Dn Performs a bidirectional arithmetic shift of Dn by Da 6 0 bits and stores the result in Dn If Da 6 0 is positive the shift is left If shifting left the vacated positions to the right are zero filled If Da 6 0 is negative the shif...

Page 367: ...e After D0 00 0000 0003 L1 D1 0 FF A572 A572 0 FD 2B95 2B90 SR 00E0 0000 00E0 0001 EMR 0000 0000 Register Memory Address Before After D0 FF FFFF FFFD L1 D1 0 FF A572 A572 0 FF F4AE 54AE SR 00E4 0000 00E4 0000 EMR 0000 0000 1 1 1 1 1 C 1 1 1 1 1 0 1 0 0 1 0 1 0 1 1 1 0 0 1 0 1 0 1 0 0 1 0 1 0 1 1 1 0 0 1 0 1 1 1 1 1 1 0 1 0 0 1 0 1 0 1 1 1 0 0 1 0 1 0 1 0 0 1 0 1 0 1 1 1 0 0 1 0 0 0 0 0 1 6 3 2 3 9...

Page 368: ...ords Cycles Type Opcode 15 8 7 0 ASLL u5 Dn 1 1 1 0 1 1 1 1 F F F 1 0 i i i i i 15 8 7 0 ASLL Da Dn 1 1 2 1 1 0 1 0 1 F F F 0 0 1 0 J J J 000 D0 010 D2 100 D4 110 D6 001 D1 011 D3 101 D5 111 D7 Note This instruction can specify D8 D15 as operands by using a prefix 000 D0 010 D2 100 D4 110 D6 001 D1 011 D3 101 D5 111 D7 Note This instruction can specify D8 D15 as operands by using a prefix u5 iiiii...

Page 369: ... source register are copied into bits 39 16 of the destination register Bits 15 0 of the destination register are cleared Register Address Bit Name Description SR 0 C Bit Da 24 is stored in the carry bit EMR 2 DOVF Set if the result cannot be represented in 40 bits Ln L Clears the Ln bit in the destination register Register Memory Address Before After D0 FF A572 A572 L1 D1 0 00 0000 0000 0 72 A572...

Page 370: ...Data Register Instruction Words Cycles Type Opcode 15 8 7 0 ASLW Da Dn 1 1 2 1 1 0 1 1 0 F F F 0 0 1 0 J J J 000 D0 010 D2 100 D4 110 D6 001 D1 011 D3 101 D5 111 D7 Note This instruction can specify D8 D15 as operands by using a prefix 000 D0 010 D2 100 D4 110 D6 001 D1 011 D3 101 D5 111 D7 Note This instruction can specify D8 D15 as operands by using a prefix ...

Page 371: ...e source register is copied into bit 39 of the destination register Register Address Bit Name Description SR 2 SM If set selects 32 bit arithmetic saturation mode SR 5 4 S 1 0 Scaling mode bits determine which bits in the result are used in the Ln bit calculation Register Address Bit Name Description SR 0 C Da 0 is stored in the carry bit Ln L If not in arithmetic saturation mode SR SM 0 calculate...

Page 372: ... 00E4 0000 00E4 0001 EMR 0000 0000 Instruction Words Cycles Type Opcode 15 8 7 0 ASR Da Dn 1 1 1 0 1 1 0 1 F F F 1 0 0 0 J J J 000 D0 010 D2 100 D4 110 D6 001 D1 011 D3 101 D5 111 D7 Note This instruction can specify D8 D15 as operands by using a prefix 000 D0 010 D2 100 D4 110 D6 001 D1 011 D3 101 D5 111 D7 Note This instruction can specify D8 D15 as operands by using a prefix Register Memory Add...

Page 373: ...ister Rx Moves bits 31 1 into bits 30 0 Bit 31 remains the same creating a sign extension Register Address Bit Name Description SR 18 EXP Determines which stack pointer is used when the stack pointer is an operand Otherwise the instruction is not affected by SR Register Memory Address Before After R2 8002 0002 C001 0001 Instruction Words Cycles Type Opcode 15 8 7 0 ASRA Rx 1 1 2 1 1 1 0 R R R R 1 ...

Page 374: ... 0 then Dn Da 6 0 Dn else Dn Da 6 0 Dn ASRR Da Dn ASRR u5 Dn Performs an arithmetic right shift by N an immediate unsigned 5 bit integer The MSB is copied into the vacated positions ASRR Da Dn Performs a bidirectional arithmetic shift of Dn by Da 6 0 bits and stores the result in Dn If Da 6 0 is positive the shift is right If shifting right the MSB is copied into the vacated positions If shifting ...

Page 375: ...ss Before After D3 3 L5 D5 0 00 0000 7C09 0 00 0000 0F81 SR 00E4 0000 00E4 0000 EMR 0000 0000 Register Memory Address Before After D3 FF FDDD DDDC L5 D5 0 00 0000 7C09 0 00 0007 C090 SR 00E4 0000 00E4 0001 EMR 0000 0000 0 0 0 0 0 C 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 1 0 1 6 3 2 3 9 1 ...

Page 376: ...ords Cycles Type Opcode 15 8 7 0 ASRR u5 Dn 1 1 1 0 1 1 1 1 F F F 1 1 i i i i i 15 8 7 0 ASRR Da Dn 1 1 2 1 1 0 1 0 1 F F F 0 0 1 1 J J J 000 D0 010 D2 100 D4 110 D6 001 D1 011 D3 101 D5 111 D7 Note This instruction can specify D8 D15 as operands by using a prefix 000 D0 010 D2 100 D4 110 D6 001 D1 011 D3 101 D5 111 D7 Note This instruction can specify D8 D15 as operands by using a prefix u5 iiiii...

Page 377: ...ource register Da and stores the result in the destination register Dn It copies bit 39 of the source register to bits 39 24 of the destination register bit 15 of the source register to the C bit and bits 39 16 of the source register to bits 23 0 of the destination register Register Address Bit Name Description SR 0 C Da 15 is stored in the carry bit Ln L Clears the Ln bit in the destination regis...

Page 378: ...Data Register Instruction Words Cycles Type Opcode 15 8 7 0 ASRW Da Dn 1 1 2 1 1 0 1 1 0 F F F 0 0 1 1 J J J 000 D0 010 D2 100 D4 110 D6 001 D1 011 D3 101 D5 111 D7 Note This instruction can specify D8 D15 as operands by using a prefix 000 D0 010 D2 100 D4 110 D6 001 D1 011 D3 101 D5 111 D7 Note This instruction can specify D8 D15 as operands by using a prefix ...

Page 379: ...g sequentially The displacement calculated by the assembler and linker is a two s complement integer that represents the relative distance from the current PC to the destination label The assembler determines if the PC relative displacement is a short branch label 28 displacement 28 W or a long branch label 220 displacement 28 W and 28 displacement 220 W Register Address Bit Name Description SR 1 ...

Page 380: ...ycle If the branch is taken it uses 4 cycles Type Opcode 15 8 7 0 BF label 1 1 4 4 1 0 0 0 0 1 0 A A A A A A A A 1 15 8 7 0 BF label 2 1 4 4 0 0 1 0 a 1 1 1 A A A 1 1 a a a 1 0 0 A A A A A A A A A A A A a displacement label AAAAAAAA0 8 bit signed PC relative displacement displacement label aaaaaAAAAAAAAAAAAAA A0 20 bit signed PC relative displacement Register Memory Address Before After ...

Page 381: ...is a two s complement integer that represents the relative distance from the current PC to the destination label The assembler determines if the PC relative displacement is a short branch label 28 displacement 28 W or a long branch label 220 displacement 28 W and 28 displacement 220 W The execution set in the delay slot immediately following the BFD instruction is executed unconditionally after th...

Page 382: ...nus the time used by the execution set in the delay slot The cycle count for this instruction cannot be less than 1 cycle Type Opcode 15 8 7 0 BFD label 1 1 4 4 1 0 0 0 0 1 0 A A A A A A A A 0 15 8 7 0 BFD label 2 1 4 4 0 0 1 0 a 1 1 0 A A A 1 1 a a a 1 0 0 A A A A A A A A A A A A a displacement label AAAAAAAA0 8 bit signed PC relative displacement displacement label aaaaaAAAAAAAAAAAAAA A0 20 bit ...

Page 383: ...bits on the EMR register due to this register s special functionality See Chapter 3 for a description of this behavior Status and Conditions that Affect Instruction Operation Assembler Syntax C1 Hi C1 Hi i denotes bits 1 in u16 BMCHG u16 C1 H 0 u16 216 C1 Li C1 Li BMCHG u16 C1 L 0 u16 216 DR Hi DR Hi BMCHG u16 DR H 0 u16 216 DR Li DR Li BMCHG u16 DR L 0 u16 216 BMCHG u16 C1 H Inverts selected bits...

Page 384: ...5 8 7 0 BMCHG u16 C1 H 2 2 3 0 0 0 1 0 0 1 0 i i i 1 0 C C C 1 0 1 i i i i i i i i i i i i i 15 8 7 0 BMCHG u16 C1 L 2 2 3 0 0 0 1 0 0 1 0 i i i 0 0 C C C 1 0 1 i i i i i i i i i i i i i 15 8 7 0 BMCHG u16 DR H 2 2 3 0 0 0 0 1 0 1 0 i i i 1 H H H H 1 0 1 i i i i i i i i i i i i i 15 8 7 0 BMCHG u16 DR L 2 2 3 0 0 0 0 1 0 1 0 i i i 0 H H H H 1 0 1 i i i i i i i i i i i i i 000 EMR 010 100 110 001 V...

Page 385: ...BMCHG W SC140 DSP Core Reference Manual A 71 u16 iiiiiiiiiiiiiiii 16 bit unsigned immediate data ...

Page 386: ... u5 i SP u5 i i denotes bits 1 in u16 BMCHG W u16 SP u5 0 u16 216 0 u5 64 W SP s16 i SP s16 i BMCHG W u16 SP s16 0 u16 216 215 s16 215 W Rn i Rn i BMCHG W u16 Rn 0 u16 216 a16 i a16 i BMCHG W u16 a16 0 u16 216 0 a16 216 W BMCHG W u16 SP u5 Inverts selected bits in the contents of a memory address pointed to by the active stack pointer SP with an unsigned 5 bit offset BMCHG W u16 SP s16 Inverts sel...

Page 387: ... BMCHG W u16 SP s16 3 3 3 0 0 1 1 1 0 1 0 A A A i i 0 1 1 0 0 1 A A A A A A A A A A A A A 1 0 i i i i i i i i i i i i i i 15 8 7 0 BMCHG W u16 Rn 2 2 3 0 0 0 1 0 0 1 0 i i i 0 1 R R R 1 0 1 i i i i i i i i i i i i i 15 8 7 0 BMCHG W u16 a16 3 2 3 0 0 1 1 1 0 1 0 A A A i i 0 0 1 0 0 1 A A A A A A A A A A A A A 1 0 i i i i i i i i i i i i i i 000 R0 010 R2 100 R4 110 R6 001 R1 011 R3 101 R5 111 R7 N...

Page 388: ...A 74 SC140 DSP Core Reference Manual BMCHG W s16 AAAAAAAAAAAAAAAA 16 bit signed SP address offset ...

Page 389: ... clear bits on the EMR register due to this register s special functionality See Chapter 3 for a description of this behavior Status and Conditions that Affect Instruction Operation Assembler Syntax 0 C1 Hi i denotes bits 1 in u16 BMCLR u16 C1 H 0 u16 216 0 C1 Li BMCLR u16 C1 L 0 u16 216 0 DR Hi BMCLR u16 DR H 0 u16 216 0 DR Li BMCLR u16 DR L 0 u16 216 BMCLR u16 C1 H Clears selected bits in the HP...

Page 390: ... 0 BMCLR u16 C1 H 2 2 3 0 0 0 1 0 0 0 0 i i i 1 0 C C C 1 0 1 i i i i i i i i i i i i i 15 8 7 0 BMCLR u16 C1 L 2 2 3 0 0 0 1 0 0 0 0 i i i 0 0 C C C 1 0 1 i i i i i i i i i i i i i 15 8 7 0 BMCLR u16 DR H 2 2 3 0 0 0 0 1 0 0 0 i i i 1 H H H H 1 0 1 i i i i i i i i i i i i i 15 8 7 0 BMCLR u16 DR L 2 2 3 0 0 0 0 1 0 0 0 i i i 0 H H H H 1 0 1 i i i i i i i i i i i i i 000 EMR 010 100 110 001 VBA 01...

Page 391: ...BMCLR SC140 DSP Core Reference Manual A 77 u16 iiiiiiiiiiiiiiii 16 bit unsigned immediate data ...

Page 392: ...ler Syntax 0 SP u5 i i denotes bits 1 in u16 BMCLR W u16 SP u5 0 u16 216 0 u5 64 W 0 SP s16 i BMCLR W u16 SP s16 0 u16 216 215 s16 215 W 0 Rn i BMCLR W u16 Rn 0 u16 216 0 a16 i BMCLR W u16 a16 0 u16 216 0 a16 216 W BMCLR W u16 SP u5 Clears selected bits in the contents of a memory address pointed to by the active stack pointer SP with an unsigned 5 bit offset BMCLR W u16 SP s16 Clears selected bit...

Page 393: ... i i i i i 15 8 7 0 BMCLR W u16 Rn 2 2 3 0 0 0 1 0 0 0 0 i i i 0 1 R R R 1 0 1 i i i i i i i i i i i i i 15 8 7 0 BMCLR W u16 a16 3 2 3 0 0 1 1 1 0 0 0 A A A i i 0 0 1 0 0 1 A A A A A A A A A A A A A 1 0 i i i i i i i i i i i i i i 000 R0 010 R2 100 R4 110 R6 001 R1 011 R3 101 R5 111 R7 Note This instruction can specify R8 R15 as operands by using a high register prefix a16 AAAAAAAAAAAAAAAA 16 bit...

Page 394: ...d by Instruction Example Operation Assembler Syntax 1 C1 Hi i denotes bits 1 in u16 BMSET u16 C1 H 0 u16 216 1 C1 Li selected bits BMSET u16 C1 L 0 u16 216 1 DR Hi selected bits BMSET u16 DR H 0 u16 216 1 DR Li selected bits BMSET u16 DR L 0 u16 216 BMSET u16 C1 H Sets selected bits in the HP contents of a control register C1 BMSET u16 C1 L Sets selected bits in the LP contents of a control regist...

Page 395: ... u16 C1 L 2 2 3 0 0 0 1 0 0 0 1 i i i 0 0 C C C 1 0 1 i i i i i i i i i i i i i 15 8 7 0 BMSET u16 DR H 2 2 3 0 0 0 0 1 0 0 1 i i i 1 H H H H 1 0 1 i i i i i i i i i i i i i 15 8 7 0 BMSET u16 DR L 2 2 3 0 0 0 0 1 0 0 1 i i i 0 H H H H 1 0 1 i i i i i i i i i i i i i 000 EMR 010 100 110 001 VBA 011 101 SR 111 MCTL 0000 D0 0100 D4 1000 R0 1100 R4 0001 D1 0101 D5 1001 R1 1101 R5 0010 D2 0110 D6 1010...

Page 396: ...notes bits 1 in u16 BMSET W u16 SP u5 0 u16 216 0 u5 64 W 1 SP s16 i selected bits BMSET W u16 SP s16 0 u16 216 215 s16 215 W 1 Rn i selected bits BMSET W u16 Rn 0 u16 216 1 a16 i selected bits BMSET W u16 a16 0 u16 216 0 a16 216 W BMSET W u16 SP u5 Sets selected bits in the contents of a memory address pointed to by the active stack pointer SP with an unsigned 5 bit offset BMSET W u16 SP s16 Sets...

Page 397: ... A A A A A A A A A A A A 1 0 i i i i i i i i i i i i i i 15 8 7 0 BMSET W u16 Rn 2 2 3 0 0 0 1 0 0 0 1 i i i 0 1 R R R 1 0 1 i i i i i i i i i i i i i 15 8 7 0 BMSET W u16 a16 3 2 3 0 0 1 1 1 0 0 1 A A A i i 0 0 1 0 0 1 A A A A A A A A A A A A A 1 0 i i i i i i i i i i i i i i 000 R0 010 R2 100 R4 110 R6 001 R1 011 R3 101 R5 111 R7 Note This instruction can specify R8 R15 as operands by using a hi...

Page 398: ... register Status and Conditions that Affect Instruction None Status and Conditions Changed by Instruction Example 1 bmtset 111f d1 l Operation Assembler Syntax 1 DR Hi i denotes bits 1 in u16 if all selected bits were set then 1 T else 0 T BMTSET u16 DR H 0 u16 216 1 DR Li selected bits if all selected bits were set then 1 T else 0 T BMTSET u16 DR L 0 u16 216 BMTSET u16 DR H Tests and sets selecte...

Page 399: ...es Type Opcode 15 8 7 0 BMTSET u16 DR H 2 2 3 0 0 0 0 1 1 1 0 i i i 1 H H H H 1 0 1 i i i i i i i i i i i i i 15 8 7 0 BMTSET u16 DR L 2 2 3 0 0 0 0 1 1 1 0 i i i 0 H H H H 1 0 1 i i i i i i i i i i i i i 0000 D0 0100 D4 1000 R0 1100 R4 0001 D1 0101 D5 1001 R1 1101 R5 0010 D2 0110 D6 1010 R2 1110 R6 0011 D3 0111 D7 1011 R3 1111 R7 Note This instruction can specify D8 D15 or R8 R15 as operands by u...

Page 400: ...lures cause the T bit to be set The process attempting to set the semaphore should test the T bit after the instruction is executed in order to determine if the semaphore is set or not The absolute addresses offsets and address register values must be word aligned Although this instruction is designed with semaphores in mind it can be used for other applications Operation Assembler Syntax 1 SP u5 ...

Page 401: ...Bit Name Description SR 18 EXP Determines which stack pointer is used when the stack pointer is an operand Otherwise the instruction is not affected by SR Register Address Bit Name Description SR 1 T Set if all the bits selected by the mask are set or the memory access fails cleared otherwise Register Memory Address Before After immediate 4238 C 5678 5678 SR 00E4 0000 00E4 0002 ...

Page 402: ...i i i i i i 15 8 7 0 BMTSET W u16 Rn 2 2 3 0 0 0 1 0 1 1 0 i i i 0 1 R R R 1 0 1 i i i i i i i i i i i i i 15 8 7 0 BMTSET W u16 a16 3 2 3 0 0 1 1 1 1 1 0 A A A i i 0 0 1 0 0 1 A A A A A A A A A A A A A 1 0 i i i i i i i i i i i i i i 000 R0 010 R2 100 R4 110 R6 001 R1 011 R3 101 R5 111 R7 Note This instruction can specify R8 R15 as operands by using a high register prefix a16 AAAAAAAAAAAAAAAA 16 ...

Page 403: ...if u16 DR H 0000 then 1 T else 0 T BMTSTC u16 DR H 0 u16 216 if u16 DR L 0000 then 1 T else 0 T BMTSTC u16 DR L 0 u16 216 BMTSTC u16 C1 H Tests selected bits in the HP contents of a control register C1 BMTSTC u16 C1 L Tests selected bits in the LP contents of a control register C1 BMTSTC u16 DR H Tests selected bits in the HP contents of a data or address register DR BMTSTC u16 DR L Tests selected...

Page 404: ... C C 1 0 1 i i i i i i i i i i i i i 15 8 7 0 BMTSTC u16 DR H 2 2 3 0 0 0 0 1 1 0 0 i i i 1 H H H H 1 0 1 i i i i i i i i i i i i i 15 8 7 0 BMTSTC u16 DR L 2 2 3 0 0 0 0 1 1 0 0 i i i 0 H H H H 1 0 1 i i i i i i i i i i i i i 000 EMR 010 100 110 001 VBA 011 101 SR 111 MCTL 0000 D0 0100 D4 1000 R0 1100 R4 0001 D1 0101 D5 1001 R1 1101 R5 0010 D2 0110 D6 1010 R2 1110 R6 0011 D3 0111 D7 1011 R3 1111 ...

Page 405: ...6 SP s16 0000 then 1 T else 0 T BMTSTC W u16 SP s16 0 u16 216 215 s16 215 W if u16 Rn 0000 then 1 T else 0 T BMTSTC W u16 Rn 0 u16 216 if u16 a16 0000 then 1 T else 0 T BMTSTC W u16 a16 0 u16 216 0 a16 216 W BMTSTC W u16 SP u5 Tests selected bits in the contents of a memory address pointed to by the active stack pointer SP with an unsigned 5 bit offset BMTSTC W u16 SP s16 Tests selected bits in th...

Page 406: ...1001 Register Address Bit Name Description SR 18 EXP Determines which stack pointer is used when the stack pointer is an operand Otherwise the instruction is not affected by SR Register Address Bit Name Description SR 1 T Set if all the bits selected by the mask are clear cleared otherwise Register Memory Address Before After immediate 8A59 R0 0000 0002 0000 0002 0002 0000 24A6 0000 24A6 SR 00E4 0...

Page 407: ...i i i i i i 15 8 7 0 BMTSTC W u16 Rn 2 2 3 0 0 0 1 0 1 0 0 i i i 0 1 R R R 1 0 1 i i i i i i i i i i i i i 15 8 7 0 BMTSTC W u16 a16 3 2 3 0 0 1 1 1 1 0 0 A A A i i 0 0 1 0 0 1 A A A A A A A A A A A A A 1 0 i i i i i i i i i i i i i i 000 R0 010 R2 100 R4 110 R6 001 R1 011 R3 101 R5 111 R7 Note This instruction can specify R8 R15 as operands by using a high register prefix a16 AAAAAAAAAAAAAAAA 16 ...

Page 408: ...6 216 if u16 C1 L 0000 then 1 T else 0 T BMTSTS u16 C1 L 0 u16 216 if u16 DR H 0000 then 1 T else 0 T BMTSTS u16 DR H 0 u16 216 if u16 DR L 0000 then 1 T else 0 T BMTSTS u16 DR L 0 u16 216 BMTSTS u16 C1 H Tests selected bits in the HP contents of a control register C1 BMTSTS u16 C1 L Tests selected bits in the LP contents of a control register C1 BMTSTS u16 DR H Tests selected bits in the HP conte...

Page 409: ... 15 8 7 0 BMTSTS u16 C1 L 2 2 3 0 0 0 1 0 1 0 1 i i i 0 0 C C C 1 0 1 i i i i i i i i i i i i i 15 8 7 0 BMTSTS u16 DR H 2 2 3 0 0 0 0 1 1 0 1 i i i 1 H H H H 1 0 1 i i i i i i i i i i i i i 15 8 7 0 BMTSTS u16 DR L 2 2 3 0 0 0 0 1 1 0 1 i i i 0 H H H H 1 0 1 i i i i i i i i i i i i i 000 EMR 010 100 110 001 VBA 011 101 SR 111 MCTL 0000 D0 0100 D4 1000 R0 1100 R4 0001 D1 0101 D5 1001 R1 1101 R5 00...

Page 410: ...0000 then 1 T else 0 T BMTSTS W u16 SP s16 0 u16 216 215 s16 215 W if u16 Rn 0000 then 1 T else 0 T BMTSTS W u16 Rn 0 u16 216 if u16 a16 0000 then 1 T else 0 T BMTSTS W u16 a16 0 u16 216 0 a16 216 W BMTSTS W u16 SP u5 Tests selected bits in the contents of a memory address pointed to by the active stack pointer SP with an unsigned 5 bit offset BMTSTS W u16 SP s16 Tests selected bits in the content...

Page 411: ...EXP Determines which stack pointer is used when the stack pointer is an operand Otherwise the instruction is not affected by SR Register Address Bit Name Description SR 1 T Set if all the selected bits in the mask are set or the memory access fails cleared otherwise Register Memory Address Before After immediate 0428 r0 16FC 16FC sr 00E4 0000 00E4 0002 In binary 0428 0000010000101000 16FC 00010110...

Page 412: ...i i i i i i 15 8 7 0 BMTSTS W u16 Rn 2 2 3 0 0 0 1 0 1 0 1 i i i 0 1 R R R 1 0 1 i i i i i i i i i i i i i 15 8 7 0 BMTSTS W u16 a16 3 2 3 0 0 1 1 1 1 0 1 A A A i i 0 0 1 0 0 1 A A A A A A A A A A A A A 1 0 i i i i i i i i i i i i i i 000 R0 010 R2 100 R4 110 R6 001 R1 011 R3 101 R5 111 R7 Note This instruction can specify R8 R15 as operands by using a high register prefix a16 AAAAAAAAAAAAAAAA 16 ...

Page 413: ...abel BRA label BRA label Causes program execution to continue at location PC displacement The displacement calculated by the assembler and linker is a two s complement integer that represents the relative distance from the current PC to the destination label The assembler determines if the PC relative displacement is a short branch label 210 displacement 210 W or a long branch label 220 displaceme...

Page 414: ... _label displacement 0000 000A PC 0000 0002 0000 000A Instruction Words Cycles Type Opcode 15 8 7 0 BRA label 1 4 4 1 0 0 0 1 A A A A A A A A A A 1 15 8 7 0 BRA label 2 4 4 0 0 1 0 a 0 0 1 A A A 1 1 a a a 1 0 0 A A A A A A A A A A A A a displacement label AAAAAAAAAA0 10 bit signed PC relative displacement displacement label aaaaaAAAAAAAAAAAAAAA0 20 bit signed PC relative displacement ...

Page 415: ...the execution set containing the BRAD instruction called the delay slot The displacement calculated by the assembler and linker is a two s complement integer that represents the relative distance from the current PC to the destination label The assembler determines if the PC relative displacement is a short branch label 210 displacement 210 W or a long branch label 220 displacement 210 W and 210 d...

Page 416: ... 41 4 1 0 0 0 1 A A A A A A A A A A 0 15 8 7 0 BRAD label 2 41 Note 1 The branch uses 4 cycles minus the execution time used by execution set in the delay slot The cycle count for this instruction cannot be less than 1 cycle 4 0 0 1 0 a 0 0 0 A A A 1 1 a a a 1 0 0 A A A A A A A A A A A A a displacement label AAAAAAAAAA0 10 bit signed PC relative displacement displacement label aaaaaAAAAAAAAAAAAAAA...

Page 417: ...ive loop n unconditionally before the active loop counter LCn equals one and clears the active loop flag The program execution continues at label The displacement calculated by the assembler and linker is a two s complement integer that represents the relative distance from the current PC to the destination label Some programming rules apply to the use of this instruction If no loops are enabled t...

Page 418: ...n Fields Instruction Words Cycles Type Opcode 15 8 7 0 BREAK label 2 4 4 0 0 1 0 0 0 0 0 A A A 0 0 0 1 1 1 0 0 A A A A A A A A A A A A a displacement aAAAAAAAAAAAAAAA0 16 bit signed PC relative displacement The encoding is the displacement with bit 0 stripped and replaced by the sign bit ...

Page 419: ...a two s complement integer that represents the relative distance from the current PC to the destination label The assembler determines if the PC relative displacement is a short branch label 28 displacement 28 W or a long branch label 220 displacement 28 W and 28 displacement 220 W In addition to being pushed onto the stack the next PC is stored in the return address from subroutine register RAS a...

Page 420: ...Cycles Type Opcode 15 8 7 0 BSR label 1 4 4 1 0 0 0 0 0 1 A A A A A A A A 1 15 8 7 0 BSR label 2 4 4 0 0 1 0 a 0 1 1 A A A 1 1 a a a 1 0 0 A A A A A A A A A A A A a displacement label AAAAAAAA0 8 bit signed PC relative displacement displacement label aaaaaAAAAAAAAAAAAAA A0 20 bit signed PC relative displacement ...

Page 421: ...plement integer that represents the relative distance from the current PC to the destination label The assembler and linker determines if the PC relative displacement is a short branch label 28 displacement 28 W or a long branch label 220 displacement 28 W and 28 displacement 220 W In addition to being pushed onto the stack the next PC is stored in the RAS register and RAS becomes valid Register A...

Page 422: ...e execution set in the delay slot if the total of the largest cycle time of the instructions grouped with the BSRD and the execution time of the delay slot set is 4 One cycle is used by the core to push the return address onto the stack Type Opcode 15 8 7 0 BSRD label 1 4 5 4 1 0 0 0 0 0 1 A A A A A A A A 0 15 8 7 0 BSRD label 2 4 5 4 0 0 1 0 a 0 1 0 A A A 1 1 a a a 1 0 0 A A A A A A A A A A A A a...

Page 423: ...entially The displacement calculated by the assembler and linker is a two s complement integer that represents the relative distance from the current PC to the destination label The assembler determines if the PC relative displacement is a short branch label 28 displacement 28 W or a long branch label 220 displacement 28 W and 28 displacement 220 W Register Address Bit Name Description SR 1 T True...

Page 424: ...cle If the branch is taken it uses 4 cycles Type Opcode 15 8 7 0 BT label 1 1 4 4 1 0 0 0 0 0 0 A A A A A A A A 1 15 8 7 0 BT label 2 1 4 4 0 0 1 0 a 1 0 1 A A A 1 1 a a a 1 0 0 A A A A A A A A A A A A a displacement label AAAAAAAA0 8 bit signed PC relative displacement displacement label aaaaaAAAAAAAAAAAAAA A0 20 bit signed PC relative displacement Register Memory Address Before BT After ...

Page 425: ...s complement integer that represents the relative distance from the current PC to the destination label The assembler determines if the PC relative displacement is a short branch label 28 displacement 28 W or a long branch label 220 displacement 28 W and 28 displacement 220 W The execution set in the delay slot immediately following the BTD instruction is executed unconditionally after the executi...

Page 426: ...the time used by the execution set in the delay slot The cycle count for this instruction cannot be less than 1 cycle Type Opcode 15 8 7 0 BTD label 1 1 4 4 1 0 0 0 0 0 0 A A A A A A A A 0 15 8 7 0 BTD label 2 1 4 4 0 0 1 0 a 1 0 0 A A A 1 1 a a a 1 0 0 A A A A A A A A A A A A a displacement label AAAAAAAA0 8 bit signed PC relative displacement displacement label aaaaaAAAAAAAAAAAAAA A0 20 bit sign...

Page 427: ...LB Da Dn CLB Da Dn Counts the leading 0s or 1s according to bit 39 of source Da It scans bits 39 0 of Da starting from bit 39 The operation loads nine minus the number of consecutive leading 0s or 1s into destination Dn The result is sign extended The range of the result is 8 to 31 This instruction can be used in conjunction with the instruction ASRR for performing fast normalization of the operan...

Page 428: ... Data Register Instruction Words Cycles Type Opcode 15 8 7 0 CLB Da Dn 1 1 2 1 1 0 1 0 0 F F F 0 0 1 0 J J J 000 D0 010 D2 100 D4 110 D6 001 D1 011 D3 101 D5 111 D7 Note This instruction can specify D8 D15 as operands by using a prefix 000 D0 010 D2 100 D4 110 D6 001 D1 011 D3 101 D5 111 D7 Note This instruction can specify D8 D15 as operands by using a prefix ...

Page 429: ... the register being cleared and Da is an arbitrary register assigned by the assembler for programming rule G G 5 Any Da Da results in zero being stored in Dn Da assignment uses the low data registers D0 D7 where possible to avoid using a prefix Register Address Bit Name Description Ln L Clears the Ln bit in the destination register SR 0 C Clears the carry bit Register Memory Address Before After S...

Page 430: ...ta Register 000 D0 010 D2 100 D4 110 D6 001 D1 011 D3 101 D5 111 D7 Note This instruction can specify D8 D15 as operands by using a prefix 10000 D0 11100 D2 10100 D4 11110 D6 Note This instruction can specify D8 D15 as operands by using a prefix 00 D1 01 D3 10 D5 11 D7 Note If registers D8 D15 are accessed instead of D0 D7 a prefix is used ...

Page 431: ...hen 1 T else 0 T CMPEQ Da Dn CMPEQ Da Dn Compares the 40 bit contents of two data registers Da and Dn setting the T bit if they are equal and clearing the T bit if they are not Register Address Bit Name Description SR 1 T Sets T bit if equal otherwise cleared Register Memory Address Before After D2 00 0000 0005 D3 00 0000 0005 SR 00E4 0000 00E4 0002 Instruction Words Cycles Type Opcode 15 8 7 0 CM...

Page 432: ...140 DSP Core Reference Manual CMPEQ Dn FFF Single Source Destination Data Register 000 D0 010 D2 100 D4 110 D6 001 D1 011 D3 101 D5 111 D7 Note This instruction can specify D8 D15 as operands by using a prefix ...

Page 433: ...T CMPEQ W s16 Dn 215 s16 215 CMPEQ W u5 Dn Compares an immediate unsigned 5 bit value range 0 31 with a data register Dn for equality The immediate value is right aligned and zero extended CMPEQ W s16 Dn Compares an immediate signed 16 bit value that has been right aligned and sign extended to 40 bits with a data register Dn for equality Register Address Bit Name Description SR 1 T Sets T bit if e...

Page 434: ...pcode 15 8 7 0 CMPEQ W u5 Dn 1 1 2 1 1 0 1 0 0 F F F 0 1 i i i i i 15 8 7 0 CMPEQ W s16 Dn 2 1 4 0 0 1 1 0 1 0 0 i i i 1 0 F F F 1 0 0 i i i i i i i i i i i i i 000 D0 010 D2 100 D4 110 D6 001 D1 011 D3 101 D5 111 D7 Note This instruction can specify D8 D15 as operands by using a prefix u5 iiiii 5 bit unsigned immediate data s16 iiiiiiiiiiiiiiii 16 bit signed immediate data ...

Page 435: ...MPEQA rx Rx Compares two AGU registers rx and Rx for equality Note that a register cannot be compared to itself using this instruction Register Address Bit Name Description SR 18 EXP Determines which stack pointer is used when the stack pointer is an operand Otherwise the instruction is not affected by SR Register Address Bit Name Description SR 1 T Sets T bit if equal otherwise cleared Register M...

Page 436: ...0 R R R R 1 0 1 0 r r r r 0000 N0 0100 1000 R0 1100 R4 0001 N1 0101 1001 R1 1101 R5 0010 N2 0110 PC 1010 R2 1110 R6 0011 N3 0111 SP 1011 R3 1111 R7 Note This instruction can specify R8 R15 as operands by using a high register prefix 0000 N0 0100 1000 R0 1100 R4 0001 N1 0101 1001 R1 1101 R5 0010 N2 0110 1010 R2 1110 R6 0011 N3 0111 SP 1011 R3 1111 R7 Note This instruction can specify R8 R15 as oper...

Page 437: ...a Dn CMPGT Da Dn Compares two data registers Da and Dn The T bit is set if the signed value in the second data register Dn is greater than the signed value in the first Da T is cleared otherwise Register Address Bit Name Description SR 1 T Sets T bit if Dn Da otherwise cleared Register Memory Address Before After D2 0000 35FA D3 0000 35FB SR 00E4 0000 00E4 0002 Instruction Words Cycles Type Opcode...

Page 438: ...140 DSP Core Reference Manual CMPGT Dn FFF Single Source Destination Data Register 000 D0 010 D2 100 D4 110 D6 001 D1 011 D3 101 D5 111 D7 Note This instruction can specify D8 D15 as operands by using a prefix ...

Page 439: ...n Example cmpgt w 8002 d2 Operation Assembler Syntax Dn u5 T CMPGT W u5 Dn 0 u5 32 Dn s16 T CMPGT W s16 Dn 215 s16 215 CMPGT W u5 Dn Compares if a data register is greater than an immediate unsigned 5 bit value that has been right aligned and zero extended to 40 bits CMPGT W s16 Dn Compares if a data register is greater than an immediate signed 16 bit value that has been right aligned and sign ext...

Page 440: ...pcode 15 8 7 0 CMPGT W u5 Dn 1 1 2 1 1 0 1 0 1 F F F 0 1 i i i i i 15 8 7 0 CMPGT W s16 Dn 2 1 4 0 0 1 1 0 1 1 0 i i i 1 0 F F F 1 0 0 i i i i i i i i i i i i i 000 D0 010 D2 100 D4 110 D6 001 D1 011 D3 101 D5 111 D7 Note This instruction can specify D8 D15 as operands by using a prefix u5 iiiii 5 bit unsigned immediate data s16 iiiiiiiiiiiiiiii 16 bit signed immediate data ...

Page 441: ...e second AGU register is greater than the first or clears the T bit if the second AGU register is not greater than the first Note that a register cannot be compared to itself using this instruction Register Address Bit Name Description SR 18 EXP Determines which stack pointer is used when the stack pointer is an operand Otherwise the instruction is not affected by SR Register Address Bit Name Desc...

Page 442: ...0 R R R R 1 0 0 1 r r r r 0000 N0 0100 1000 R0 1100 R4 0001 N1 0101 1001 R1 1101 R5 0010 N2 0110 PC 1010 R2 1110 R6 0011 N3 0111 SP 1011 R3 1111 R7 Note This instruction can specify R8 R15 as operands by using a high register prefix 0000 N0 0100 1000 R0 1100 R4 0001 N1 0101 1001 R1 1101 R5 0010 N2 0110 1010 R2 1110 R6 0011 N3 0111 SP 1011 R3 1111 R7 Note This instruction can specify R8 R15 as oper...

Page 443: ... value in bits 31 0 of two data registers Da and Dn to determine which is greater It sets the T bit if the unsigned value of Dn 31 0 is greater than the unsigned value of Da 31 0 Otherwise it clears the T bit Register Address Bit Name Description SR 1 T Sets the T bit if 32 bit unsigned Dn Da otherwise cleared Register Memory Address Before After D1 00 26A2 44F3 D0 00 2781 21A2 SR 00E4 0000 00E4 0...

Page 444: ...140 DSP Core Reference Manual CMPHI Dn FFF Single Source Destination Data Register 000 D0 010 D2 100 D4 110 D6 001 D1 011 D3 101 D5 111 D7 Note This instruction can specify D8 D15 as operands by using a prefix ...

Page 445: ... the unsigned value of Rx is greater than the unsigned value of rx It clears the T bit if the unsigned value of Rx is not greater than the unsigned value of rx Note that a register cannot be compared to itself using this instruction Register Address Bit Name Description SR 18 EXP Determines which stack pointer is used when the stack pointer is an operand Otherwise the instruction is not affected b...

Page 446: ...0 R R R R 1 0 0 0 r r r r 0000 N0 0100 1000 R0 1100 R4 0001 N1 0101 1001 R1 1101 R5 0010 N2 0110 PC 1010 R2 1110 R6 0011 N3 0111 SP 1011 R3 1111 R7 Note This instruction can specify R8 R15 as operands by using a high register prefix 0000 N0 0100 1000 R0 1100 R4 0001 N1 0101 1001 R1 1101 R5 0010 N2 0110 1010 R2 1110 R6 0011 N3 0111 SP 1011 R3 1111 R7 Note This instruction can specify R8 R15 as oper...

Page 447: ...e loop SAn if its loop counter LCn is greater than one Otherwise it clears the active loop flag LFn and branches to an address determined by a 16 bit signed displacement 216 displacement 216 W added to the PC In either case the active loop counter is decremented by one Some programming rules apply to the use of this instruction If no loops are enabled this instruction is undefined Register Address...

Page 448: ...s1 Note 1 If LC 1 CONT uses 3 cycles If LC 1 CONT uses 4 cycles Type Opcode 15 8 7 0 CONT label 2 3 4 4 0 0 1 0 0 0 1 1 A A A 0 0 0 1 1 1 0 0 A A A A A A A A A A A A a displacement aAAAAAAAAAAAAAAA0 16 bit signed PC relative displacement The encoding is the displacement with bit 0 stripped and replaced by the sign bit ...

Page 449: ...active loop counter is decremented by one and the execution set immediately following the execution set containing the CONTD is executed Some programming rules apply to the use of this instruction If no loops are enabled this instruction is undefined Register Address Bit Name Description SR 30 27 LF 3 0 Read loop flags to determine active loop Register Address Bit Name Description SR 30 27 LF 3 0 ...

Page 450: ... both cases the cycles are decreased by the time used for the execution set in the delay slot The cycle count for this instruction cannot be less than 1 cycle Type Opcode 15 8 7 0 CONTD label 2 3 4 4 0 0 1 0 0 0 1 0 A A A 0 0 0 1 1 1 0 0 A A A A A A A A A A A A a displacement aAAAAAAAAAAAAAAA0 16 bit signed PC relative displacement The encoding is the displacement with bit 0 stripped and replaced ...

Page 451: ...ion None Example debug Instruction Formats and Opcodes Operation Assembler Syntax DEBUG DEBUG Causes the device to enter the debug state It is an Enhanced On chip Emulator EOnCE dedicated instruction that is used for debugging This instruction cannot be grouped with another debug instruction Instruction Words Cycles Type Opcode 15 8 7 0 DEBUG 1 2 4 1 0 0 1 1 1 1 0 0 1 1 1 0 0 0 0 ...

Page 452: ... enabled since reset issuing DEBUGEV has no effect If the EOnCE is enabled the effect of this instruction depends on the programming of EOnCE control registers Receipt of an EOnCE event can cause the core to enter the debug mode generate an exception or enable the trace buffer The delay from the DEBUGEV instruction to entering debug mode or generating an exception is not precise it could be a few ...

Page 453: ...tion of this instruction Note The assembler maps this instruction to SUBA u5 Rx where u5 1 Register Address Bit Name Description MCTL 31 0 AM3 AM0 Address modification bits when updating R0 R7 Otherwise the instruction is not affected by MCTL Register Memory Address Before After MCTL 0000 0000 R0 074F 312A 074F 3129 Instruction Words Cycles Type Opcode 15 8 7 0 DECA Rx 1 1 2 1 1 1 0 R R R R 0 1 1 ...

Page 454: ...A 140 SC140 DSP Core Reference Manual DECA u5 iiiii 5 bit unsigned immediate data 1 set by the assembler ...

Page 455: ...ECEQ Dn DECEQ Dn Decrements a data register Dn and sets the T bit if the result is equal to zero Register Address Bit Name Description SR 0 C Calculates and updates the carry bit in the status register SR 1 T Set if result 0 cleared otherwise EMR 2 DOVF Set if the result cannot be represented in 40 bits Ln L Clears the Ln bit in the destination register Register Memory Address Before After L7 D7 0...

Page 456: ...ore Reference Manual DECEQ Instruction Fields Dn FFF Single Source Destination Data Register 000 D0 010 D2 100 D4 110 D6 001 D1 011 D3 101 D5 111 D7 Note This instruction can specify D8 D15 as operands by using a prefix ...

Page 457: ...egister Rx and sets the T bit if the result is zero SP cannot be used as an operand of this instruction Register Address Bit Name Description SR 1 T Set if result 0 cleared otherwise Register Memory Address Before After R0 0000 0001 0000 0000 SR 00E4 0000 00E4 0002 Instruction Words Cycles Type Opcode 15 8 7 0 DECEQA Rx 1 1 2 1 1 1 0 R R R R 1 1 1 1 0 1 1 0 0000 N0 0100 1000 R0 1100 R4 0001 N1 010...

Page 458: ...is greater than or equal to zero In the case of an arithmetic overflow DECGE on the value 80 0000 0000 the T bit will not be set Register Address Bit Name Description SR 0 C Calculates and updates the carry bit in the status register SR 1 T Set if result 0 cleared otherwise EMR 2 DOVF Set if the result cannot be represented in 40 bits Ln L Clears the Ln bit in the destination register Instruction ...

Page 459: ...ore Reference Manual A 145 Instruction Fields Dn FFF Single Source Destination Data Register 000 D0 010 D2 100 D4 110 D6 001 D1 011 D3 101 D5 111 D7 Note This instruction can specify D8 D15 as operands by using a prefix ...

Page 460: ...ECGEA Rx Decrements an AGU register Rx and sets the T bit if the result is greater than or equal to zero In case there is an arithmetic overflow DECGEA on the value of 80000000 the T bit will not be set by this instruction SP cannot be used as an operand of this instruction Register Address Bit Name Description SR 1 T Set if result 0 cleared otherwise Register Memory Address Before After R4 0010 E...

Page 461: ... Instruction Words Cycles Type Opcode 15 8 7 0 DECGEA Rx 1 1 2 1 1 1 0 R R R R 1 1 1 1 0 1 1 1 0000 N0 0100 1000 R0 1100 R4 0001 N1 0101 1001 R1 1101 R5 0010 N2 0110 1010 R2 1110 R6 0011 N3 0111 SP 1011 R3 1111 R7 Note This instruction can specify R8 R15 as operands by using a high register prefix SP cannot be used by this instruction ...

Page 462: ...DI instruction and its counterpart the EI instruction can be used to delimit a code segment that needs to be protected from interruption For example a non interruptible read modify write sequence of execution sets could be written like this DI read modify EI write Where read modify and write stand for instruction s If using this instruction no allowance is necessary for a pipeline delay of updatin...

Page 463: ...DI SC140 DSP Core Reference Manual A 149 15 8 7 0 DI 1 1 4 1 0 0 1 1 1 1 1 0 1 1 1 1 1 0 1 ...

Page 464: ...hen Dn Da and the operands are interpreted as fractions This condition ensures that the magnitude of the quotient is less than one i e is fractional and precludes division by zero The DIV instruction calculates one quotient bit based on the divisor and the previous partial remainder To produce an N bit quotient the DIV instruction is executed N times where N is the number of bits of precision desi...

Page 465: ...applicable and a user defined N bit division routine is required For further information on division algorithms refer to pages 524 530 of Theory and Application of Digital Signal Processing by Rabiner and Gold Prentice Hall 1975 pages 190 199 of Computer Architecture and Organization by John Hayes McGraw Hill 1978 pages 213 223 of Computer Arithmetic Principles Architecture and Design by Kai Hwang...

Page 466: ... Da JJJ Single Source Data Register Instruction Words Cycles Type Opcode 15 8 7 0 DIV Da Dn 1 1 1 0 1 1 0 0 F F F 1 0 1 0 J J J 000 D0 010 D2 100 D4 110 D6 001 D1 011 D3 101 D5 111 D7 Note This instruction can specify D8 D15 as operands by using a prefix 000 D0 010 D2 100 D4 110 D6 001 D1 011 D3 101 D5 111 D7 Note This instruction can specify D8 D15 as operands by using a prefix ...

Page 467: ... right with bit 39 sign extended into bits 39 24 Adds the result to the product of signed fractions in Dc H and Dd H Places the result into Dn Dc and Dd are a data register pair The operands are in the HP of each register This instruction is optimized for multi precision multiplication support Register Address Bit Name Description Ln L Clears the Ln bit in the destination register Register Memory ...

Page 468: ... Single Source Destination Data Register Instruction Words Cycles Type Opcode 15 8 7 0 DMACSS Dc Dd Dn 1 1 1 0 1 0 1 1 F F F 1 1 1 0 1 e e 00 D0 D1 01 D2 D3 10 D4 D5 11 D6 D7 Note This instruction can specify D8 D15 as operands by using a prefix 000 D0 010 D2 100 D4 110 D6 001 D1 011 D3 101 D5 111 D7 Note This instruction can specify D8 D15 as operands by using a prefix ...

Page 469: ... bits to the right with bit 39 sign extended into bits 39 24 Adds the result to the product of a signed fraction in Dc H and an unsigned fraction in Dd L Places the result into Dn Dc and Dd are a data register pair The operands are in the HP and LP of each register respectively This instruction is optimized for multi precision multiplication support Register Address Bit Name Description Ln L Clear...

Page 470: ... Pairs Dn FFF Single Source Destination Data Register 00 D0 D1 01 D2 D3 10 D4 D5 11 D6 D7 Note This instruction can specify D8 D15 as operands by using a prefix 000 D0 010 D2 100 D4 110 D6 001 D1 011 D3 101 D5 111 D7 Note This instruction can specify D8 D15 as operands by using a prefix ...

Page 471: ...distance between this instruction and the loop body or other loop instructions Status and Conditions that Affect Instruction None Status and Conditions Changed by Instruction Example doen2 d0 Operation Assembler Syntax u6 LCn 1 LFn DOENn u6 0 u6 64 u16 LCn 1 LFn DOENn u16 0 u16 216 DR LCn 1 LFn DOENn DR DOENn u6 Moves an unsigned 6 bit immediate value into the loop counter LCn and enables the chos...

Page 472: ...0 0 0 n n i i i 0 0 1 0 0 1 0 0 i i i i i i i i i i i i i 15 8 7 0 DOENn DR 1 1 4 1 0 0 1 1 0 n n 0 1 0 0 H H H H 00 Loop 0 01 Loop 1 10 Loop 2 11 Loop 3 0000 D0 0100 D4 1000 R0 1100 R4 0001 D1 0101 D5 1001 R1 1101 R5 0010 D2 0110 D6 1010 R2 1110 R6 0011 D3 0111 D7 1011 R3 1111 R7 Note This instruction can specify D8 D15 or R8 R15 as operands by using a high register prefix u6 iiiiii 6 bit unsigne...

Page 473: ...oop body or other loop instructions Status and Conditions that Affect Instruction None Status and Conditions Changed by Instruction Example doensh2 d0 Operation Assembler Syntax u6 LCn 1 LFn 1 SLF DOENSHn u6 0 u6 64 u16 LCn 1 LFn 1 SLF DOENSHn u16 0 u16 216 DR LCn 1 LFn 1 SLF DOENSHn DR DOENSHn u6 Moves an unsigned 6 bit immediate value into the loop counter LCn and enables the chosen loop flag an...

Page 474: ... n n i i i 0 0 1 0 0 1 0 0 i i i i i i i i i i i i i 15 8 7 0 DOENSHn DR 1 1 4 1 0 0 1 1 1 n n 0 1 0 0 H H H H 00 Loop 0 01 Loop 1 10 Loop 2 11 Loop 3 0000 D0 0100 D4 1000 R0 1100 R4 0001 D1 0101 D5 1001 R1 1101 R5 0010 D2 0110 D6 1010 R2 1110 R6 0011 D3 0111 D7 1011 R3 1111 R7 Note This instruction can specify D8 D15 or R8 R15 as operands by using a high register prefix u6 iiiiii 6 bit unsigned i...

Page 475: ...e placed outside the enveloping loop as long as SA Start Address is not changed by instructions in the loop DOSETUPn loads a loop start address register SAn The label is placed at the beginning of the loop The encoded value in the DOSETUP instruction is a PC relative displacement calculated by the assembler and linker from the label The start address placed in SAn is the absolute address of the la...

Page 476: ...struction Words Cycles Type Opcode 15 8 7 0 DOSETUPn label 2 1 4 0 0 1 0 1 0 n n A A A 0 0 0 1 1 1 0 0 A A A A A A A A A A A A a 00 Loop 0 01 Loop 1 10 Loop 2 11 Loop 3 displacement aAAAAAAAAAAAAAAA0 16 bit signed PC relative displacement The encoding is the displacement with bit 0 stripped and replaced by the sign bit ...

Page 477: ...modify write sequence of execution sets can be written like this DI read modify EI write Where read modify and write represent instruction s This instruction can appear only once in an execution set The effect of EI may not be immediate That is a pending interrupt may not be serviced as the first execution set immediately after this instruction because of pipeline effects Register Address Bit Name...

Page 478: ...A 164 SC140 DSP Core Reference Manual EI ...

Page 479: ...e eor d4 d5 B 1011 3 0011 8 1000 Operation Assembler Syntax Da Dn Dn EOR Da Dn EOR Da Dn Performs a bitwise exclusive OR between two data registers Da and Dn and stores the result in a destination data register Dn Register Address Bit Name Description Ln L Clears the Ln bit in the destination register Register Memory Address Before After D4 FF FFFF FFFB L5 D5 0 00 0000 0003 0 FF FFFF FFF8 ...

Page 480: ... Data Register Instruction Words Cycles Type Opcode 15 8 7 0 EOR Da Dn 1 1 2 1 1 0 1 1 1 F F F 0 0 1 0 J J J 000 D0 010 D2 100 D4 110 D6 001 D1 011 D3 101 D5 111 D7 Note This instruction can specify D8 D15 as operands by using a prefix 000 D0 010 D2 100 D4 110 D6 001 D1 011 D3 101 D5 111 D7 Note This instruction can specify D8 D15 as operands by using a prefix ...

Page 481: ...gister or data register DR Stores the result in the destination register DR This instruction is assembler mapped to BMCHG u16 DR L with the immediate value The HP of the register is unaffected EOR u16 DR H Performs a bitwise exclusive OR between a 16 bit unsigned immediate value and the HP of an address register or data register DR Stores the result in the destination register DR This instruction ...

Page 482: ...i 0 H H H H 1 0 1 i i i i i i i i i i i i i 15 8 7 0 EOR u16 DR H 2 2 3 0 0 0 0 1 0 1 0 i i i 1 H H H H 1 0 1 i i i i i i i i i i i i i 0000 D0 0100 D4 1000 R0 1100 R4 0001 D1 0101 D5 1001 R1 1101 R5 0010 D2 0110 D6 1010 R2 1110 R6 0011 D3 0111 D7 1011 R3 1111 R7 Note This instruction can specify D8 D15 or R8 R15 as operands by using a high register prefix u16 iiiiiiiiiiiiiiii 16 bit unsigned imme...

Page 483: ... the immediate value EOR W u16 SP u5 Performs a bitwise exclusive OR between an immediate unsigned word and the contents of a memory address Stores the result in the same memory address The memory address is calculated as the active stack pointer SP minus a 5 bit unsigned offset value This instruction is assembler mapped to BMCHG W u16 SP u5 with the immediate value EOR W u16 SP s16 Performs a bit...

Page 484: ... i i i i i i i i i i i 15 8 7 0 EOR W u16 SP s16 3 3 3 0 0 1 1 1 0 1 0 A A A i i 0 1 1 0 0 1 A A A A A A A A A A A A A 1 0 i i i i i i i i i i i i i i 15 8 7 0 EOR W u16 a16 3 2 3 0 0 1 1 1 0 1 0 A A A i i 0 0 1 0 0 1 A A A A A A A A A A A A A 1 0 i i i i i i i i i i i i i i 000 R0 010 R2 100 R4 110 R6 001 R1 011 R3 101 R5 111 R7 Note This instruction can specify R8 R15 as operands by using a high...

Page 485: ...by Instruction Example extract c e d2 d4 Operation Assembler Syntax Db offset width 1 offset Dn width 1 0 Db offset width 1 Dn 39 width sign extension width U6 offset u6 EXTRACT U6 u6 Db Dn 0 U6 40 0 u6 40 U6 u6 40 width Da 13 8 offset Da 5 0 EXTRACT Da Db Dn 0 Da 13 8 40 0 Da 5 0 40 Da 13 8 Da 5 0 40 EXTRACT U6 u6 Db Dn Uses two immediate unsigned 6 bit integers for the width U6 and offset u6 EXT...

Page 486: ...J J J 000 D0 010 D2 100 D4 110 D6 001 D1 011 D3 101 D5 111 D7 Note This instruction can specify D8 D15 as operands by using a prefix 000 D0 010 D2 100 D4 110 D6 001 D1 011 D3 101 D5 111 D7 Note This instruction can specify D8 D15 as operands by using a prefix 000 D0 010 D2 100 D4 110 D6 001 D1 011 D3 101 D5 111 D7 Note This instruction can specify D8 D15 as operands by using a prefix u16 iiiiii Un...

Page 487: ... by Instruction Example extractu c e d2 d4 Operation Assembler Syntax Db offset width 1 offset Dn width 1 0 0 Dn 39 width width U6 offset u6 EXTRACTU U6 u6 Db Dn 0 U6 40 0 u6 40 U6 u6 40 width Da 13 8 offset Da 5 0 EXTRACTU Da Db Dn 0 Da 13 8 40 0 Da 5 0 40 Da 13 8 Da 5 0 40 EXTRACTU U6 u6 Db Dn Uses two immediate unsigned 6 bit integers for the width U6 and offset u6 EXTRACTU Da Db Dn Uses a supp...

Page 488: ...0 J J J 000 D0 010 D2 100 D4 110 D6 001 D1 011 D3 101 D5 111 D7 Note This instruction can specify D8 D15 as operands by using a prefix 000 D0 010 D2 100 D4 110 D6 001 D1 011 D3 101 D5 111 D7 Note This instruction can specify D8 D15 as operands by using a prefix 000 D0 010 D2 100 D4 110 D6 001 D1 011 D3 101 D5 111 D7 Note This instruction can specify D8 D15 as operands by using a prefix u16 iiiiii ...

Page 489: ... not affected by the arithmetic saturation mode The carry bit is not affected by this instruction This instruction is an integer non saturating version of ADDNC W Register Address Bit Name Description EMR 2 DOVF Set if the result cannot be represented in 40 bits Ln L Clears the L bit in the destination register Register Memory Address Before After L2 D2 1 FFFFFFCA3E 0 FFFFFF6A40 EMR 00000000 Instr...

Page 490: ...ondition is false If T is equal to one condition is true the group or subgroup is treated as a NOP This instruction can be used in conjunction with IFT to form an if else clause IFT Execute the group or subgroup if T is equal to one condition is true If T is equal to zero condition is false the group or subgroup is treated as a NOP This instruction can be used in conjunction with IFF to form an if...

Page 491: ...numbers relate to the relative offset of the instruction from the beginning of the set as encoded For example a full execution set might be D0 D1 D2 D3 A0 A1 000 Unconditionally executed 001 If true D0 D2 A0 if false D1 D3 A1 010 If true all the set 011 If false all the set 100 Reserved 101 Reserved 110 If true D0 D2 A0 always D1 D3 A1 111 If false D0 D2 A0 always D1 D3 A1 Register Address Bit Nam...

Page 492: ...sers should not rely on any timing between the ILLEGAL instruction execution and the start of exception processing In the most common case the exception vector is executed after four more execution sets are executed following the illegal instruction In other cases it can be the set immediately after or delayed by another execution set Thus it should be realized that in the exception routine the ma...

Page 493: ...k pointer SR 23 21 I 2 0 Set interrupt priority level to 111 EMR 0 ILIN Sets illegal instruction bit SR 0 C Cleared SR 1 T Cleared SR 5 4 S 1 0 Cleared SR 31 SLF Cleared SR 30 27 LF 3 0 Clear loop flags Register Memory Address Before After SR 18E0 0003 00E4 0000 EMR 0000 0000 0000 0001 Instruction Words Cycles1 Note 1 Cycle count is dependant on the machine state Typically five cycles is the servi...

Page 494: ...er multiplication on the LP contents of two source data registers Da and Db and adds or subtracts the product to or from a destination data register Dn The default operation is the addition of the product to the destination register Register Address Bit Name Description Ln L Clears the Ln bit in the destination register EMR 2 DOVF Set if the result cannot be represented in 40 bits Register Memory ...

Page 495: ...s Note indicates serial grouping encoding Instruction Fields k Accumulation Notation Register Memory Address Before After D4 00 1022 002A D5 FF FF3A 000B L6 D6 0 00 0000 1000 0 00 0000 0E32 EMR 0000 0000 0000 0000 Instruction Words Cycles Type Opcode 15 8 7 0 IMAC Da Db Dn 1 1 1 0 1 0 1 0 F F F k 0 J J J J J 15 8 7 0 IMAC Da Da Dn 1 1 1 0 1 0 1 0 F F F 1 1 0 k 1 j j 0 add 1 subtract ...

Page 496: ... 00110 D1 D6 01110 D3 D6 10110 D4 D6 11110 D6 D6 00111 D1 D7 01111 D3 D7 10111 D4 D7 11111 D6 D7 Notes 1 This instruction can specify D8 D15 as operands by using a prefix 2 Register pair order can be inverted for clarity because the order of operation is not important for multiply operations 3 The JJJJJ encoding does not include the pairs D1 D1 D3 D3 D5 D5 and D7 D7 These are covered in the jj enc...

Page 497: ...ACLHUU Da Db Dn Performs an unsigned integer multiplication of the 16 bit LP of one source data register Da with the 16 bit HP of another source data register Db It then adds the zero extended 32 bit product to a destination data register Dn This instruction is optimized for multi precision multiplication support Register Address Bit Name Description Ln L Clears the Ln bit in the destination regis...

Page 498: ... 0 IMACLHUU Da Db Dn 2 1 4 0 0 1 1 1 0 0 0 j j j 0 0 F F F 1 0 0 0 0 0 0 0 0 0 0 0 0 J J J 000 D0 010 D2 100 D4 110 D6 001 D1 011 D3 101 D5 111 D7 Note This instruction can specify D8 D15 as operands by using a prefix 000 D0 010 D2 100 D4 110 D6 001 D1 011 D3 101 D5 111 D7 Note This instruction can specify D8 D15 as operands by using a prefix 000 D0 010 D2 100 D4 110 D6 001 D1 011 D3 101 D5 111 D7...

Page 499: ...plication of the unsigned 16 bit LP of one source data register Da with the signed 16 bit HP of another source data register Db It then adds the sign extended 32 bit product to a destination data register Dn This instruction is optimized for multi precision multiplication support Register Address Bit Name Description Ln L Clears the Ln bit in the destination register EMR 2 DOVF Set if the result c...

Page 500: ...es Type Opcode 15 8 7 0 IMACUS Da Db Dn 2 1 4 0 0 1 1 0 0 0 0 j j j 0 0 F F F 1 0 0 0 0 0 0 0 0 0 0 0 0 J J J 000 D0 010 D2 100 D4 110 D6 001 D1 011 D3 101 D5 111 D7 Note This instruction can specify D8 D15 as operands by using a prefix 000 D0 010 D2 100 D4 110 D6 001 D1 011 D3 101 D5 111 D7 Note This instruction can specify D8 D15 as operands by using a prefix 000 D0 010 D2 100 D4 110 D6 001 D1 0...

Page 501: ...Da L Db L Dn IMPY Da Db Dn IMPY Da Db Dn Performs a signed integer multiplication on the low portions of two signed source data registers Da Db and stores the product in a destination data register Dn Register Address Bit Name Description Ln L Clears the Ln bit in the destination register Register Memory Address Before After D3 FF FFFF 0202 D4 00 0000 FFFE L0 D0 0 FF FFFF FBFC Instruction Words Cy...

Page 502: ...10011 D0 D3 11011 D5 D7 00100 D1 D4 01100 D3 D4 10100 D4 D4 11100 D2 D2 00101 D1 D5 01101 D3 D5 10101 D4 D5 11101 D2 D3 00110 D1 D6 01110 D3 D6 10110 D4 D6 11110 D6 D6 00111 D1 D7 01111 D3 D7 10111 D4 D7 11111 D6 D7 Notes 1 This instruction can specify D8 D15 as operands by using a prefix 2 Register pair order can be inverted for clarity because the order of operation is not important for multiply...

Page 503: ...peration Assembler Syntax s16 Dn L Dn IMPY W s16 Dn 215 s16 215 IMPY W s16 Dn Performs a signed integer multiplication on the low portion of a source data register Dn and an immediate signed 16 bit word It then stores the result in a destination data register Dn Register Address Bit Name Description Ln L Clears the Ln bit in the destination register Register Memory Address Before After immediate F...

Page 504: ...urce Destination Data Register Instruction Words Cycles Type Opcode 15 8 7 0 IMPY W s16 Dn 2 1 4 0 0 1 1 1 1 1 0 i i i 1 0 F F F 1 0 0 i i i i i i i i i i i i i 000 D0 010 D2 100 D4 110 D6 001 D1 011 D3 101 D5 111 D7 Note This instruction can specify D8 D15 as operands by using a prefix s16 iiiiiiiiiiiiiiii 16 bit signed immediate data ...

Page 505: ...PYHLUU Da Db Dn IMPYHLUU Da Db Dn Performs an unsigned integer multiplication on the 16 bit HP of one source data register Da and the 16 bit LP of another source data register Db It then stores the zero extended 32 bit result in a destination data register Dn Register Address Bit Name Description Ln L Clears the Ln bit in the destination register Register Memory Address Before After D3 00 0002 FFF...

Page 506: ... 0 IMPYHLUU Da Db Dn 2 1 4 0 0 1 1 1 0 1 0 j j j 0 0 F F F 1 0 0 0 0 0 0 0 0 0 0 0 0 J J J 000 D0 010 D2 100 D4 110 D6 001 D1 011 D3 101 D5 111 D7 Note This instruction can specify D8 D15 as operands by using a prefix 000 D0 010 D2 100 D4 110 D6 001 D1 011 D3 101 D5 111 D7 Note This instruction can specify D8 D15 as operands by using a prefix 000 D0 010 D2 100 D4 110 D6 001 D1 011 D3 101 D5 111 D7...

Page 507: ...a H Db L Dn IMPYSU Da Db Dn IMPYSU Da Db Dn Performs a signed integer multiplication on the signed 16 bit HP of one source data register Da and the unsigned 16 bit LP of a second source data register Db It then stores the sign extended 32 bit result in a destination data register Dn Register Address Bit Name Description Ln L Clears the Ln bit in the destination register Register Memory Address Bef...

Page 508: ... 0 IMPYSU Da Db Dn 2 1 4 0 0 1 1 0 1 0 0 j j j 0 0 F F F 1 0 0 0 0 0 0 0 0 0 0 0 0 J J J 000 D0 010 D2 100 D4 110 D6 001 D1 011 D3 101 D5 111 D7 Note This instruction can specify D8 D15 as operands by using a prefix 000 D0 010 D2 100 D4 110 D6 001 D1 011 D3 101 D5 111 D7 Note This instruction can specify D8 D15 as operands by using a prefix 000 D0 010 D2 100 D4 110 D6 001 D1 011 D3 101 D5 111 D7 N...

Page 509: ...igned integer multiplication on the 16 bit LP Da of one data register and the16 bit LP of another data register Db It then stores the zero extended 32 bit result in a data register Dn Register Address Bit Name Description Ln L Clears the Ln bit in the destination register Register Memory Address Before After D5 00 0000 0002 D3 FF FFFF FFFC L1 D1 0 00 0001 FFF8 Instruction Words Cycles Type Opcode ...

Page 510: ...ngle Source Destination Data Register 000 D0 010 D2 100 D4 110 D6 001 D1 011 D3 101 D5 111 D7 Note This instruction can specify D8 D15 as operands by using a prefix 000 D0 010 D2 100 D4 110 D6 001 D1 011 D3 101 D5 111 D7 Note This instruction can specify D8 D15 as operands by using a prefix ...

Page 511: ...de SR 5 4 S 1 0 Scaling mode bits determine which bits in the result are used in the Ln bit calculation Register Address Bit Name Description SR 0 C Calculates and updates the carry bit in the status register EMR 2 DOVF Set if the result cannot be represented in 40 bits or if the result saturates to 32 bits in arithmetic saturation mode Ln L If not in arithmetic saturation mode SR SM 0 calculates ...

Page 512: ...oding Instruction Fields Dn FFF Single Source Destination Data Register Register Memory Address Before After SR 00E0 0004 00E0 0004 L15 D15 0 00 7FFF FFFF 0 00 7FFF FFFF EMR 0000 0004 Instruction Words Cycles Type Opcode 15 8 7 0 INC Dn 1 1 1 0 1 1 1 0 F F F 1 0 0 0 0 0 1 000 D0 010 D2 100 D4 110 D6 001 D1 011 D3 101 D5 111 D7 Note This instruction can specify D8 D15 as operands by using a prefix ...

Page 513: ...tion mode SR 5 4 S 1 0 Scaling mode bits determine which bits in the result are used in the Ln bit calculation Register Address Bit Name Description SR 0 C Calculates and updates the carry bit in the status register EMR 2 DOVF Set if the result cannot be represented in 40 bits or if the result saturates to 32 bits in arithmetic saturation mode Ln L If not in arithmetic saturation mode SR SM 0 calc...

Page 514: ...rouping encoding Instruction Fields Dn FFF Single Source Destination Data Register Instruction Words Cycles Type Opcode 15 8 7 0 INC F Dn 1 1 1 0 1 0 0 1 F F F 1 1 0 0 1 1 1 000 D0 010 D2 100 D4 110 D6 001 D1 011 D3 101 D5 111 D7 Note This instruction can specify D8 D15 as operands by using a prefix ...

Page 515: ...x Adds one to an AGU register Rx The stack pointer SP cannot be used as an operand by this instruction Note The assembler maps this instruction to ADDA u5 Rx where u5 1 Register Address Bit Name Description MCTL 31 0 AM3 AM0 Address modification bits when updating R0 R7 Otherwise the instruction is not affected by MCTL Register Memory Address Before After MCTL 0000 0000 R0 074F 312A 074F 312B Regi...

Page 516: ... Words Cycles Type Opcode 15 8 7 0 INCA Rx 1 1 2 1 1 1 0 R R R R 0 1 0 i i i i i 0000 N0 0100 1000 R0 1100 R4 0001 N1 0101 1001 R1 1101 R5 0010 N2 0110 1010 R2 1110 R6 0011 N3 0111 SP 1011 R3 1111 R7 Note This instruction can specify R8 R15 as operands by using a high register prefix u5 iiiii 5 bit unsigned immediate data 1 set by the assembler ...

Page 517: ...th U6 offset u6 INSERT U6 u6 Db Dn 0 U6 40 0 u6 40 U6 u6 40 width Da 13 8 offset Da 5 0 INSERT Da Db Dn 0 Da 5 0 40 0 Da 13 8 16 Da 13 8 Da 5 0 40 INSERT U6 u6 Db Dn Uses two immediate unsigned 6 bit integers for the width U6 and offset u6 INSERT Da Db Dn Uses a supplemental data register Da for the width bits 13 8 and the offset bits 5 0 Register Address Bit Name Description Ln L Clears the Ln bi...

Page 518: ...i i i i i 15 8 7 0 INSERT Da Db Dn 2 1 4 0 0 1 1 j j j 0 1 0 1 0 1 F F F 1 0 0 0 0 0 0 0 0 0 0 0 0 J J J 000 D0 010 D2 100 D4 110 D6 001 D1 011 D3 101 D5 111 D7 Note This instruction can specify D8 D15 as operands by using a prefix 000 D0 010 D2 100 D4 110 D6 001 D1 011 D3 101 D5 111 D7 Note This instruction can specify D8 D15 as operands by using a prefix 000 D0 010 D2 100 D4 110 D6 001 D1 011 D3...

Page 519: ... Assembler Syntax If T 0 then label PC JF label 0 label 232 W If T 0 then Rn PC JF Rn JF label Jumps to the absolute memory address specified by a label The assembler and linker calculate an absolute address from the label JF Rn Jumps to the memory address specified in an address register Rn The value of Rn must be word aligned Register Address Bit Name Description SR 1 T True bit Instruction Resu...

Page 520: ...e branch is taken it uses 4 cycles Type Opcode 15 8 7 0 JF label 3 1 4 3 0 0 1 1 0 1 1 1 A A A a a 1 0 0 0 0 1 A A A A A A A A A A A A A 1 0 a a a a a a a a a a a a a a 15 8 7 0 JF Rn 1 1 4 4 1 0 0 1 1 R R R 0 1 1 0 0 1 1 1 000 R0 010 R2 100 R4 110 R6 001 R1 011 R3 101 R5 111 R7 Note This instruction can specify R8 R15 as operands by using a high register prefix label aaaaaaaaaaaaaaaaAAAAAAAAAAAAA...

Page 521: ...f T 0 then label PC JFD label 0 label 232 W If T 0 then Rn PC JFD Rn JFD label Jumps to the absolute memory address specified by a label after executing the set in the delay slot The assembler and linker calculate the destination address from the label JFD Rn Jumps to the memory address specified in an address register Rn after executing the execution set in the delay slot Register Address Bit Nam...

Page 522: ...t uses 4 cycles minus the time used by the execution set in the delay slot The cycle count for this instruction cannot be less than 1 cycle Type Opcode 15 8 7 0 JFD label 3 1 4 3 0 0 1 1 0 1 1 0 A A A a a 1 0 0 0 0 1 A A A A A A A A A A A A A 1 0 a a a a a a a a a a a a a a 15 8 7 0 JFD Rn 1 1 4 4 1 0 0 1 1 R R R 0 1 1 0 0 1 1 0 000 R0 010 R2 100 R4 110 R6 001 R1 011 R3 101 R5 111 R7 Note This ins...

Page 523: ...ne Status and Conditions Changed by Instruction None Example jmp _label Operation Assembler Syntax label PC JMP label 0 label 232 W Rn PC JMP Rn JMP label Jumps to an absolute memory address specified by a label The assembler and the linker calculate the destination address from the label JMP Rn Jumps to a memory address specified by an address register Rn The value in Rn must be word aligned Regi...

Page 524: ... 0 0 1 A A A a a 1 0 0 0 0 1 A A A A A A A A A A A A A 1 0 a a a a a a a a a a a a a a 15 8 7 0 JMP Rn 1 3 4 1 0 0 1 1 R R R 0 1 1 0 0 0 0 1 000 R0 010 R2 100 R4 110 R6 001 R1 011 R3 101 R5 111 R7 Note This instruction can specify R8 R15 as operands by using a high register prefix label aaaaaaaaaaaaaaaaAAAAAAAAAAAAAAAA 32 bit absolute long address Note Label must be word aligned LSBit 0 ...

Page 525: ...ion set in the delay slot The assembler and the linker calculate the destination address from the label The destination address cannot be in the middle of an execution set JMPD Rn Jumps to a memory address specified by an address register Rn after executing the execution set in the delay slot The value in Rn must be word aligned Instruction Comment move w 35 d0 Places 35 in d0 jmpd lbl move w 29 d...

Page 526: ...lot The cycle count for this instruction cannot be less than 1 cycle 3 0 0 1 1 0 0 0 0 A A A a a 1 0 0 0 0 1 A A A A A A A A A A A A A 1 0 a a a a a a a a a a a a a a 15 8 7 0 JMPD Rn 1 31 4 1 0 0 1 1 R R R 0 1 1 0 0 0 0 0 label aaaaaaaaaaaaaaaaAAAAAAAAAAAAAAAAA 32 bit absolute long address Note Label must be word aligned LSBit 0 000 R0 010 R2 100 R4 110 R6 001 R1 011 R3 101 R5 111 R7 Note This in...

Page 527: ... execution set Status and Conditions that Affect Instruction Status and Conditions Changed by Instruction None Example jsr r6 Operation Assembler Syntax Next PC SP SR SP 4 SP 8 SP label PC JSR label 0 label 232 W Next PC SP SR SP 4 SP 8 SP Rn PC JSR Rn JSR label Jumps to a memory location specified by the label The assembler and linker calculate the 32 bit absolute destination address from the lab...

Page 528: ...A A A 1 0 a a a a a a a a a a a a a a 15 8 7 0 JSR Rn 1 3 41 Note 1 The cycle time is 4 if the largest execution time of the other instructions grouped with JSR is 3 4 1 0 0 1 1 R R R 0 1 1 0 0 0 1 1 label aaaaaaaaaaaaaaaaAAAAAAAAAAAAAAAA absolute long address Note Label must be word aligned LSBit 0 000 R0 010 R2 100 R4 110 R6 001 R1 011 R3 101 R5 111 R7 Note This instruction can specify R8 R15 as...

Page 529: ... None Example jsrd r6 Operation Assembler Syntax Next PC SP SR SP 4 SP 8 SP Next PC RAS label PC JSRD label 0 label 232 W Next PC SP SR SP 4 SP 8 SP Next PC RAS Rn PC JSRD Rn JSRD label Jumps to a memory location specified by an immediate 32 bit absolute address JSRD Rn Jumps to a memory location contained in an address register Rn The value in Rn must be word aligned Register Address Bit Name Des...

Page 530: ...les if the largest cycle time of the instructions grouped with JSRD is 3 or greater The cycle count of two or three is reduced by the execution time used by the execution set in the delay slot The cycle count for this instruction cannot be less than one cycle 4 1 0 0 1 1 R R R 0 1 1 0 0 0 1 0 label aaaaaaaaaaaaaaaaAAAAAAAAAAAAAAAA absolute long address Note Label must be word aligned LSBit 0 000 R...

Page 531: ...and Conditions that Affect Instruction Status and Conditions Changed by Instruction None Example jt r0 Operation Assembler Syntax If T 1 then label PC JT label 0 label 232 W If T 1 then Rn PC JT Rn JT label Jumps to the memory location specified by the label The assembler and linker calculate the 32 bit absolute address from the label JT Rn Jumps to the memory location contained in an address regi...

Page 532: ...taken the jump uses 4 cycles 3 0 0 1 1 0 1 0 1 A A A a a 1 0 0 0 0 1 A A A A A A A A A A A A A 1 0 a a a a a a a a a a a a a a 15 8 7 0 JT Rn 1 1 41 4 1 0 0 1 1 R R R 0 1 1 0 0 1 0 1 label aaaaaaaaaaaaaaaaAAAAAAAAAAAAAAAA absolute long address Note Label must be word aligned LSBit 0 000 R0 010 R2 100 R4 110 R6 001 R1 011 R3 101 R5 111 R7 Note This instruction can specify R8 R15 as operands by usin...

Page 533: ...le jtd r0 Operation Assembler Syntax If T 1 then label PC JTD label 0 label 232 W If T 1 then Rn PC JTD Rn JTD label Jumps to the memory location specified by the label The assembler and linker calculate the 32 bit absolute address from the label JTD Rn Jumps to the memory location contained in an address register Rn The value in Rn must be word aligned Register Address Bit Name Description SR 1 T...

Page 534: ... execution set in the delay slot The cycle count for this instruction cannot be less than 1 cycle 3 0 0 1 1 0 1 0 0 A A A a a 1 0 0 0 0 1 A A A A A A A A A A A A A 1 0 a a a a a a a a a a a a a a 15 8 7 0 JTD Rn 1 1 41 4 1 0 0 1 1 R R R 0 1 1 0 0 1 0 0 label aaaaaaaaaaaaaaaaAAAAAAAAAAAAAAAA absolute long address Note Label must be word aligned LSBit 0 000 R0 010 R2 100 R4 110 R6 001 R1 011 R3 101 ...

Page 535: ...its in SR The LPMARK bits are encoded in the prefix words and are not independent instructions They are generated automatically by the assembler at the correct positions based on the LOOPSTART and LOOPEND assembly directives inserted by the programmer The assembler does not allow the programmer to use LPMARKx Operation Disassembler Syntax Only If LCn 1 then SAn PC LCn 1 LCn else next PC PC 0 LCn 0...

Page 536: ...Conditions that Affect LPMARK Execution The loop flag LFn short loop flag SLFn and loop counters LCn affect the response as described in the description above Table A 17 Combinations of LPMARKx Use LPMARKA LPMARKB LFn SLF LCn Description no LPMARKB set clear 1 LCn decrements by one and a jump with two delay slots to SAn occurs LPMARKs appearing in the delay slots are ignored 1 LCn and LFn are clea...

Page 537: ...ts the number two into d2 move w 3 d3 move w 3 d3 Puts the number three into d3 move w 4 d4 move w 4 d4 Puts the number four into d4 loopstart0 An assembler directive that defines the start of the loop _lab inc d1 inc d1 Increments d1 each pass through the loop inc d2 lpmarkb inc d2 lpmarkb bit placed in the prefix by the assembler Incre ments d2 each pass through the loop inc d3 inc d3 Increments...

Page 538: ...If N is positive Dn is shifted left Bit 40 N is stored in the C bit Bits 39 N 0 are copied to bits 39 N Bits N 1 0 are cleared If N is negative Dn is shifted right Bit N 1 of Dn is stored in the C bit Bits 39 N are copied to bits 39 N 0 Bits 39 40 N are cleared Register Address Bit Name Description SR 0 C Bit 40 N of Dn is stored in the C bit for a left shift Or bit N 1 of Dn is stored in the C bi...

Page 539: ...F F 0 0 0 0 J J J 000 D0 010 D2 100 D4 110 D6 001 D1 011 D3 101 D5 111 D7 Note This instruction can specify D8 D15 as operands by using a prefix 000 D0 010 D2 100 D4 110 D6 001 D1 011 D3 101 D5 111 D7 Note This instruction can specify D8 D15 as operands by using a prefix 1 1 1 1 1 C 1 1 1 1 1 0 0 0 0 1 1 1 0 1 1 0 0 1 0 1 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 0 1 1 0 0 1 0 1 ...

Page 540: ...s the contents of a data register Dn right one bit The LSB bit 0 is shifted into the carry C bit in the status register Bits 39 1 are copied to bits 38 0 Bit 39 is cleared Register Address Bit Name Description SR 0 C Dn 0 is stored in the C bit Ln L Clears the Ln bit in the destination register Register Memory Address Before After SR 00E4 0000 00E4 0001 L4 D4 0 FF CCCC CCCD 0 7F E666 6666 Instruct...

Page 541: ...er Rx right one bit Bits 31 1 are copied to bits 30 0 Bit 31 is cleared Register Address Bit Name Description SR 18 EXP Determines which stack pointer is used when the stack pointer is an operand Otherwise the instruction is not affected by SR Register Memory Address Before After R2 AAAA AAAA 5555 5555 Instruction Words Cycles Type Opcode 15 8 7 0 LSRA Rx 1 1 2 1 1 1 0 R R R R 1 1 1 1 1 1 1 1 0000...

Page 542: ...ntained in Da bits 6 0 If N is positive Dn is shifted right Bit N 1 is stored in the C bit Bits 39 N are copied to bits 39 N 0 Bits 39 40 N are cleared If N is negative Dn is shifted left Bit 40 N is stored in the C bit Bits 39 N 0 are copied to bits 39 N Bits N 1 0 are cleared LSRR u5 Dn Shifts the contents of a 40 bit data register Dn right the number of bits designated in u5 u5 is an unsigned 5...

Page 543: ...ress Before After D4 FF FFFF FFFE SR 00E4 0000 00E4 0001 L2 D2 0 FF 8765 4321 0 FE 1D95 0C84 Register Memory Address Before After D4 00 0000 0002 SR 00E4 0000 00E4 0000 L2 D2 0 FF 8765 4321 0 3F 1ED9 50C8 1 1 1 1 1 C 1 1 1 1 1 0 0 0 0 1 1 1 0 1 1 0 0 1 0 1 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 0 1 1 0 0 1 0 1 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 0 0 1 6 3 2 3 9 0 C 0 0 1 1 1 1 1...

Page 544: ...de 15 8 7 0 LSRR Da Dn 1 1 2 1 1 0 1 0 1 F F F 0 0 0 1 J J J 15 8 7 0 LSRR u5 Dn 1 1 2 1 1 0 1 1 1 F F F 0 1 i i i i i 000 D0 010 D2 100 D4 110 D6 001 D1 011 D3 101 D5 111 D7 Note This instruction can specify D8 D15 as operands by using a prefix 000 D0 010 D2 100 D4 110 D6 001 D1 011 D3 101 D5 111 D7 Note This instruction can specify D8 D15 as operands by using a prefix u5 iiiii 5 bit unsigned imm...

Page 545: ...tion data register Dn logically shifted right 16 bits Bit 15 of the source register is copied to the C bit Bits 39 16 of the source register are copied to bits 23 0 of the destination register Bits 39 24 of the destination register are cleared Register Address Bit Name Description SR 0 C Dn 15 is copied into the C bit Ln L Clears the Ln bit in the destination register Register Memory Address Befor...

Page 546: ... F F F 0 0 0 1 J J J 000 D0 010 D2 100 D4 110 D6 001 D1 011 D3 101 D5 111 D7 Note This instruction can specify D8 D15 as operands by using a prefix 000 D0 010 D2 100 D4 110 D6 001 D1 011 D3 101 D5 111 D7 Note This instruction can specify D8 D15 as operands by using a prefix 0 C 0 0 0 0 0 1 6 3 2 3 9 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 0 1 1 0 0 1 0 1 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1...

Page 547: ...data register Da to the destination register Dn MAC Da Db Dn Multiplies the HP contents of two data registers Da Db and adds or subtracts the product to or from a destination data register Dn The default is to add the product to the destination register Register Address Bit Name Description SR 2 SM If set selects 32 bit arithmetic saturation mode SR 5 4 S 1 0 Scaling mode bits determine which bits...

Page 548: ...0 L6 D6 0 00 4000 0000 0 00 4600 0000 EMR 0000 0000 Register Memory Address Before After SR 00E0 0000 D5 00 3000 261F L6 D6 0 00 4000 0000 0 00 4600 0000 EMR 0000 0000 Instruction Words Cycles Type Opcode 15 8 7 0 MAC s16 Da Dn 2 1 4 0 0 1 1 J J J 1 i i i 1 0 F F F 1 0 0 i i i i i i i i i i i i i 15 8 7 0 MAC Da Db Dn 1 1 1 0 1 0 0 0 F F F k 0 J J J J J 15 8 7 0 MAC Da Da Dn 1 1 1 0 1 0 1 0 F F F ...

Page 549: ...2 D2 00101 D1 D5 01101 D3 D5 10101 D4 D5 11101 D2 D3 00110 D1 D6 01110 D3 D6 10110 D4 D6 11110 D6 D6 00111 D1 D7 01111 D3 D7 10111 D4 D7 11111 D6 D7 Notes 1 This instruction can specify D8 D15 as operands by using a prefix 2 Register pair order can be inverted for clarity because the order of operation is not important for add and multiply operations 3 The JJJJJ encoding does not include the pairs...

Page 550: ...er and then zeros the low part The two modes of the round function Rnd are described on page A 359 Register Address Bit Name Description SR 2 SM If set selects 32 bit arithmetic saturation mode SR 3 RM Rounding mode SR 5 4 S 1 0 The scaling mode bits determine which bits in the result are used in the Ln bit calculation and which bits are used in rounding Register Address Bit Name Description Ln L ...

Page 551: ...d 1 subtract 00000 D0 D4 01000 D2 D4 10000 D0 D0 11000 D1 D2 00001 D0 D5 01001 D2 D5 10001 D0 D1 11001 D1 D3 00010 D0 D6 01010 D2 D6 10010 D0 D2 11010 D5 D6 00011 D0 D7 01011 D2 D7 10011 D0 D3 11011 D5 D7 00100 D1 D4 01100 D3 D4 10100 D4 D4 11100 D2 D2 00101 D1 D5 01101 D3 D5 10101 D4 D5 11101 D2 D3 00110 D1 D6 01110 D3 D6 10110 D4 D6 11110 D6 D6 00111 D1 D7 01111 D3 D7 10111 D4 D7 11111 D6 D7 Not...

Page 552: ...FFF Single Source Destination Data Register 00 D1 D1 01 D3 D3 10 D5 D5 11 D7 D7 Note This instruction can specify D8 D15 as operands by using a prefix 000 D0 010 D2 100 D4 110 D6 001 D1 011 D3 101 D5 111 D7 Note This instruction can specify D8 D15 as operands by using a prefix ...

Page 553: ...orms signed fractional multiplication of the signed 16 bit HP of one data register Dc in a register pair Dc and Dd by the unsigned 16 bit LP of the other data register Dd It then adds the sign extended 32 bit product to a destination data register Dn Register Address Bit Name Description Ln L Clears the Ln bit in the destination register EMR 2 DOVF Set if the result cannot be represented in 40 bit...

Page 554: ...elds Dc Dd ee Data Register Pairs Dn FFF Single Source Destination Data Register Instruction Words Cycles Type Opcode 15 8 7 0 MACSU Dc Dd Dn 1 1 1 0 1 0 0 0 F F F 1 1 1 0 0 e e 00 D0 D1 01 D2 D3 10 D4 D5 11 D6 D7 Note This instruction can specify D8 D15 as operands by using a prefix 000 D0 010 D2 100 D4 110 D6 001 D1 011 D3 101 D5 111 D7 Note This instruction can specify D8 D15 as operands by usi...

Page 555: ...ration Assembler Syntax Dn Dc L Dd H Dn MACUS Dc Dd Dn MACUS Dc Dd Dn Performs signed fractional multiplication of the unsigned 16 bit LP of one data register Dc in a register pair by the signed 16 bit HP of the other data register Dd It then adds the sign extended 32 bit product to a data register Dn Register Address Bit Name Description Ln L Clears the Ln bit in the destination register EMR 2 DO...

Page 556: ... Single Source Destination Data Register Instruction Words Cycles Type Opcode 15 8 7 0 MACUS Dc Dd Dn 1 1 1 0 1 0 1 1 F F F 1 1 0 0 0 e e 00 D0 D1 01 D2 D3 10 D4 D5 11 D6 D7 Note This instruction can specify D8 D15 as operands by using a prefix 000 D0 010 D2 100 D4 110 D6 001 D1 011 D3 101 D5 111 D7 Note This instruction can specify D8 D15 as operands by using a prefix ...

Page 557: ... 111 1111 1111 1100 0000 0000 0000 0001 02 7FFC 0001 Operation Assembler Syntax Dn Dc L Dd L Dn MACUU Dc Dd Dn MACUU Dc Dd Dn Performs unsigned fractional multiplication of the unsigned 16 bit LP of one data register Dc by the unsigned 16 bit LP of the other data register Dd It then adds the zero extended 32 bit product to a data register Dn Register Address Bit Name Description Ln L Clears the Ln...

Page 558: ... Single Source Destination Data Register Instruction Words Cycles Type Opcode 15 8 7 0 MACUU Dc Dd Dn 1 1 1 0 1 0 1 1 F F F 1 1 0 0 1 e e 00 D0 D1 01 D2 D3 10 D4 D5 11 D6 D7 Note This instruction can specify D8 D15 as operands by using a prefix 000 D0 010 D2 100 D4 110 D6 001 D1 011 D3 101 D5 111 D7 Note This instruction can specify D8 D15 as operands by using a prefix ...

Page 559: ...n Formats and Opcodes Operation Assembler Syntax PC trace buffer MARK MARK Writes PC the address of the MARK instruction to the trace buffer if the trace buffer is enabled TMARK bit in the TB_CTRL register is set It is an EOnCE dedicated instruction used for debugging This instruction can appear only once in an execution set Instruction Words Cycles Type Opcode 15 8 7 0 MARK 1 1 4 1 0 0 1 1 1 1 0 ...

Page 560: ...er pair Dg and Dh to the second of the two registers Dh If the first register is greater than the second the value of the first register is written to the second Otherwise the second register is unchanged Only certain pairs of registers are allowed see Instruction Fields below Register Address Bit Name Description Ln L Clears the Ln bit in the destination register Register Memory Address Before Af...

Page 561: ...s 16 bit signed values and written or not written based on the comparison If the high portion of the first register is greater than the high portion of the second the value of the high portion of the first register is written to the high portion of the second Otherwise the high portion of the second register is unchanged The same process is applied to the low portions of the two registers with the...

Page 562: ...A 248 SC140 DSP Core Reference Manual MAX2 Instruction Fields Dg Dh GG Data Register Pairs 00 D0 D4 01 D1 D5 10 D2 D6 11 D3 D7 Note This instruction can specify D8 D15 as operands by using a prefix ...

Page 563: ...th the VSL instruction see page A 423 Status and Conditions that Affect Instruction None Operation Assembler Syntax If Da L Db L then 0 VFn Da L Db L else 1 VFn MAX2VIT Da Db Da Db VFn D4 L D2 L VF0 D4 H D2 H VF1 D0 L D6 L VF2 D0 H D6 H VF3 D12 L D10 L VF0 D12 H D10 H VF1 D8 L D14 L VF2 D8 H D14 H VF3 MAX2VIT Da Db For the low portion comparison the instruction clears VFn n 0 2 if the LP of Da is ...

Page 564: ...VIT D4 D2 and MAX2VIT D12 D10 SR 9 VF1 Updated by MAX2VIT D4 D2 and MAX2VIT D12 D10 SR 10 VF2 Updated by MAX2VIT D0 D6 and MAX2VIT D8 D14 SR 11 VF3 Updated by MAX2VIT D0 D6 and MAX2VIT D8 D14 Ln L Clears the Ln bit in the destination register Register Memory Address Before After D4 00 0643 1023 D2 00 0564 1F22 00 0643 1F22 SR 00E4 0000 00E4 0100 Instruction Words Cycles Type Opcode 15 8 7 0 MAX2VI...

Page 565: ... a data register pair Dg and Dh If the absolute value of the first register Dg is greater than the absolute value of the second Dh the value of the first register is written to the second Dh Otherwise the second register is unchanged In case Dg and Dh have equal magnitudes but opposite signs the destination register Dh is written with the positive value Register Address Bit Name Description Ln L C...

Page 566: ...A 252 SC140 DSP Core Reference Manual MAXM Instruction Fields Dg Dh GG Data Register Pairs 00 D0 D4 01 D1 D5 10 D2 D6 11 D3 D7 Note This instruction can specify D8 D15 as operands by using a prefix ...

Page 567: ...r of two signed values in a data register pair Dg and Dh to the second of the two registers Dh If the first register is less than the second the value of the first register is written to the second Otherwise the second register is unchanged Register Address Bit Name Description Ln L Clears the Ln bit in the destination register Register Memory Address Before After D1 00 36AE 3FB4 L5 D5 0 00 48FE 4...

Page 568: ...MOVES 2F The first operand Da will be moved from the lower memory address EA The second operand Db will be moved from memory address EA 2 In order to maintain this behavior in both big endian and little endian modes the core will interpret the data bus differently in each mode See Section 2 4 1 SC140 Endian Support on page 2 56 for more detail on bus and memory behavior for each mode The address r...

Page 569: ...D3 0 00 2000 0000 Instruction Words Cycles Type Opcode 15 8 7 0 MOVE 2F EA Da Db 1 12 1 0 0 1 1 h h 1 0 1 M M M R R R 00 D0 D1 01 D2 D3 10 D4 D5 11 D6 D7 Note This instruction can specify D8 D15 as operands by using a prefix In such a case all the registers in the group will be high registers 000 Rn N0 010 Rn 100 Rn N0 110 Rn N2 001 Rn 011 Rn 101 Rn N1 111 Rn N3 000 R0 010 R2 100 R4 110 R6 001 R1 ...

Page 570: ...EA The first operand Da will be moved to or from the lower memory address EA The second operand Db will be moved to or from memory address EA 4 In order to keep this behavior in both big endian and little endian modes the core will drive or interpret the data bus differently in each mode See Section 2 4 1 SC140 Endian Support on page 2 56 for more detail on bus and memory behavior for each mode Th...

Page 571: ...te 1 When the form Rn N0 is used in EA the cycle count is increased by 1 2 1 1 0 0 0 h h w 0 0 M M M R R R MOVE 2L EA Da Db 0 write 1 read 00 D0 D1 01 D2 D3 10 D4 D5 11 D6 D7 Note This instruction can specify D8 D15 as operands by using a prefix In such a case all the registers in the group will be high registers 000 Rn N0 010 Rn 100 Rn N0 110 Rn N2 001 Rn 011 Rn 101 Rn N1 111 Rn N3 000 R0 010 R2 ...

Page 572: ...a will be moved to or from the lower memory address EA and the second operand Db will be moved to or from memory address EA 2 In order to keep this behavior in both big endian and little endian modes the core will drive or sample the data bus differently in each mode See Section 2 4 1 SC140 Endian Support on page 2 56 for more detail on bus and memory behavior for each mode The address register va...

Page 573: ...AF44 0052 2377 Instruction Words Cycles Type Opcode 15 8 7 0 MOVE 2W EA Da Db 1 12 1 0 0 w 1 h h 0 0 1 M M M R R R MOVE 2W Da Db EA 0 write 1 read 00 D0 D1 01 D2 D3 10 D4 D5 11 D6 D7 Note This instruction can specify D8 D15 as operands by using a prefix In such a case all the registers in the group will be high registers 000 Rn N0 010 Rn 100 Rn N0 110 Rn N2 001 Rn 011 Rn 101 Rn N1 111 Rn N3 000 R0...

Page 574: ... the lower memory address EA The second operand Db will be moved from memory address EA 2 The third operand Dc will be moved from memory address EA 4 And the fourth operand Dd will be moved from memory address EA 6 In order to keep this behavior in both big endian and little endian modes the core will interpret the data bus differently in each mode See Section 2 4 1 SC140 Endian Support on page 2 ...

Page 575: ... 0102 5AB1 0104 33E4 0106 A7AC L0 D0 0 FF 943C 0000 L1 D1 0 00 5AB1 0000 L2 D2 0 00 33E4 0000 L3 D3 0 FF A7AC 0000 Instruction Words Cycles Type Opcode 15 8 7 0 MOVE 4F EA Da Db Dc Dd 1 12 1 0 0 0 1 k 0 1 1 1 M M M R R R 0 D0 D1 D2 D3 1 D4 D5 D6 D7 Note This instruction can specify D8 D15 as operands by using a prefix In such a case all the registers in the group will be high registers 000 Rn N0 0...

Page 576: ...EA The second operand Db will be moved to or from memory address EA 2 The third operand Dc will be moved to or from memory address EA 4 And the fourth operand Dd will be moved to or from memory address EA 6 In order to keep this behavior in both big endian and little endian modes the core will drive or interpret the data bus differently in each mode See Section 2 4 1 SC140 Endian Support on page 2...

Page 577: ...0 0056 4151 Instruction Words Cycles Type Opcode 15 8 7 0 MOVE 4W EA Da Db Dc Dd 1 11 Note 1 When the form Rn N0 is used in EA the cycle count is increased by 1 2 1 1 0 0 1 k 0 w 0 0 M M M R R R MOVE 4W Da Db Dc Dd EA 0 write 1 read 0 D0 D1 D2 D3 1 D4 D5 D6 D7 Note This instruction can specify D8 D15 as operands by using a prefix In such a case all the registers in the group will be high registers...

Page 578: ... SP s15 214 s15 214 MOVE B a16 DR Reads a byte from a 16 bit absolute memory address sign extending it into a register MOVE B DR a16 Writes a byte to a 16 bit absolute memory address MOVE B DR a32 Writes a byte to a 32 bit absolute memory address MOVE B DR Rn s15 Writes a byte to memory from a register The effective memory address is obtained from an address register with a signed 15 bit offset MO...

Page 579: ...tive stack pointer SP with a signed 15 bit offset MOVE B DR SP s15 Writes a byte to memory The address is obtained from the stack pointer with a signed 15 bit offset Register Address Bit Name Description MCTL 31 0 AM3 AM0 Address modification bits when updating R0 R7 Otherwise the instruction is not affected by MCTL SR 18 EXP Determines which stack pointer is used when the stack pointer is an oper...

Page 580: ...DR Rn s15 2 2 3 0 0 0 0 H H H H 0 s s 1 0 R R R 1 0 0 s s s s s s s s s s s s s 15 8 7 0 MOVE B ea DR 1 11 Note 1 When the form Rn N0 is used in ea the cycle count is increased by 1 4 1 0 0 1 H H H H 1 1 1 M M R R R 15 8 7 0 MOVE B DR ea 1 11 4 1 0 0 1 H H H H 1 0 0 M M R R R 15 8 7 0 MOVE B SP s15 DR 2 2 3 0 0 0 1 H H H H 0 s s 1 1 1 1 0 1 0 0 s s s s s s s s s s s s s 15 8 7 0 MOVE B DR SP s15 2...

Page 581: ...2 100 R4 110 R6 001 R1 011 R3 101 R5 111 R7 Note This instruction can specify R8 R15 as operands by using a high register prefix 00 Rn 01 Rn 10 Rn N0 11 Rn a16 AAAAAAAAAAAAAAAA 16 bit unsigned absolute address a32 aaaaaaaaaaaaaaaaAAAAAAAAAAAAAAAA 32 bit absolute long address s15 sssssssssssssss Signed 15 bit offset ...

Page 582: ... a32 Db 0 a32 232 W EA Db MOVE F EA Db 0 EA 232 W Rn s15 Db MOVE F Rn s15 Db 214 s15 214 W SP s15 Db MOVE F SP s15 Db 214 s15 214 W Db ea MOVE F Db ea 0 ea 232 W MOVE F s16 Db Loads a 16 bit immediate fractional value into a data register MOVE F a16 Db Reads a fractional word from a 16 bit unsigned absolute address into a data register MOVE F a32 Db Reads a fractional word from a 32 bit absolute a...

Page 583: ...uction available for moving the HP of a data register to memory without saturation The effective memory address is obtained from an address register with an optional offset or post increment Register Address Bit Name Description MCTL 31 0 AM3 AM0 Address modification bits when updating R0 R7 Otherwise the instruction is not affected by MCTL SR 18 EXP Determines which stack pointer is used when the...

Page 584: ... 0 1 1 0 1 1 0 0 A A A A A A A A A A A A A 15 8 7 0 MOVE F a32 Db 3 1 3 0 0 0 0 1 j j j A A A a a 0 1 1 0 0 1 A A A A A A A A A A A A A 1 0 a a a a a a a a a a a a a a 15 8 7 0 MOVE F EA Db 1 12 1 0 0 1 0 j j j 0 1 M M M R R R 15 8 7 0 MOVE F Rn s15 Db 2 2 3 0 0 0 0 1 j j j 1 s s 1 0 R R R 1 0 0 s s s s s s s s s s s s s 15 8 7 0 MOVE F SP s15 Db 2 2 3 0 0 0 0 0 j j j 1 s s 1 1 1 0 0 1 0 0 s s s s...

Page 585: ... R2 100 R4 110 R6 001 R1 011 R3 101 R5 111 R7 Note This instruction can specify R8 R15 as operands by using a high register prefix s16 iiiiiiiiiiiiiiii 16 bit signed immediate data a16 AAAAAAAAAAAAAAAA 16 bit unsigned absolute address a32 aaaaaaaaaaaaaaaaAAAAAAAAAAAAAAAA 32 bit absolute long address s15 sssssssssssssss Signed 15 bit offset ...

Page 586: ...2 C1 0 u32 232 C4 Db MOVE L C4 Db MOVE L Db C4 C2 Db MOVE L C2 Db MOVE L Db C2 MOVE L s32 C4 Loads an immediate signed long word into a general register MOVE L u32 C1 Loads an immediate unsigned long word into a control register MOVE L C4 Db MOVE L Db C4 Moves a long word between a selected data register and a selected general register MOVE L C2 Db MOVE L Db C2 Moves a long word between a selected...

Page 587: ... w j j j MOVE L Db C2 000 EMR 010 100 110 001 VBA 011 101 SR 111 MCTL 0000 EMR 0100 1000 SA0 1100 SA2 0001 VBA 0101 SR 1001 LC0 1101 LC2 0010 0110 1010 SA1 1110 SA3 0011 0111 MCTL 1011 LC1 1111 LC3 00000 D0 01000 D4 10000 R0 11000 R4 00001 B0 01001 B4 10001 N0 11001 M0 00010 D1 01010 D5 10010 R1 11010 R5 00011 B1 01011 B5 10011 N1 11011 M1 00100 D2 01100 D6 10100 R2 11100 R6 00101 B2 01101 B6 1010...

Page 588: ...e Reference Manual MOVE L w Read Write Notation 0 write 1 read s32 31 IIIIIIIIIIIIIIII 16 15 iiiiiiiiiiiiiiii 0 32 bit signed immediate data u32 31 IIIIIIIIIIIIIIII 16 15 iiiiiiiiiiiiiiii 0 32 bit unsigned immediate data ...

Page 589: ...ister An extension saved to memory from an even numbered register must be restored to an even register likewise for odd registers The address of the access must be long word aligned Note Moves of extensions into data registers restore the corresponding limit tag bit Ln bit in the destination register Operation Assembler Syntax SP s15 8 0 De E MOVE L SP s15 De E 214 s15 214 L Da E Db E SP s15 MOVE ...

Page 590: ...into the extension and Ln bit of an even numbered data register MOVE L Da E Db E a32 Stores the L and extension bits from one even and one odd data register intoa 32 bit absolute memory address MOVE L a32 Do E Reads from a 32 bit absolute memory address into the extension and Ln bit of an odd numbered data register Register Address Bit Name Description SR 18 EXP Determines which stack pointer is u...

Page 591: ...A A a a 0 0 0 0 0 1 A A A A A A A A A A A A A 1 0 a a a a a a a a a a a a a a 15 8 7 0 MOVE L Da E Db E a32 3 1 3 0 0 0 1 0 f f 0 A A A a a 0 0 0 0 0 1 A A A A A A A A A A A A A 1 0 a a a a a a a a a a a a a a 15 8 7 0 MOVE L a32 Do E 3 1 3 0 0 0 1 1 q q 1 A A A a a 0 0 0 0 0 1 A A A A A A A A A A A A A 1 0 a a a a a a a a a a a a a a 00 D0 01 D2 10 D4 11 D6 Note This instruction can specify D8 D1...

Page 592: ...A 278 SC140 DSP Core Reference Manual MOVE L a32 aaaaaaaaaaaaaaaaAAAAAAAAAAAAAAAA 32 bit absolute long address ...

Page 593: ...sure that the effective address resides on a long word boundary Operation Assembler Syntax aa DR MOVE L a32 DR 0 a32 232 L MOVE L DR a32 aa C4 MOVE L a16 C4 0 a16 216 L MOVE L C4 a16 Rn u3 DR MOVE L Rn u3 DR 0 u3 32 L MOVE L DR Rn u3 Rn s15 DR MOVE L Rn s15 DR 214 s15 214 L MOVE L DR Rn s15 Rn Rr DR MOVE L Rn Rr DR MOVE L DR Rn Rr EA DR MOVE L EA DR MOVE L DR EA Rn C3 MOVE L Rn C3 MOVE L C3 Rn SP ...

Page 594: ...hort immediates are needed MOVE L Rn s15 DR MOVE L DR Rn s15 Moves a 32 bit long word between a data or address register and a memory address pointed to by an address register plus a 15 bit signed offset MOVE L Rn Rr DR MOVE L DR Rn Rr Moves a 32 bit long word between a data or address register and a memory address pointed to by an address register plus the contents of a second address register as...

Page 595: ...n is not affected by MCTL SR 18 EXP Determines which stack pointer is used when the stack pointer is an operand Otherwise the instruction is not affected by SR Register Address Bit Name Description Ln L Clears the Ln bit in the destination register Register Memory Address Before After MCTL 0000 0000 D0 FF FFFF FFFA R0 0000 0084 0084 FFFF FFFA Instruction Words Cycles Type Opcode 15 8 7 0 MOVE L a3...

Page 596: ...r 15 8 7 0 MOVE L EA DR 1 11 1 0 0 w H H H H 1 0 M M M R R R MOVE L DR EA Note indicates serial grouping encoding 15 8 7 0 MOVE L Rn C3 1 1 4 1 0 0 1 D D D D 0 0 0 1 w R R R MOVE L C3 Rn 15 8 7 0 MOVE L SP u6 DR 1 2 2 1 1 1 1 H H H H w 1 s s s s s s MOVE L DR SP u6 15 8 7 0 MOVE L SP s15 C4 2 2 3 0 0 0 w D D D D 1 s s 1 1 0 D 0 MOVE L C4 SP s15 1 0 0 s s s s s s s s s s s s s Note 1 When the form ...

Page 597: ...00 R6 00101 B2 01101 B6 10101 N2 11101 M2 00110 D3 01110 D7 10110 R3 11110 R7 00111 B3 01111 B7 10111 N3 11111 M3 Note This instruction can specify D8 D15 or R8 R15 as operands by using a high register prefix 0000 D0 0100 D4 1000 R0 1100 R4 0001 D1 0101 D5 1001 R1 1101 R5 0010 D2 0110 D6 1010 R2 1110 R6 0011 D3 0111 D7 1011 R3 1111 R7 Note This instruction can specify D8 D15 or R8 R15 as operands ...

Page 598: ...l MOVE L a16 AAAAAAAAAAAAAAAA 16 bit unsigned absolute address a32 aaaaaaaaaaaaaaaaAAAAAAAAAAAAAAAA 32 bit absolute long address s15 sssssssssssssss Signed 15 bit offset u3 sss00 Unsigned 3 bit offset u6 ssssss00 Unsigned 6 bit SP offset ...

Page 599: ...d 7 bit value into the LP of a data or address register and sign extends it MOVE W s16 C4 Loads an immediate signed 16 bit value into the LP of a general register and sign extends it MOVE W s16 a16 Writes an immediate signed 16 bit value to an absolute 16 bit address MOVE W s16 SP u5 Writes an immediate signed 16 bit value to a memory address pointed to by the active stack pointer SP minus an unsi...

Page 600: ...move w 0050 r7 Register Address Bit Name Description SR 18 EXP Determines which stack pointer is used when the stack pointer is an operand Otherwise the instruction is not affected by SR Register Address Bit Name Description Ln L Clears the Ln bit in the destination register Register Memory Address Before After immediate 0000 0050 R7 0000 0050 ...

Page 601: ...3 0 0 0 1 1 0 0 0 i i i A A A A A 1 0 1 i i i i i i i i i i i i i 15 8 7 0 MOVE W s16 Rn 2 1 3 0 0 0 1 1 0 0 1 i i i 0 1 R R R 1 0 1 i i i i i i i i i i i i i 15 8 7 0 MOVE W s16 SP sa16 3 2 3 0 0 1 1 1 0 0 0 A A A i i 1 0 1 0 0 1 A A A A A A A A A A A A A 1 0 i i i i i i i i i i i i i i 00000 D0 01000 D4 10000 R0 11000 R4 00001 B0 01001 B4 10001 N0 11001 M0 00010 D1 01010 D5 10010 R1 11010 R5 000...

Page 602: ...ruction can specify D8 D15 or R8 R15 as operands by using a high register prefix 000 R0 010 R2 100 R4 110 R6 001 R1 011 R3 101 R5 111 R7 Note This instruction can specify R8 R15 as operands by using a high register prefix s7 iiiiiii 7 bit signed immediate data s16 iiiiiiiiiiiiiiii 16 bit signed immediate data a16 AAAAAAAAAAAAAAAA 16 bit unsigned absolute address sa16 AAAAAAAAAAAAAAAA Signed 16 bit...

Page 603: ...a16 216 W MOVE W C4 a16 Rn u3 DR MOVE W Rn u3 DR 0 u3 16 W MOVE W DR Rn u3 Rn s15 DR MOVE W Rn s15 DR 214 s15 214 W MOVE W DR Rn s15 Rn Rr DR MOVE W Rn Rr DR MOVE W DR Rn Rr EA DR MOVE W EA DR MOVE W DR EA Rn C3 MOVE W Rn C3 MOVE W C3 Rn SP u6 DR MOVE W SP u6 DR 0 u6 128 W MOVE W DR SP u6 SP s15 C4 MOVE W SP s15 C4 214 s15 214 W MOVE W C4 SP s15 MOVE W a32 DR MOVE W DR a32 Moves a signed word betw...

Page 604: ...s a signed word between a data or address register DR and a memory address pointed to by an address register Rn with an offset contained in another address register Rr The second address register Rr is shifted left by one bit prior to being added The modifier mode of this instruction is determined by Rn in MCTL Rr is limited to R0 R7 MOVE W EA DR MOVE W DR EA Moves a signed word between a data or ...

Page 605: ...dress modification bits when updating R0 R7 Otherwise the instruction is not affected by MCTL SR 18 EXP Determines which stack pointer is used when the stack pointer is an operand Otherwise the instruction is not affected by SR Register Address Bit Name Description Ln L Clears the Ln bit in the destination registers Register Memory Address Before After MCTL 0000 0000 d1 FF FFFF FFF1 R7 0000 000A 0...

Page 606: ...u3 15 8 7 0 MOVE W Rn s15 DR 2 2 3 0 0 0 w H H H H 0 s s 0 0 R R R MOVE W DR Rn s15 1 0 0 s s s s s s s s s s s s s 15 8 7 0 MOVE W Rn Rr DR 1 2 4 1 0 1 0 H H H H w 0 R R R r r r MOVE W DR Rn Rr 15 8 7 0 MOVE W EA DR 1 12 1 0 0 w H H H H 0 0 M M M R R R MOVE W DR EA Notes 1 indicates serial grouping encoding 2 When the form Rn N0 is used in EA the cycle count is increased by 1 0 MOVE W Rn C3 1 1 4...

Page 607: ...2 11100 R6 00101 B2 01101 B6 10101 N2 11101 M2 00110 D3 01110 D7 10110 R3 11110 R7 00111 B3 01111 B7 10111 N3 11111 M3 Note This instruction can specify D8 D15 or R8 R15 as operands by using a high register prefix 0000 D0 0100 D4 1000 R0 1100 R4 0001 D1 0101 D5 1001 R1 1101 R5 0010 D2 0110 D6 1010 R2 1110 R6 0011 D3 0111 D7 1011 R3 1111 R7 Note This instruction can specify D8 D15 or R8 R15 as oper...

Page 608: ...al MOVE W a16 AAAAAAAAAAAAAAAA 16 bit unsigned absolute address a32 aaaaaaaaaaaaaaaaAAAAAAAAAAAAAAAA 32 bit absolute long address s15 sssssssssssssss Signed 15 bit offset u3 sss0 Unsigned 3 bit offset u6 ssssss0 Unsigned 6 bit SP offset ...

Page 609: ...d in the address generation stage Status and Conditions that Affect Instruction Status and Conditions Changed by Instruction None Example movet r0 r1 Note 00E4 0002 in the status register indicates that the true bit is set Operation Assembler Syntax If T 1 then Rq Rn MOVET Rq Rn If T 0 then Rq Rn MOVEF Rq Rn MOVET Rq Rn Copies one address register to another if the T bit is set MOVEF Rq Rn Copies ...

Page 610: ...MOVET Rq Rn 1 1 4 1 0 0 1 1 R R R 0 1 0 1 0 q q q 15 8 7 0 MOVEF Rq Rn 1 1 4 1 0 0 1 1 R R R 0 1 0 1 1 q q q 000 R0 010 R2 100 R4 110 R6 001 R1 011 R3 101 R5 111 R7 Note This instruction can specify R8 R15 as operands by using a high register prefix 000 R0 010 R2 100 R4 110 R6 001 R1 011 R3 101 R5 111 R7 Note This instruction can specify R8 R15 as operands by using a high register prefix ...

Page 611: ... post increment The first operand Da will be moved to the lower memory address EA The second operand Db will be moved to memory address EA 2 In order to keep this behavior in both big endian and little endian modes the core will interpret the data bus differently in each mode See Section 2 4 1 SC140 Endian Support on page 2 56 for more detail on bus and memory behavior for each mode Register Addre...

Page 612: ...F 0056 7EAC Instruction Words Cycles Type Opcode 15 8 7 0 MOVES 2F Da Db EA 1 12 1 0 0 0 1 h h 1 0 1 M M M R R R Notes 1 indicates serial grouping encoding 2 When the form Rn N0 is used in EA the cycle count is increased by 1 00 D0 D1 01 D2 D3 10 D4 D5 11 D6 D7 Note This instruction can specify D8 D15 as operands by using a prefix 000 Rn N0 010 Rn 100 Rn N0 110 Rn N2 001 Rn 011 Rn 101 Rn N1 111 Rn...

Page 613: ... will be moved to the lower memory address EA The second operand Db will be moved to memory address EA 2 The third operand Dc will be moved to memory address EA 4 And the fourth operand Dd will be moved to memory address EA 6 In order to keep this behavior in both big endian and little endian modes the core will drive the data bus differently in each mode See Section 2 4 1 SC140 Endian Support on ...

Page 614: ... 7FFF FFFF L2 D2 1 87 6543 2100 L3 D3 0 FF 8765 4321 0050 7FFF 0052 7FFF 0054 8000 0056 8765 Instruction Words Cycles Type Opcode 15 8 7 0 MOVES 4F 1 12 1 0 0 0 1 k 0 0 1 1 M M M R R R Da Db Dc Dd EA 0 D0 D1 D2 D3 1 D4 D5 D6 D7 Note This instruction can specify D8 D15 as operands by using a prefix 000 Rn N0 010 Rn 100 Rn N0 110 Rn N2 001 Rn 011 Rn 101 Rn N1 111 Rn N3 000 R0 010 R2 100 R4 110 R6 00...

Page 615: ...OVES F Db a16 0 a16 216 W Db aa MOVES F Db a32 0 a32 232 W Db Rn s15 MOVES F Db Rn s15 214 s15 214 W Db EA MOVES F Db EA Db SP s15 MOVES F Db SP s15 214 s15 214 W MOVES F Db a16 Writes the HP of a data register Db to an absolute 16 bit memory address MOVES F Db a32 Writes the HP of a data register Db to an absolute 32 bit memory address MOVES F Db Rn s15 Writes the HP of a data register Db to a me...

Page 616: ...s for R0 R7 SR 5 4 S 1 0 Scaling mode bits choose no scaling scale up one bit or scale down one bit Ln L Limited values are written to the destination if the Ln bit is set SR 18 EXP Determines the stack pointer used in instructions that have a stack pointer as an operand Register Address Bit Name Description SR 6 S Scaling bit set when the absolute value of the data moved after scaling and limitin...

Page 617: ... s s s s s s s 15 8 7 0 MOVES F Db EA 1 12 1 0 0 0 0 j j j 0 1 M M M R R R Notes 1 indicates serial grouping encoding 2 When the form Rn N0 is used in EA the cycle count is increased by 1 15 8 7 0 MOVES F Db SP s15 2 2 3 0 0 0 0 0 j j j 1 s s 1 1 1 1 0 1 0 0 s s s s s s s s s s s s s 000 D0 010 D2 100 D4 110 D6 001 D1 011 D3 101 D5 111 D7 Note This instruction can specify D8 D15 as operands by usi...

Page 618: ...A 304 SC140 DSP Core Reference Manual MOVES 4F s15 sssssssssssssss Signed 15 bit offset ...

Page 619: ... MOVES L Db EA Moves a saturated long word from a data register Db to a memory address pointed to by an address register with an optional offset or post increment Register Address Bit Name Description MCTL 31 0 AM3 AM0 Address modification bits when updating R0 R7 Otherwise the instruction is not affected by MCTL SR 5 4 S 1 0 Scaling mode bits choose no scaling scale up one bit or scale down one b...

Page 620: ...gister EA MMM Effective Address Notation Instruction Words Cycles Type Opcode 15 8 7 0 MOVES L Db EA 1 12 1 0 0 0 0 j j j 1 1 M M M R R R 000 R0 010 R2 100 R4 110 R6 001 R1 011 R3 101 R5 111 R7 Note This instruction can specify R8 R15 as operands by using a high register prefix 000 D0 010 D2 100 D4 110 D6 001 D1 011 D3 101 D5 111 D7 Note This instruction can specify D8 D15 as operands by using a p...

Page 621: ...ed absolute address in memory into a data or address register DR MOVEU B a32 DR Reads an unsigned byte from an absolute 32 bit address in memory into a data or address register DR MOVEU B Rn s15 DR Reads an unsigned byte from a memory address pointed to by an address register with a signed 15 bit offset into a data or address register DR MOVEU B ea DR Reads an unsigned byte from a memory address p...

Page 622: ...MCTL 31 0 AM3 AM0 Address modification bits when updating R0 R7 Otherwise the instruction is not affected by MCTL SR 18 EXP Determines which stack pointer is used when the stack pointer is an operand Otherwise the instruction is not affected by SR Register Address Bit Name Description Ln L Clears the Ln bit in the destination registers Register Memory Address Before After 0053 F8 D10 0 00 0000 00F...

Page 623: ... 0 0 s s s s s s s s s s s s s 15 8 7 0 MOVEU B ea DR 1 11 Note 1 When the form Rn N0 is used in ea the cycle count is increased by 1 4 1 0 0 1 H H H H 1 0 1 M M R R R 15 8 7 0 MOVEU B SP s15 DR 2 2 3 0 0 0 1 H H H H 0 s s 1 1 1 0 0 1 0 0 s s s s s s s s s s s s s 0000 D0 0100 D4 1000 R0 1100 R4 0001 D1 0101 D5 1001 R1 1101 R5 0010 D2 0110 D6 1010 R2 1110 R6 0011 D3 0111 D7 1011 R3 1111 R7 Note Th...

Page 624: ...A 310 SC140 DSP Core Reference Manual MOVEU B a32 aaaaaaaaaaaaaaaaAAAAAAAAAAAAAAAA 32 bit absolute long address s15 sssssssssssssss Signed 15 bit offset ...

Page 625: ...ged by Instruction Example moveu l fffffff8 d3 Operation Assembler Syntax u32 Db MOVEU L u32 Db 0 u32 232 MOVEU L u32 Db Loads an unsigned long word 32 bit immediate value into a data register Db zero extending it Register Address Bit Name Description Ln L Clears the Ln bit in the destination register Register Memory Address Before After Immediate FFFF FFF8 D3 0 00 FFFF FFFF8 ZERO EXTENSION 39 0 3...

Page 626: ...Words Cycles Type Opcode 15 8 7 0 MOVEU L u32 Db 3 1 3 0 0 1 1 0 j j j i i i I I 0 0 1 0 0 1 i i i i i i i i i i i i i 1 0 I I I I I I I I I I I I I I 000 D0 010 D2 100 D4 110 D6 001 D1 011 D3 101 D5 111 D7 Note This instruction can specify D8 D15 as operands by using a prefix u32 31 IIIIIIIIIIIIIIII 16 15 iiiiiiiiiiiiiiii 0 32 bit unsigned immediate data ...

Page 627: ... l Operation Assembler Syntax u16 Db 31 16 MOVEU W u16 Db H 0 u16 216 u16 Db 15 0 MOVEU W u16 Db L 0 u16 216 MOVEU W u16 Db H Loads an immediate unsigned word into the HP of a data register Db The other bits in the register are unchanged MOVEU W u16 Db L Loads an immediate unsigned word into the LP of a data register Db The other bits in the register are unchanged Register Address Bit Name Descrip...

Page 628: ...pcode 15 8 7 0 MOVEU W u16 Db H 2 1 3 0 0 0 1 1 0 0 1 i i i 1 0 j j j 1 0 1 i i i i i i i i i i i i i 15 8 7 0 MOVEU W u16 Db L 2 1 3 0 0 0 1 1 0 0 1 i i i 0 0 j j j 1 0 1 i i i i i i i i i i i i i 000 D0 010 D2 100 D4 110 D6 001 D1 011 D3 101 D5 111 D7 Note This instruction can specify D8 D15 as operands by using a prefix u16 iiiiiiiiiiiiiiii 16 bit unsigned immediate data ...

Page 629: ...ned word from an absolute 32 bit address places the data in the LP of a data or address register DR and zero extends the upper bits MOVEU W Rn s15 DR Reads an unsigned word from a memory address pointed to by an address register Rn with a signed 15 bit offset places the data in the LP of a data or address register DR and zero extends the upper bits MOVEU W EA DR Reads an unsigned word from a memor...

Page 630: ...dress modification bits when updating R0 R7 Otherwise the instruction is not affected by MCTL SR 18 EXP Determines which stack pointer is used when the stack pointer is an operand Otherwise the instruction is not affected by SR Register Address Bit Name Description Ln L Clears the Ln bit in the destination registers Register Memory Address Before After MCTL 0000 0000 R7 0000 0050 R7 2 FFF8 D10 00 ...

Page 631: ...al grouping encoding 2 When the form Rn N0 is used in EA the cycle count is increased by 1 15 8 7 0 MOVEU W SP s15 C4 2 2 3 0 0 0 1 D D D D 1 s s 1 1 1 D 0 1 0 0 s s s s s s s s s s s s s 00000 D0 01000 D4 10000 R0 11000 R4 00001 B0 01001 B4 10001 N0 11001 M0 00010 D1 01010 D5 10010 R1 11010 R5 00011 B1 01011 B5 10011 N1 11011 M1 00100 D2 01100 D6 10100 R2 11100 R6 00101 B2 01101 B6 10101 N2 11101...

Page 632: ... N2 001 Rn 011 Rn 101 Rn N1 111 Rn N3 000 R0 010 R2 100 R4 110 R6 001 R1 011 R3 101 R5 111 R7 Note This instruction can specify R8 R15 as operands by using a high register prefix a16 AAAAAAAAAAAAAAAA 16 bit unsigned absolute address a32 aaaaaaaaaaaaaaaaAAAAAAAAAAAAAAAA 32 bit absolute long address s15 sssssssssssssss Signed 15 bit offset ...

Page 633: ... Name Description SR 2 SM If set selects 32 bit arithmetic saturation mode SR 5 4 S 1 0 Scaling bits determine which bits in the result are used in the Ln bit calculation Register Address Bit Name Description Ln L If not in arithmetic saturation mode SR SM 0 calculates and updates the Ln bit in the destination register If in arithmetic saturation mode SR SM 1 clears the Ln bit in the destination r...

Page 634: ...tion can specify D8 D15 as operands by using a prefix 00000 D0 D4 01000 D2 D4 10000 D0 D0 11000 D1 D2 00001 D0 D5 01001 D2 D5 10001 D0 D1 11001 D1 D3 00010 D0 D6 01010 D2 D6 10010 D0 D2 11010 D5 D6 00011 D0 D7 01011 D2 D7 10011 D0 D3 11011 D5 D7 00100 D1 D4 01100 D3 D4 10100 D4 D4 11100 D2 D2 00101 D1 D5 01101 D3 D5 10101 D4 D5 11101 D2 D3 00110 D1 D6 01110 D3 D6 10110 D4 D6 11110 D6 D6 00111 D1 D...

Page 635: ...40 DSP Core Reference Manual A 321 Dn FFF Single Source Destination Data Register 000 D0 010 D2 100 D4 110 D6 001 D1 011 D3 101 D5 111 D7 Note This instruction can specify D8 D15 as operands by using a prefix ...

Page 636: ...r and then zeros the low part The two modes of the round function Rnd are described on page A 359 Register Address Bit Name Description SR 2 SM If set selects 32 bit arithmetic saturation mode SR 3 RM Rounding mode SR 5 4 S 1 0 Scaling bits determine which bits in the result are used in the Ln bit calculation and which bits are used in rounding Register Address Bit Name Description Ln L If not in ...

Page 637: ... 00010 D0 D6 01010 D2 D6 10010 D0 D2 11010 D5 D6 00011 D0 D7 01011 D2 D7 10011 D0 D3 11011 D5 D7 00100 D1 D4 01100 D3 D4 10100 D4 D4 11100 D2 D2 00101 D1 D5 01101 D3 D5 10101 D4 D5 11101 D2 D3 00110 D1 D6 01110 D3 D6 10110 D4 D6 11110 D6 D6 00111 D1 D7 01111 D3 D7 10111 D4 D7 11111 D6 D7 Notes 1 This instruction can specify D8 D15 as operands by using a prefix 2 Register pair order can be inverted...

Page 638: ...A 324 SC140 DSP Core Reference Manual MPYR ...

Page 639: ... signed fractional multiplication between the signed 16 bit HP of the first register Dc of a data register pair with the unsigned 16 bit LP of the second register Dd It then stores the sign extended 32 bit product in a destination data register Dn Register Address Bit Name Description Ln L Clears the Ln bit in the destination registers Register Memory Address Before After D4 FF C000 0001 D5 FF E00...

Page 640: ...140 DSP Core Reference Manual MPYSU Dn FFF Single Source Destination Data Register 000 D0 010 D2 100 D4 110 D6 001 D1 011 D3 101 D5 111 D7 Note This instruction can specify D8 D15 as operands by using a prefix ...

Page 641: ... Assembler Syntax Dc L Dd H Dn MPYUS Dc Dd Dn MPYUS Dc Dd Dn Performs signed fractional multiplication between the unsigned 16 bit LP of the first register Dc of a data register pair with the signed 16 bit HP of the second register Dd It then stores the sign extended 32 bit product in a destination data register Dn Register Address Bit Name Description Ln L Clears the Ln bit in the destination reg...

Page 642: ... Pairs Dn FFF Single Source Destination Data Register 00 D0 D1 01 D2 D3 10 D4 D5 11 D6 D7 Note This instruction can specify D8 D15 as operands by using a prefix 000 D0 010 D2 100 D4 110 D6 001 D1 011 D3 101 D5 111 D7 Note This instruction can specify D8 D15 as operands by using a prefix ...

Page 643: ... Dc L Dd L Dn MPYUU Dc Dd Dn MPYUU Dc Dd Dn Performs unsigned fractional multiplication between the unsigned 16 bit LP of the first register Dc of a data register pair with the unsigned 16 bit LP of the second register Dd It then stores the sign extended 32 bit product in a destination data register Dn Register Address Bit Name Description Ln L Clears the Ln bit in the destination registers Regist...

Page 644: ... Pairs Dn FFF Single Source Destination Data Register 00 D0 D1 01 D2 D3 10 D4 D5 11 D6 D7 Note This instruction can specify D8 D15 as operands by using a prefix 000 D0 010 D2 100 D4 110 D6 001 D1 011 D3 101 D5 111 D7 Note This instruction can specify D8 D15 as operands by using a prefix ...

Page 645: ...nation data register Dn Register Address Bit Name Description SR 2 SM If set selects 32 bit arithmetic saturation mode SR 5 4 S 1 0 Scaling mode bits determine which bits in the result are used in the Ln bit calculation Register Address Bit Name Description Ln L If not in arithmetic saturation mode SR SM 0 calculates and updates the Ln bit in the destination register If in arithmetic saturation mo...

Page 646: ...rouping encoding Instruction Fields Dn FFF Single Source Destination Data Register Instruction Words Cycles Type Opcode 15 8 7 0 NEG Dn 1 1 1 0 1 0 0 1 F F F 1 1 0 0 1 0 0 000 D0 010 D2 100 D4 110 D6 001 D1 011 D3 101 D5 111 D7 Note This instruction can specify D8 D15 as operands by using a prefix ...

Page 647: ...case delays are needed in a program for various reasons for example to account for pipeline delays The NOP instruction is not dispatched to any execution unit As a prefix it is identified by the dispatcher and is not dispatched further If grouped with other instructions as an intra group NOP it functions as a program place holder In a few isolated cases the assembler adds this instruction inside a...

Page 648: ... Dn NOT Da Dn NOT Da Dn Replaces the contents of the destination data register Dn with the 40 bit one s complement of the source data register Da Register Address Bit Name Description Ln L Clears the Ln bit in the destination register Register Memory Address Before After D4 FF FFFF FFFB L5 D5 0 00 0000 0004 Instruction Words Cycles Type Opcode 15 8 7 0 NOT Da Dn 1 1 2 1 1 0 1 1 0 F F F 0 0 0 0 J J...

Page 649: ...OT SC140 DSP Core Reference Manual A 335 Da JJJ Single Source Data Register 000 D0 010 D2 100 D4 110 D6 001 D1 011 D3 101 D5 111 D7 Note This instruction can specify D8 D15 as operands by using a prefix ...

Page 650: ...verts the LP of a source data or address register DR The other bits are unchanged This instruction is assembler mapped to BMCHG DR L with the full mask enabled NOT DR H Inverts the HP of a source data or address register DR The other bits are unchanged This instruction is assembler mapped to BMCHG DR H with the full mask enabled Register Address Bit Name Description Ln L Clears the Ln bit in the d...

Page 651: ...2 2 3 0 0 0 0 1 0 1 0 1 1 1 0 H H H H 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 15 8 7 0 NOT DR H 2 2 3 0 0 0 0 1 0 1 0 1 1 1 1 H H H H 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0000 D0 0100 D4 1000 R0 1100 R4 0001 D1 0101 D5 1001 R1 1101 R5 0010 D2 0110 D6 1010 R2 1110 R6 0011 D3 0111 D7 1011 R3 1111 R7 Note This instruction can specify D8 D15 or R8 R15 as operands by using a high register prefix ...

Page 652: ... assembler mapped to BMCHG W FFFF Rn The full mask is enabled NOT W SP u5 Replaces the contents of a memory address pointed to by the active stack pointer SP minus a 5 bit unsigned immediate value with its complement This instruction is assembler mapped to BMCHG W FFFF SP u5 The full mask is enabled NOT W SP s16 Replaces the contents of a memory address pointed to by the active stack pointer SP of...

Page 653: ...A A A A A 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 15 8 7 0 NOT W SP s16 3 3 3 0 0 1 1 1 0 1 0 A A A 1 1 0 1 1 0 0 1 A A A A A A A A A A A A A 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 15 8 7 0 NOT W a16 3 2 3 0 0 1 1 1 0 1 0 A A A 1 1 0 0 1 0 0 1 A A A A A A A A A A A A A 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 000 R0 010 R2 100 R4 110 R6 001 R1 011 R3 101 R5 111 R7 Note This instruction can specify R8 R15 as operands by u...

Page 654: ...n OR Da Dn OR Da Dn Performs a bitwise inclusive OR of two data registers Da and Dn and stores the result in the second data register Dn This is a full 40 bit operation Register Address Bit Name Description Ln L Clears the Ln bit in the destination registers Register Memory Address Before After D3 E0 0007 0005 L0 D0 0 50 0003 0008 0 F0 0007 000F Instruction Words Cycles Type Opcode 15 8 7 0 OR Da ...

Page 655: ...40 DSP Core Reference Manual A 341 Dn FFF Single Source Destination Data Register 000 D0 010 D2 100 D4 110 D6 001 D1 011 D3 101 D5 111 D7 Note This instruction can specify D8 D15 as operands by using a prefix ...

Page 656: ...hen stores the result in the LP of the destination data or address register DR The other register bits are not affected This instruction is assembler mapped to BMSET u16 DR L with the immediate value OR u16 DR H Performs a bitwise inclusive OR of an immediate value with the HP of a data or address register DR It then stores the result in the HP of the destination data or address register DR The ot...

Page 657: ... 0 H H H H 1 0 1 i i i i i i i i i i i i i 15 8 7 0 OR u16 DR H 2 2 3 0 0 0 0 1 0 0 1 i i i 1 H H H H 1 0 1 i i i i i i i i i i i i i 0000 D0 0100 D4 1000 R0 1100 R4 0001 D1 0101 D5 1001 R1 1101 R5 0010 D2 0110 D6 1010 R2 1110 R6 0011 D3 0111 D7 1011 R3 1111 R7 Note This instruction can specify D8 D15 or R8 R15 as operands by using a high register prefix u16 iiiiiiiiiiiiiiii 16 bit unsigned immedi...

Page 658: ... Rn with the immediate value OR W u16 SP u5 Performs a bitwise inclusive OR of an immediate unsigned word with the contents of a memory address pointed to by the active stack pointer SP minus an unsigned 5 bit offset It then stores the result in the memory address This instruction is assembler mapped to BMSET W u16 SP u5 with the immediate value OR W u16 SP s16 Performs a bitwise inclusive OR of a...

Page 659: ... W u16 SP u5 2 3 3 0 0 0 0 0 0 0 1 i i i A A A A A 1 0 1 i i i i i i i i i i i i i 15 8 7 0 OR W u16 SP s16 3 3 3 0 0 1 1 1 0 0 1 A A A i i 0 1 1 0 0 1 A A A A A A A A A A A A A 1 0 i i i i i i i i i i i i i i 15 8 7 0 OR W u16 a16 3 2 3 0 0 1 1 1 0 0 1 A A A i i 0 0 1 0 0 1 A A A A A A A A A A A A A 1 0 i i i i i i i i i i i i i i 000 R0 010 R2 100 R4 110 R6 001 R1 011 R3 101 R5 111 R7 Note This ...

Page 660: ...A 346 SC140 DSP Core Reference Manual OR W s16 AAAAAAAAAAAAAAAA Signed 16 bit SP address offset ...

Page 661: ...ferent register group If the register is a DALU register bits 39 32 of the destination are sign extended from bit 31 and the Ln bit is cleared Hence in order to restore a full data register the extension should be popped last Extensions of data registers with the associated Ln bits are special Extensions of even and odd registers are read from bits 8 0 and 24 16 of the long data word respectively ...

Page 662: ... Bit Name Description Ln L Pops of extensions restore the Ln bit in the destination register Pops to data registers clear the Ln bit Register Memory Address Before After SR 00E00000 NSP 00000010 00000008 0000000C 2E03FF4E L3 D3 0 002E03FF4E Instruction Words Cycles1 Note 1 An extra cycle is added if the shadow SP is not valid when the POP instruction is executed See Section 5 5 4 Shadow Stack Poin...

Page 663: ...101 B6 10101 N2 11101 M2 00110 01110 10110 SA1 11110 SA3 00111 D2 E 01111 D6 E 10111 D2 E D3 E 11111 D6 E D7 E Note If registers D8 D15 or R8 R15 are accessed instead of D0 D7 or R0 R7 a prefix is used 00000 D1 01000 D5 10000 R1 11000 R5 00001 B1 01001 B5 10001 N1 11001 M1 00010 VBA 01010 SR 10010 LC0 11010 LC2 00011 D1 E 01011 D5 E 10011 11011 00100 D3 01100 D7 10100 R3 11100 R7 00101 B3 01101 B7...

Page 664: ...tions can appear in an execution set In both cases NSP is decremented only once by 8 When two POP instructions are grouped together in an execution set each must be in a different register group If the register is a DALU register bits 39 32 of the destination are sign extended from bit 31 and the Ln bit is cleared Hence in order to restore a full data register the extension should be popped last E...

Page 665: ...ers from the normal stack Register Address Bit Name Description SR 18 EXP Determines execution working mode Register Address Bit Name Description Ln L Pops of extensions restore the Ln bit in the destination register Pops to data registers clear the Ln bit Register Memory Address Before After NSP 00000010 00000008 00000008 000000FF L6 D6 0 FF00000000 L7 D7 0 0000000000 Instruction Words Cycles1 No...

Page 666: ...1101 B6 10101 N2 11101 M2 00110 01110 10110 SA1 11110 SA3 00111 D2 E 01111 D6 E 10111 D2 E D3 E 11111 D6 E D7 E Note If registers D8 D15 or R8 R15 are accessed instead of D0 D7 or R0 R7 a prefix is used 00000 D1 01000 D5 10000 R1 11000 R5 00001 B1 01001 B5 10001 N1 11001 M1 00010 VBA 01010 SR 10010 LC0 11010 LC2 00011 D1 E 01011 D5 E 10011 11011 00100 D3 01100 D7 10100 R3 11100 R7 00101 B3 01101 B...

Page 667: ...USH instructions are grouped together in an execution set each must be in a different register group Extensions of data registers with the associated Ln bits are special Extensions of even and odd registers are written to bits 8 0 and 24 16 of the long data word respectively both for single register and register pair operations see the figure below Note For proper data register restoration extensi...

Page 668: ... Register Address Bit Name Description SR 18 EXP Determines which stack pointer used and execution working mode Register Memory Address Before After SR 00E40000 ESP 00000000 00000008 00000000 00000000 000000FF L0 D0 0 FF89ABCDEF L1 D1 0 0001234567 Instruction Words Cycles Type Opcode 15 8 7 0 PUSH De 1 1 4 1 0 0 1 E E E 0 0 0 1 E 0 0 E 0 15 8 7 0 PUSH Do 1 1 4 1 0 0 1 e e e 1 0 0 1 e 0 0 e 0 ...

Page 669: ...0101 B2 01101 B6 10101 N2 11101 M2 00110 01110 10110 SA1 11110 SA3 00111 D2 E 01111 D6 E 10111 D2 E D3 E 11111 D6 E D7 E Note If registers D8 D15 or R8 R15 are accessed instead of D0 D7 or R0 R7 a prefix is used 00000 D1 01000 D5 10000 R1 11000 R5 00001 B1 01001 B5 10001 N1 11001 M1 00010 VBA 01010 SR 10010 LC0 11010 LC2 00011 D1 E 01011 D5 E 10011 11011 00100 D3 01100 D7 10100 R3 11100 R7 00101 B...

Page 670: ...SP is incremented only once by 8 When two PUSHN instructions are grouped together in an execution set each must be in a different register group Extensions of data registers with the associated Ln bits are special Extensions of even and odd registers are written to bits 8 0 and 24 16 of the long data word respectively both for single register and register pair operations see the figure below Note ...

Page 671: ... e d1 e Register Address Bit Name Description SR 18 EXP Determines execution working mode Register Address Bit Name Description Ln L Pops of extensions restore the Ln bit in the destination register Pops to data registers clear the Ln bit Register Memory Address Before After NSP 00000008 000000010 L0 D0 0 FF89ABCDEF L1 D1 0 0001234567 000008 000000FF ...

Page 672: ...00011 D0 E 01011 D4 E 10011 D0 E D1 E 11011 D4 E D5 E 00100 D2 01100 D6 10100 R2 11100 R6 00101 B2 01101 B6 10101 N2 11101 M2 00110 01110 10110 SA1 11110 SA3 00111 D2 E 01111 D6 E 10111 D2 E D3 E 11111 D6 E D7 E Note If registers D8 D15 or R8 R15 are accessed instead of D0 D7 or R0 R7 a prefix is used 00000 D1 01000 D5 10000 R1 11000 R5 00001 B1 01001 B5 10001 N1 11001 M1 00010 VBA 01010 SR 10010 ...

Page 673: ...he left of the rounding position is cleared in the result ensuring that the result is even An even result eliminates the two s complement bias where 1 2 is always rounded up See Section 2 2 2 6 Rounding Modes on page 2 21 for more detailed information The following table shows the rounding position LP MSB and rounding constant RC as determined by the scaling mode bits Operation Assembler Syntax Rn...

Page 674: ... RM Rounding mode SR 5 4 S 1 0 Scaling bits determine which bits in the result are used in the Ln bit calculation and which bits are used in rounding Register Address Bit Name Description Ln L If not in arithmetic saturation mode SR SM 0 calculates and updates the Ln bit in the destination register If in arithmetic saturation mode SR SM 1 clears the Ln bit in the destination register EMR 2 DOVF Se...

Page 675: ... Da JJJ Single Source Data Register Instruction Words Cycles Type Opcode 15 8 7 0 RND Da Dn 1 1 1 0 1 1 0 1 F F F 1 0 0 1 J J J 000 D0 010 D2 100 D4 110 D6 001 D1 011 D3 101 D5 111 D7 Note This instruction can specify D8 D15 as operands by using a prefix 000 D0 010 D2 100 D4 110 D6 001 D1 011 D3 101 D5 111 D7 Note This instruction can specify D8 D15 as operands by using a prefix ...

Page 676: ... bit to the left The carry bit C is shifted to bit 0 bit 39 is copied to the carry bit and bits 38 0 are copied to bits 39 1 Register Address Bit Name Description SR 0 C The carry bit is copied into Dn 0 Register Address Bit Name Description SR 0 C Set if bit 39 in the data register was one before rotation Cleared if bit 39 in the data register was zero before rotation Ln L Clears the Ln bit in th...

Page 677: ...rouping encoding Instruction Fields Dn FFF Single Source Destination Data Register Instruction Words Cycles Type Opcode 15 8 7 0 ROL Dn 1 1 1 0 1 0 0 1 F F F 1 1 0 0 0 1 0 000 D0 010 D2 100 D4 110 D6 001 D1 011 D3 101 D5 111 D7 Note This instruction can specify D8 D15 as operands by using a prefix ...

Page 678: ... bit to the right The carry bit C is shifted to bit 39 bit 0 is copied to the carry bit and bits 39 1 are copied to bits 38 0 Register Address Bit Name Description SR 0 C The carry bit is copied into Dn 39 Register Address Bit Name Description SR 0 C Set if bit 0 in the data register was one before rotation Cleared if bit 0 in the data register was zero before rotation Ln L Clears the Ln bit in th...

Page 679: ...rouping encoding Instruction Fields Dn FFF Single Source Destination Data Register Instruction Words Cycles Type Opcode 15 8 7 0 ROR Dn 1 1 1 0 1 0 0 1 F F F 1 1 0 0 0 1 1 000 D0 010 D2 100 D4 110 D6 001 D1 011 D3 101 D5 111 D7 Note This instruction can specify D8 D15 as operands by using a prefix ...

Page 680: ...ister are popped from the active stack in memory and program execution continues at the address specified in the PC This instruction cannot appear in an execution set with another AGU instruction or a set that uses IFT and IFF IFT and IFA or IFF and IFA because RTE uses both AGUs RTE does two simultaneous 32 bit long word memory accesses Instructions that change SR cannot appear in the same set wi...

Page 681: ...r ESP 00000010 00000008 000C 00E00000 0008 0000000A PC 0000000A SR 00E40000 00E00000 EMR 00000000 Instruction Words Cycles1 Note 1 The shadow SP is valid or not valid RTE uses 5 cycles if the shadow SP is valid RTE uses 6 cycles if the shadow SP is not valid Type Opcode 15 8 7 0 RTE 1 5 6 4 1 0 0 1 1 1 1 1 0 1 1 1 0 0 1 1 ...

Page 682: ...ss specified in PC This instruction cannot appear in an execution set with another AGU instruction or a set that uses IFT and IFF IFT and IFA or IFF and IFA because RTED uses both AGUs RTED does two simultaneous 32 bit long word memory accesses Instructions that change SR cannot appear in the same set with this instruction or in the delay slot following the instruction Note Because RTED does not u...

Page 683: ...ute the not instruction and the inc d1 instruction in the delay slot Return to the original working mode see exam ple for RTE Instruction Words Cycles1 Note 1 The shadow SP is valid or not valid RTED uses 5 cycles if the shadow SP is valid RTED uses 6 cycles if the shadow SP is not valid To get the correct cycle count for this instruction subtract the execution time used by the execution set in th...

Page 684: ...d then RAS PC else SP 8 PC always SP 8 SP RTS RTS Returns from a subroutine If the RAS is valid the PC is restored from the RAS Otherwise the PC is popped from the active stack in memory as a 32 bit long word The stack pointer always decrements by 8 RAS becomes invalid and program execution continues at the address specified in the PC Register Address Bit Name Description SR 18 EXP Determines whic...

Page 685: ...s Instruction Words Cycles1 Note 1 RTS uses 3 cycles if the RAS is valid RTS uses 5 cycles if the RAS is not valid and the shadow SP is valid RTS uses 6 cycles if neither the RAS nor the shadow SP are valid Type Opcode 15 8 7 0 RTS 1 3 5 6 4 1 0 0 1 1 1 1 1 0 1 1 1 0 0 0 1 ...

Page 686: ... before the execution set in the delay slot is executed The stack pointer always decrements by 8 RAS becomes invalid and program execution continues at the address specified in the PC Note Because RTSD uses the RAS mechanism returning from an exception using RTSD is illegal The result is undefined Register Address Bit Name Description SR 18 EXP Determines which stack pointer is used Instruction Co...

Page 687: ...id and the shadow SP is valid RTSD uses 6 cycles if neither the RAS nor the shadow SP are valid To get the correct cycle count for this instruction subtract the execution time taken by the execution set in the delay slot The cycle count for this instruction cannot be less than 1 cycle 2 cycles if shadow SP is not valid Type Opcode 15 8 7 0 RTSD 1 3 5 6 4 1 0 0 1 1 1 1 1 0 1 1 1 0 0 0 0 ...

Page 688: ...active stack in memory The restore to the PC is not from the RAS register even if RAS is valid The implicit pop is done before the execution set in the delay slot is executed The stack pointer decrements by 8 and RAS becomes invalid This instruction can be used to bypass RAS for example when the return address is changed directly on the stack RTSTK does one 32 bit long word memory access Register ...

Page 689: ...w 16 d4 Execute the subroutine here move w lbl SP 8 Change the original value in the stack for PC to lbl rtstk Restore the new value lbl to PC move l 16 d5 This instruction skipped lbl move l 16 d6 Continue executing here Instruction Words Cycles1 Note 1 RTSTK uses 5 cycles if the shadow SP is valid RTSTK uses 6 cycles if the shadow SP is not valid Type Opcode 15 8 7 0 RTSTK 1 5 6 4 1 0 0 1 1 1 1 ...

Page 690: ...n memory after executing the execution set in the delay slot The restore to the PC is not from the RAS register even if RAS is valid The implicit pop is done before the execution set in the delay slot is executed The stack pointer decrements by 8 and RAS becomes invalid This instruction can be used to bypass RAS for example when the return address is changed directly on the stack RTSTK does one 32...

Page 691: ...ore the new value lbl to PC Load 35 into d1 Incre ment d1 to 36 the delay slot instruction move l 16 d5 This instruction skipped lbl move l 16 d6 Continue executing here Instruction Words Cycles1 Note 1 RTSTKD uses 5 cycles if shadow SP is valid RTSTKD uses 6 cycles if the shadow SP is not valid To get the correct cycle count for this instruction subtract the execution time used by the execution s...

Page 692: ...d to the destination register and the LP is cleared If the source register indicates an overflow the saturated value positive or negative depending on bit 39 is transferred to the HP of the destination register sign extended and the LP is cleared The saturated positive value is 007FFF0000 the saturated negative value is FF80000000 This operation is independent of the SM bit in SR It is intended fo...

Page 693: ...le Source Destination Data Register Instruction Words Cycles Type Opcode 15 8 7 0 SAT F Da Dn 1 1 1 0 1 1 0 1 F F F 1 0 1 1 J J J 000 D0 010 D2 100 D4 110 D6 001 D1 011 D3 101 D5 111 D7 Note This instruction can specify D8 D15 as operands by using a prefix 000 D0 010 D2 100 D4 110 D6 001 D1 011 D3 101 D5 111 D7 Note This instruction can specify D8 D15 as operands by using a prefix ...

Page 694: ... left alone If the source register indicates an overflow the saturated value positive or negative depending on bit 39 is transferred to the destination register and sign extended The saturated positive value is 007FFFFFFF the saturated negative value is FF80000000 This operation is independent of the SM bit in SR It is intended for use after an instruction that is not affected by the saturation mo...

Page 695: ...ore Reference Manual A 381 Instruction Fields Dn FFF Single Source Destination Data Register 000 D0 010 D2 100 D4 110 D6 001 D1 011 D3 101 D5 111 D7 Note This instruction can specify D8 D15 as operands by using a prefix ...

Page 696: ...he example which is a 64 bit subtraction Register Address Bit Name Description SR 0 C Subtracted as a borrow from the LSB SR 5 4 S 1 0 Scaling mode bits determine which bits in the result are used in the Ln bit calculation Register Address Bit Name Description EMR 2 DOVF Set if the result cannot be represented in 40 bits Ln L Calculates and updates the Ln bit in the destination register SR 0 C Cal...

Page 697: ... 32 bits calculated by sbc d2 d3 Instruction Formats and Opcodes Note indicates serial grouping encoding Instruction Fields Dc Dd ee Data Register Pairs SR 00E4 0001 00E4 0000 EMR 0000 0000 Instruction Words Cycles Type Opcode 15 8 7 0 SBC Dc Dd 1 1 1 0 1 0 1 1 e e 0 1 1 1 1 0 1 1 00 D0 D1 01 D2 D3 10 D4 D5 11 D6 D7 Note This instruction can specify D8 D15 as operands by using a prefix Register Me...

Page 698: ...nd function Rnd are described on page A 359 Register Address Bit Name Description SR 2 SM If set selects 32 bit arithmetic saturation mode SR 3 RM Rounding mode SR 5 4 S 1 0 Scaling bits determine which bits in the result are used in the Ln bit calculation and which bits are used in rounding Register Address Bit Name Description EMR 2 DOVF Set if the result cannot be represented in 40 bits or if t...

Page 699: ...g encoding Instruction Fields Da JJJ Single Source Data Register Dn FFF Single Source Destination Data Register Instruction Words Cycles Type Opcode 15 8 7 0 SBR Da Dn 1 1 1 0 1 1 0 0 F F F 1 0 0 1 J J J 000 D0 010 D2 100 D4 110 D6 001 D1 011 D3 101 D5 111 D7 Note This instruction can specify D8 D15 as operands by using a prefix 000 D0 010 D2 100 D4 110 D6 001 D1 011 D3 101 D5 111 D7 Note This ins...

Page 700: ... less than or equal to zero The displacement is calculated by the assembler and linker SKIPLS is typically placed before a loop to bypass it if the loop count at run time does not indicate any iterations Some programming rules apply to the use of this instruction If no loops are enabled this instruction is undefined Register Address Bit Name Description SR 30 27 LF 3 0 Determines which loop is act...

Page 701: ...KIPLS label 2 1 41 Note 1 If LC 1 the instruction takes 1 cycle If LC 0 and the branch is taken the instruction takes 4 cycles 4 0 0 1 0 0 0 0 1 A A A 0 0 0 1 1 1 0 0 A A A A A A A A A A A A a displacement aAAAAAAAAAAAAAAA0 16 bit signed PC relative displacement The encoding is the displacement with bit 0 stripped and replaced by the sign bit ...

Page 702: ... the external interrupt request pins A low level is applied to the RESET_B signal A low level is applied to the EE0 debug signal A JTAG debug request command is made Any of these actions causes the core to exit the STOP processing state as follows If STOP is exited by assertion of the RESET signal the processor enters the reset processing state If STOP is exited in parallel with an external interr...

Page 703: ...r Dn Register Address Bit Name Description SR 2 SM If set selects 32 bit arithmetic saturation mode SR 5 4 S 1 0 Scaling mode bits determine which bits in the result are used in the Ln bit calculation Register Address Bit Name Description SR 0 C Calculates the borrow and updates the carry bit in the status register EMR 2 DOVF Set if the result cannot be represented in 40 bits or if the result satu...

Page 704: ...0 0000 Register Memory Address Before After D0 FF D000 0000 D1 00 2000 0000 SR 00E4 0020 00E4 0021 L2 D2 1 00 5000 0000 EMR 0000 0000 Instruction Words Cycles Type Opcode 15 8 7 0 SUB u5 Dn 1 1 1 0 1 1 1 0 F F F 1 1 i i i i i 15 8 7 0 SUB Da Db Dn 1 1 1 0 1 0 1 1 F F F 0 0 J J J J J 15 8 7 0 SUB Db Da Dn 1 1 1 0 1 0 1 1 F F F 0 1 J J J J J 15 8 7 0 SUB Da Da Dn 1 1 1 0 1 0 0 0 F F F 1 1 0 0 1 j j ...

Page 705: ...5 11101 D2 D3 00110 D1 D6 01110 D3 D6 10110 D4 D6 11110 D6 D6 00111 D1 D7 01111 D3 D7 10111 D4 D7 11111 D6 D7 Notes 1 This instruction can specify D8 D15 as operands by using a prefix 2 The order of source operands specifies the opcode for subtract operations 3 The JJJJJ encoding does not include the pairs D1 D1 D3 D3 D5 D5 and D7 D7 These are covered in the jj encoding 00 D1 D1 01 D3 D3 10 D5 D5 ...

Page 706: ...forms a 32 bit subtraction of source register Da from Dn with borrow disabled between bits 15 and 16 so that the high and low words of each register are subtracted separately The result is stored back in Dn The extension byte of the result is undefined Register Address Bit Name Description Ln L Clears the Ln bit in the destination register Register Memory Address Before After D0 00 0003 2A14 L1 D1...

Page 707: ... Data Register Instruction Words Cycles Type Opcode 15 8 7 0 SUB2 Da Dn 1 1 2 1 1 0 1 0 0 F F F 1 0 0 1 J J J 000 D0 010 D2 100 D4 110 D6 001 D1 011 D3 101 D5 111 D7 Note This instruction can specify D8 D15 as operands by using a prefix 000 D0 010 D2 100 D4 110 D6 001 D1 011 D3 101 D5 111 D7 Note This instruction can specify D8 D15 as operands by using a prefix ...

Page 708: ...he stack pointer is the destination operand then the immediate value must be a multiple of eight since the resulting 3 LSBs are forced to zero SUBA rx Rx Subtracts one AGU register rx from another Rx and stores the result in the destination AGU register Rx If the stack pointer is the destination operand then the value in rx must be a multiple of eight since the resulting 3 LSBs are forced to zero ...

Page 709: ...2 1 1 1 0 R R R R 0 0 1 1 r r r r 0000 N0 0100 1000 R0 1100 R4 0001 N1 0101 1001 R1 1101 R5 0010 N2 0110 PC 1010 R2 1110 R6 0011 N3 0111 SP 1011 R3 1111 R7 Note This instruction can specify R8 R15 as operands by using a high register prefix 0000 N0 0100 1000 R0 1100 R4 0001 N1 0101 1001 R1 1101 R5 0010 N2 0110 1010 R2 1110 R6 0011 N3 0111 SP 1011 R3 1111 R7 Note This instruction can specify R8 R15...

Page 710: ... mode SR 5 4 S 1 0 Scaling mode bits determine which bits in the result are used in the Ln bit calculation Register Address Bit Name Description SR 0 C Calculates the borrow and updates the carry bit in the status register EMR 2 DOVF Set if the MS bit of the result cannot be represented in 40 bits or saturates to 32 bits in arithmetic saturation mode or the MS bit of the result changed due to the ...

Page 711: ...emory Address Before After D0 00 0000 000A L1 D1 0 00 0000 0004 0 FF FFFF FFFE SR 00E4 0000 00E4 0001 Instruction Words Cycles Type Opcode 15 8 7 0 SUBL Da Dn 1 1 1 0 1 1 0 0 F F F 1 0 1 1 J J J 000 D0 010 D2 100 D4 110 D6 001 D1 011 D3 101 D5 111 D7 Note This instruction can specify D8 D15 as operands by using a prefix 000 D0 010 D2 100 D4 110 D6 001 D1 011 D3 101 D5 111 D7 Note This instruction ...

Page 712: ...o form a 32 bit operand The carry bit is not affected by this instruction Register Address Bit Name Description SR 2 SM If set selects 32 bit arithmetic saturation mode SR 5 4 S 1 0 Scaling mode bits determine which bits in the result are used in the Ln bit calculation Register Address Bit Name Description EMR 2 DOVF Set if the result cannot be represented in 40 bits or if the result saturates to ...

Page 713: ...tion Data Register Instruction Words Cycles Type Opcode 15 8 7 0 SUBNC W s16 Dn 2 1 4 0 0 1 1 1 1 0 0 i i i 1 0 F F F 1 0 0 i i i i i i i i i i i i i 000 D0 010 D2 100 D4 110 D6 001 D1 011 D3 101 D5 111 D7 Note This instruction can specify D8 D15 as operands by using a prefix s16 iiiiiiiiiiiiiiii 16 bit signed immediate data ...

Page 714: ...7 0 Dn 7 0 Da 7 Dn 39 8 SXT B Da Dn Da 15 0 Dn 15 0 Da 15 Dn 39 16 SXT W Da Dn Dn 31 Dn 39 32 SXT L Dn SXT B Da Dn Sign extends a byte from a source data register Da 7 0 into a destination data register Dn SXT W Da Dn Sign extends a word from a source data register Da 15 0 into a destination data register Dn SXT L Dn Sign extends a long word from a source data register Dn 31 0 into a destination d...

Page 715: ... 8E60 6EC6 0 FF 8E60 6EC6 Instruction Words Cycles Type Opcode 15 8 7 0 SXT B Da Dn 1 1 1 0 1 1 0 1 F F F 1 1 0 0 J J J 15 8 7 0 SXT W Da Dn 1 1 1 0 1 1 0 1 F F F 1 1 1 0 J J J 15 8 7 0 SXT L Dn 1 1 1 0 1 0 0 1 F F F 1 1 0 0 0 0 1 000 D0 010 D2 100 D4 110 D6 001 D1 011 D3 101 D5 111 D7 Note This instruction can specify D8 D15 as operands by using a prefix 000 D0 010 D2 100 D4 110 D6 001 D1 011 D3 ...

Page 716: ...3 r1 Example 2 sxta w r3 Operation Assembler Syntax rx 7 0 Rx 7 0 rx 7 Rx 31 8 SXTA B rx Rx Rx 15 Rx 31 16 SXTA W Rx SXTA B rx Rx Sign extends a byte from a source AGU register rx 7 0 into a destination AGU register Rx SXTA W Rx Sign extends a word from a source AGU register Rx 15 0 into a destination AGU register Rx Register Address Bit Name Description SR 18 EXP Determines which stack pointer is...

Page 717: ... 8 7 0 SXTA W Rx 1 1 2 1 1 1 0 R R R R 1 1 1 1 1 0 0 1 0000 N0 0100 1000 R0 1100 R4 0001 N1 0101 1001 R1 1101 R5 0010 N2 0110 PC 1010 R2 1110 R6 0011 N3 0111 SP 1011 R3 1111 R7 Note This instruction can specify R8 R15 as operands by using a high register prefix 0000 N0 0100 1000 R0 1100 R4 0001 N1 0101 1001 R1 1101 R5 0010 N2 0110 1010 R2 1110 R6 0011 N3 0111 SP 1011 R3 1111 R7 Note This instructi...

Page 718: ...register Da to a destination data register Dn The Ln bit is re calculated not copied in the destination register Saturation mode is ignored and no saturation is done Register Address Bit Name Description SR 5 4 S 1 0 Scaling bits determine which bits in the result are used in the Ln bit calculation Register Address Bit Name Description Ln L Calculates and updates the Ln bit in the destination regi...

Page 719: ...le Source Destination Data Register Instruction Words Cycles Type Opcode 15 8 7 0 TFR Da Dn 1 1 1 0 1 1 0 1 F F F 1 0 1 0 J J J 000 D0 010 D2 100 D4 110 D6 001 D1 011 D3 101 D5 111 D7 Note This instruction can specify D8 D15 as operands by using a prefix 000 D0 010 D2 100 D4 110 D6 001 D1 011 D3 101 D5 111 D7 Note This instruction can specify D8 D15 as operands by using a prefix ...

Page 720: ... rx to a destination AGU register Rx Register Address Bit Name Description SR 18 EXP Determines which stack pointer is used when the stack pointer is an operand Otherwise the instruction is not affected by SR Register Memory Address Before After R0 1234 5678 R1 1234 5678 Instruction Words Cycles Type Opcode 15 8 7 0 TFRA rx Rx 1 1 2 1 1 1 0 R R R R 1 1 1 0 r r r r 0000 N0 0100 1000 R0 1100 R4 0001...

Page 721: ... Rx RRRR AGU Source Destination Register 0000 N0 0100 1000 R0 1100 R4 0001 N1 0101 1001 R1 1101 R5 0010 N2 0110 1010 R2 1110 R6 0011 N3 0111 SP 1011 R3 1111 R7 Note This instruction can specify R8 R15 as operands by using a high register prefix ...

Page 722: ... the inactive other stack pointer OSP to an address register Rn If EXP SR 18 is set then OSP is the normal stack pointer NSP Otherwise OSP is the exception stack pointer ESP TFRA Rn OSP Writes the contents of an address register Rn to the inactive other stack pointer OSP If EXP SR 18 is set then OSP is the normal stack pointer NSP Otherwise OSP is the exception stack pointer ESP Note The value in ...

Page 723: ... Memory Address Before After SR 00E40000 R0 2A33217B NSP 2A332178 Instruction Words Cycles Type Opcode 15 8 7 0 TFRA OSP Rn 1 1 4 1 0 0 1 1 0 1 0 0 1 1 1 0 R R R 15 8 7 0 TFRA Rn OSP 1 1 4 1 0 0 1 1 0 1 0 0 1 1 1 1 R R R 000 R0 010 R2 100 R4 110 R6 001 R1 011 R3 101 R5 111 R7 Note If registers R8 R15 are accessed instead of R0 R7 a prefix is used ...

Page 724: ... then Da Dn TFRT Da Dn If T 0 then Da Dn TFRF Da Dn TFRT Da Dn Copies a source data register Da to a destination data register Dn if the T bit is set TFRF Da Dn Copies a source data register Da to a destination data register Dn if the T bit is cleared Register Address Bit Name Description SR 1 T True bit SR 5 4 S 1 0 Scaling bits determine which bits in the result are used in the Ln bit calculatio...

Page 725: ...rds Cycles Type Opcode 15 8 7 0 TFRT Da Dn 1 1 2 1 1 0 1 0 0 F F F 1 0 1 0 J J J 15 8 7 0 TFRF Da Dn 1 1 2 1 1 0 1 0 0 F F F 1 0 1 1 J J J 000 D0 010 D2 100 D4 110 D6 001 D1 011 D3 101 D5 111 D7 Note This instruction can specify D8 D15 as operands by using a prefix 000 D0 010 D2 100 D4 110 D6 001 D1 011 D3 101 D5 111 D7 Note This instruction can specify D8 D15 as operands by using a prefix ...

Page 726: ...code section pointed to from the exception table The term precise is defined such that the exception timing is guaranteed to be synchronous with the instruction execution The TRAP exception occurs immediately after the TRAP instruction The current state of the machine is saved by pushing the values of the SR and the next PC onto the exception stack with two simultaneous 32 bit long word memory acc...

Page 727: ...et SR 0 C Cleared SR 1 T Cleared SR 5 4 S 1 0 Cleared SR 31 SLF Cleared SR 30 27 LF 3 0 Cleared SR 23 21 I 2 0 Set interrupt priority level to 111 Register Memory Address Before After ESP 0000 8030 0000 8038 VBA 8000 0000 8034 00E0 0000 8030 0000 0014 PC 0000 0012 8000 0000 SR 00E0 0000 00E4 0000 Instruction Words Cycles Type Opcode 15 8 7 0 TRAP 1 5 4 1 0 0 1 1 1 1 0 0 1 1 1 1 1 1 0 ...

Page 728: ... then 1 T else 0 T TSTEQ Dn TSTEQ Dn Sets the T bit in SR if the source data register Dn is equal to zero otherwise it clears the T bit Register Address Bit Name Description SR 1 T Set if the source operand is equal to zero and cleared if the source operand is not equal to zero Register Memory Address Before After D1 00 0000 0000 SR 00E4 0000 00E4 0002 Instruction Words Cycles Type Opcode 15 8 7 0...

Page 729: ...then 1 T else 0 T TSTEQA L Rx TSTEQA W Rx Tests only the lower word bits 15 0 of the source operand TSTEQA L Rx Tests all 32 bits of the source operand Register Address Bit Name Description SR 18 EXP Determines which stack pointer is used when the stack pointer is an operand Otherwise the instruction is not affected by SR Register Address Bit Name Description SR 1 T Set if the source operand is eq...

Page 730: ...on Words Cycles Type Opcode 15 8 7 0 TSTEQA W Rx 1 1 2 1 1 1 0 R R R R 1 1 1 1 0 0 0 0 15 8 7 0 TSTEQA L Rx 1 1 2 1 1 1 0 R R R R 1 1 1 1 0 0 0 1 0000 N0 0100 1000 R0 1100 R4 0001 N1 0101 1001 R1 1101 R5 0010 N2 0110 1010 R2 1110 R6 0011 N3 0111 SP 1011 R3 1111 R7 Note This instruction can specify R8 R15 as operands by using a high register prefix ...

Page 731: ...STGE Dn Sets the T bit if the source data register Dn is greater than or equal to zero otherwise clears the T bit The value in Dn is treated as a signed number Register Address Bit Name Description SR 1 T Set if the source operand is greater than or equal to zero and cleared if the source operand is not greater than or equal to zero Register Memory Address Before After D4 00 5F3E 05C2 SR 00E4 0000...

Page 732: ...U register Rx is greater than or equal to zero otherwise it clears the T bit The value in Rx is treated as a signed number Register Address Bit Name Description SR 18 EXP Determines which stack pointer is used when the stack pointer is an operand Otherwise the instruction is not affected by SR Register Address Bit Name Description SR 1 T Set if the source operand is greater than or equal to zero a...

Page 733: ...estination Register Instruction Words Cycles Type Opcode 15 8 7 0 TSTGEA L Rx 1 1 2 1 1 1 0 R R R R 1 1 1 1 0 0 1 1 0000 N0 0100 1000 R0 1100 R4 0001 N1 0101 1001 R1 1101 R5 0010 N2 0110 1010 R2 1110 R6 0011 N3 0111 SP 1011 R3 1111 R7 Note This instruction can specify R8 R15 as operands by using a high register prefix ...

Page 734: ...n 0 then 1 T else 0 Τ TSTGT Dn TSTGT Dn Sets the T bit if the source data register Dn is greater than zero otherwise clears the T bit Register Address Bit Name Description SR 1 T Set if the source operand is greater than zero and cleared if the source operand is not greater than zero Register Memory Address Before After L6 D6 1 80 0000 0000 SR 00E4 0002 00E4 0000 Instruction Words Cycles Type Opco...

Page 735: ...ress Bit Name Description SR 18 EXP Determines which stack pointer is used when the stack pointer is an operand Otherwise the instruction is not affected by SR Register Address Bit Name Description SR 1 T Set if the source operand is greater than zero and cleared if the source operand is not greater than zero Register Memory Address Before After R2 46EA 2BE8 SR 00E4 0000 00E4 0002 Instruction Word...

Page 736: ...eanings in big and little endian modes as follows Operation Assembler Syntax If VF2 1 then D3 L 1 1 word 3 else D1 L 1 1 word 3 If VF0 1 then D3 L 1 word 2 else D1 L 1 word 2 D2 L word 0 D6 L word 1 VSL 4W D2 D6 D1 D3 Rn N0 If VF3 1 then D3 H 1 1 word 3 else D1 H 1 1 word 3 If VF1 1 then D3 H 1 word 2 else D1 H 1 word 2 D2 H word 0 D6 H word 1 VSL 4F D2 D6 D1 D3 Rn N0 If VF2 1 then D3 L 1 1 word 1...

Page 737: ...ion of the first two words in the memory the order of which depends on the endian mode The next two words that are written are 1 A left shifted value of D1 H or D3 H according to the Viterbi flag VF1 If the Viterbi flag VF1 is set then the left shifted D3 H is chosen Otherwise the left shifted D1 H is chosen and the LSB is filled with zero 2 A left shifted value of D1 H or D3 H according to the Vi...

Page 738: ...0 R7 SR 8 VF0 Viterbi flag 0 set by MAX2VIT D4 D2 SR 9 VF1 Viterbi flag 1 set by MAX2VIT D4 D2 SR 10 VF2 Viterbi flag 2 set by MAX2VIT D0 D6 SR 11 VF3 Viterbi flag 3 set by MAX2VIT D0 D6 EMR 16 BEM Set if big endian mode cleared if little endian mode Register Memory Address Before After Little Endian After Big Endian MCTL 0000 0000 SR 00e4 0000 D1 00 2A62 EA79 D3 00 5437 9EAC N0 0000 0002 R0 0000 ...

Page 739: ...1 0 1 0 0 0 0 0 0 R R R D2 D6 D1 D3 Rn N0 15 8 7 0 VSL 4F 1 1 2 1 1 0 0 1 0 1 0 0 0 0 1 0 R R R D2 D6 D1 D3 Rn N0 15 8 7 0 VSL 2W D1 D3 Rn N0 1 1 2 1 1 0 0 1 0 1 0 0 0 1 0 0 R R R 15 8 7 0 VSL 2F D1 D3 Rn N0 1 1 2 1 1 0 0 1 0 1 0 0 0 1 1 0 R R R 000 R0 010 R2 100 R4 110 R6 001 R1 011 R3 101 R5 111 R7 Note This instruction can specify R8 R15 as operands by using a high register prefix ...

Page 740: ...e when data is available for processing The WAIT instruction can appear only once in an execution set During the WAIT processing state if a maskable interrupt is asserted the core behaves according to the following rules Condition Response The priority level of the interrupt is higher than the level programmed in the SR by the IPLn bits and the DI bit in SR is clear meaning the interrupt is enable...

Page 741: ...Affect Instruction Status and Conditions Changed by Instruction None Instruction Formats and Opcodes Register Address Bit Name Description SR 18 EXP Determines execution working mode Instruction Words Cycles Type Opcode 15 8 7 0 WAIT 1 8 4 1 0 0 1 1 1 1 1 0 1 1 1 1 0 0 0 ...

Page 742: ...Dn ZXT B Da Dn Copies bits 7 0 from a source data register Da to a 40 bit destination data register Dn and zero extends bits 39 8 of Dn ZXT W Da Dn Copies bits 15 0 from a source data register Da to a 40 bit destination data register Dn and zero extends bits 39 16 of Dn ZXT L Dn Zero extend a long word from bit 32 through the remaining upper bits in a 40 bit data register Dn Register Address Bit N...

Page 743: ...C4 0 00 A836 A7C4 Instruction Words Cycles Type Opcode 15 8 7 0 ZXT B Da Dn 1 1 1 0 1 1 0 1 F F F 1 1 0 1 J J J 15 8 7 0 ZXT W Da Dn 1 1 1 0 1 1 0 1 F F F 1 1 1 1 J J J 15 8 7 0 ZXT L Dn 1 1 1 0 1 0 0 1 F F F 1 1 0 0 0 0 0 000 D0 010 D2 100 D4 110 D6 001 D1 011 D3 101 D5 111 D7 Note This instruction can specify D8 D15 as operands by using a prefix 000 D0 010 D2 100 D4 110 D6 001 D1 011 D3 101 D5 1...

Page 744: ...ation Assembler Syntax rx 7 0 Rx 7 0 0 Rx 31 8 ZXTA B rx Rx 0 Rx 31 16 ZXTA W Rx ZXTA B rx Rx Copies bits 7 0 from a source AGU register rx to a 32 bit destination AGU register Rx and zero extends bits 31 8 of Rx ZXTA W Rx Zero extends bits 31 16 of Rx Register Address Bit Name Description SR 18 EXP Determines which stack pointer is used when the stack pointer is an operand Otherwise the instructi...

Page 745: ... 8 7 0 ZXTA W Rx 1 1 2 1 1 1 0 R R R R 1 1 1 1 1 0 0 0 0000 N0 0100 1000 R0 1100 R4 0001 N1 0101 1001 R1 1101 R5 0010 N2 0110 PC 1010 R2 1110 R6 0011 N3 0111 SP 1011 R3 1111 R7 Note This instruction can specify R8 R15 as operands by using a high register prefix 0000 N0 0100 1000 R0 1100 R4 0001 N1 0101 1001 R1 1101 R5 0010 N2 0110 1010 R2 1110 R6 0011 N3 0111 SP 1011 R3 1111 R7 Note This instructi...

Page 746: ...A 432 SC140 DSP Core Reference Manual ZXTA x ...

Page 747: ...4 lsr d4 shifts right 1 bit and 0 d4 h clears high portion and 007f d4 l clears bits 15 7 leaves the SCID in data register d4 The SCID has three fields REVNO bits 23 21 instruction set version RESERVED bit 20 0 in Freescale implementations CORETP bits 19 17 core architecture version The REVNO field generally identifies the basic instruction set revision of the SC100 core It identifies the availabi...

Page 748: ...ill produce the same results on a higher REVNO except where the higher REVNO introduces a bug fix to an existing instruction These bug fixes may present software migration and tools issues For the same REVNO software written for a lower CORETP may not run on a higher CORETP because CORETP is not a monotonic scalability index A higher CORETP may have more or less execution units and VLES grouping c...

Page 749: ...2 64 ALU arithmetic logic unit 1 3 2 2 AM address modification bits 2 37 AM bits 2 45 AND A 40 A 43 AND W A 45 Arithmetic instructions on address registers 2 48 Arithmetic saturation mode 2 25 bit 3 6 ASL A 48 ASL2A A 50 ASLA A 51 ASLL A 52 ASLW A 55 ASR A 57 ASRA A 59 ASRR A 60 ASRW A 63 ATS access type selection 4 56 4 60 AWS access width selection 4 59 B B0 B7 base address registers 2 36 BEM bi...

Page 750: ...2 8 Data shifter limiter 2 13 DEBUG A 137 Debug exception 4 12 Debug mode 4 11 DEBUGERST debugger status information 4 42 DEBUGEV A 138 Debugging system 4 1 DECA A 139 DECEQ A 141 DECEQA A 143 DECGE A 144 DECGEA A 146 DI A 148 DI disable interrupts bit 3 4 DIS debug interrupt status 4 42 DIV A 150 Division 2 20 DMA direct memory access 1 4 DMAC implementation 2 26 DMACSS A 153 DMACSU A 155 DOENn A...

Page 751: ...an support 2 56 bit mask instructions 2 67 change of flow instructions 2 68 control instructions 2 68 data moves 2 58 data transfer 2 59 instruction word transfers 2 62 memory access behavior 2 64 multi register transfer 2 61 stack support instructions 2 67 EOnCE 1 3 EOnCE enhanced on chip emulator 1 3 2 5 4 1 4 10 command registers ECR 4 36 dedicated instructions 4 11 EE pins 4 18 internal archit...

Page 752: ...de of operation 4 51 EXTRACT A 171 EXTRACTU A 173 G GO go command 4 37 GP6 0 general purpose flags 3 8 Grouping 5 5 assembly reordering rules 5 12 conditional execution 5 9 general 5 5 mechanism 5 6 prefix words 5 7 types of prefix 5 7 serial non prefix 5 7 Grouping Mechanism 5 6 I I2 0 interrupt mask bits 3 3 IADDNC W A 175 IFc A 176 ILIN illegal instruction 3 9 ILLEGAL A 178 ILST illegal executi...

Page 753: ...175 IFc A 176 ILLEGAL A 178 IMAC A 180 IMACLHUU A 183 IMACUS A 185 IMPY A 187 IMPY W A 189 IMPYHLUU A 191 IMPYSU A 193 IMPYUU A 195 INC A 197 INC F A 199 INCA A 201 INSERT A 203 JF A 205 JFD A 207 JMP A 209 JMPD A 211 JSR A 213 JSRD A 215 JT A 217 JTD A 219 LPMARKx A 221 LSLL A 224 LSR A 226 LSRA A 227 LSRR A 228 LSRW A 231 MAC A 233 MACR A 236 MACSU A 239 MACUS A 241 MACUU A 243 MARK A 245 MAX A ...

Page 754: ...nstructions 6 63 Programming rules 6 67 working with a single ISAP 6 58 working with data and memory 6 60 Working with multiple ISAPs 6 59 J JF A 205 JFD A 207 JMP A 209 JMPD A 211 JSR A 213 JSRD A 215 JT A 217 JTAG 5 44 5 45 JTAG access 4 33 JTAG and EOnCE interface 4 2 JTAG interface pins 4 2 JTD A 219 L LF3 0 loop flags 3 0 3 2 Linear addressing mode 2 45 Loop looping rules 5 32 nested loop 5 3...

Page 755: ...gram address generator 2 5 PC program counter 1 3 2 5 PC relative addressing modes 2 40 PC relative mode 2 40 PC_DETECT PC breakpoint detection register 4 49 PC_EXCP PC of the exception execution set 4 49 PC_LAST PC of last execution set 4 49 PC_NEXT PC of the next execution set 4 49 PCKILL PC killed 4 38 PCU program control unit 2 5 PDB program data bus 2 1 PDU program dispatch unit 2 5 Pipeline ...

Page 756: ...VF3 0 3 4 SRAM static random access memory 1 2 Stack pointer registers 2 4 Stack support 5 32 fast call return from subroutines 5 36 instructions 2 67 normal and exception modes 5 32 shadow stack pointer registers 5 35 STOP A 388 Stop processing state 5 45 SUB A 389 SUB2 A 392 SUBA A 394 SUBL A 396 SUBNC W A 398 SWDIS software access disable 4 42 SXT x A 400 SXTA x A 402 T T true bit 3 6 TB_BUFF t...

Page 757: ... TSTEQ A 414 TSTEQA x A 415 TSTGE A 417 TSTGEA L A 418 TSTGT A 420 TSTGTA A 421 Two s complement rounding 2 23 U Unsigned arithmetic 2 20 Unsigned integer data format 2 19 Unsigned multiplication 2 20 V VF3 0 Viterbi flags 3 0 3 4 Viterbi decoding support 2 30 VLES variable length execution set 1 2 VSL A 422 W WAIT A 426 Wait processing state 5 44 X XABA and XABB data memory address buses 2 1 XDBA...

Page 758: ...I 10 Index ...

Page 759: ...SC140 DSP Core Reference Manual i ...

Page 760: ......

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