CPC1302 User Manual
0-32
Description of operation of CPC1302 major components
CPC1302
Control Register (Base+1)
Bit
number
Name
Type
Descriptio
n
7
MEN
R/W
Start/reset of controller. Writing "1" to this bit switches on the I2C controller.
Writing "0" to this bit resets and switches off the I2C controller.
6
MIEN
R/W
Interrupt activation Writing "1" to this bit enables interrupt. Interrupt occurs when
MIF bit is set in the Status Register.
5
MSTA
R/W
Start of the transaction. Writing "1" to this bit calls the Start condition and
transmit\receive condition, depending on the MTX bit setting. Writing "0" to this
bit calls the Stop condition. Where there is no acknowledgement of (RXAK=1) of
the transmit transaction, the bit will automatically reset to "0" and the Stop
Condition will be initiated.
4
MTX
R/W
Selection of transaction mode. Writing "1" to this bit sets the transmission
mode, writing "0"
– to receipt mode.
3
TXAK
R/W
Reception transaction acknowledgement bit. Writing "0" to this bit performs
acknowledgement (ACK), writing "1"
– no acknowledgement is performed.
2
RSTA
R/W
Restart. Writing "1" to this bit calls the Repeated Start Condition. The bit is
automatically reset to "0" upon completion of the Repeated Start Condition.
1
-
Reserved
0
-
Reserved
Data Register (Base+2)
Bit
number
Name
Type
Descriptio
n
7-0
R/W
Data for transfer mode during recording or data of receipt mode during
reading.
GPIO Register (Base+3)
Bit
number
Name
Type
Descriptio
n
7-4
GPO
R/W
Values of output signals GPO[3:0].
3-0
GPI
R
Values of input signals GPO[3:0].
