CPC1302 User Manual
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Description of operation of CPC1302 major components
CPC1302
2.9.2 Registers of I2C controller
Input/output address
Type
HARD RESET
Configuration register
Base+0
R/W
00h
Status Register
Base+1
R/W
00h
Control Register
Base+2
R/W
00h
Data Register
Base+3
R/W
0xh
GPIO Register
2.9.3 Description of I2C controller registers
Status Register (Base+0)
Bit
number
Name
Type
Descriptio
n
7
MCF
R/W
Flag of transaction ending / continuation.
Is set to "1" after acknowledgement (ACK) condition and STOP Condition of the
transaction.
For start of the next transaction it should be reset by writing "1" to this bit.
6
-
Reserved
5
MBB
R
Bus busy flag. Is set to "1" if the START condition was recorded and is
reset to "0" if the STOP condition was recorded.
4
MAL
R/W
Flag of the bus arbitration loss. Is set to "1" at bus arbitration loss (in
START/STOP/Transmit conditions). Should be reset by writing "1" to this bit.
3
-
Reserved
2
-
Reserved
1
MIF
R/W
Interrupt flag. Is installed in the "1" under condition of MCF="1" or MAL="1".
Interrupt occurs when MIEN bit is set in the Control Register should be reset by
writing "1" to this bit.
0
RXAK
R
Flag of transaction acknowledgement (ACK). This will be reset to "0" if ACK was
obtained, and will be set to "1" if ACK wasn't obtained. Where there is no
acknowledgement of (RXAK=1) of the transmit transaction, MSTA bit will be
automatically reset to "0" and the Stop Condition will be initiated.
