CPC1302 User Manual
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Description of operation of CPC1302 major components
CPC1302
2.7 FRAM
controller registers
FRAM controller is implemented in FPGA as a device on LPC bus. Controller is activated in
BIOS Setup. The device is operated via registers in the field of input-output (I/O) ports. Base
register address (BASE), set in BIOS, is specified in "Help" section of BIOS Setup, to the right side
of the item dedicated to activation/deactivation of FRAM controller.
INDEX
Input/output
address
Type
HARD RESET
Configuration register
Base+0
R/W
00h
FRAM address value [7:0]
Base+1
R/W
00h
FRAM address value [14:8]
Base+2
R/W
00h
SPI data value [7:0]
Base+3
R/W
00h
SPI Control/Status register
[7]
– busy status
[6]
– last 1K FRAM lock
status [5:1]
– Reserved
[0]
– BURST mode
The controller automatically generates the sequence of access to FRAM on SPI bus
(address from registers BASE+0, BASE+1, write/ read mode and data
– register BASE+2).
The las kilobyte from 32 Kbyte is backed up for storing the BIOS Setup settings. Bit <0> in
the control register (Base+3) includes the mode of automatic increase of address during
reading/writing of data register (base+2), upon completion of the packet exchange it should be
reset.
Programming SPI devices
Work with FRAM is carried out in the field of I/O at the addresses, specified in BIOS Setup. The
example shows base address 310H.
▪ Writing data byte (32h) to FRAM at the address (144h)
MOV
DX, 310H
MOV
AL, 44H
OUT
DX, AL
MOV
DX, 311H
MOV
AL, 01H
OUT
DX, AL
MOV
DX,
312h MOV
AL,
32h OUT
DX,AL
▪ Reading data byte from FRAM at the address (101h)
MOV
DX, 310H
MOV
AL, 01H
OUT
DX, AL
MOV
DX, 311H
MOV
AL, 10H
OUT
DX, AL
MOV
DX,
312h IN
AL,DX
