CPC1302 User Manual
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Description of operation of CPC1302 major components
CPC1302
Operation algorithm with watchdog timer via I/O registers:
1) The counter decrement is stopped.
2) Timeout value is recorded to the initial value registers.
3) Counter register is initiated by recording any number to the counter register. In this case, the
timeout value from the initial value register is overwritten to the counter register.
4) Start the counter for decrement and, if required, allow the board automatic reset.
5) After that, with a period of the lesser or equal timeout value we regularly perform counter reset
(using any of the methods described above). If the counter is not reset during the first timeout
interval
– TMF flag is set and interrupt will appear (if allowed), If the counter is not reset during the
second timeout interval
– STF flag is set and the board will reboot, if the reset was allowed.
2.8.1 Watchdog timer's registers
Input/output address
Type
HARD RESET
Configuration register
Base+0
R/W
Timer current value [7:0]
Base+1
R/W
Timer current value [15:8]
Base+2
R/W
Timer current value [23:16]
Base+3
R/W
00h
Timer initial value [7:0]
Base+4
R/W
40h
Timer initial value [15:8]
Base+5
R/W
00h
Timer initial value [23:16]
Base+6
R/W
00h
Status register
Base+7
R/W
00h
Control register
