Endace DAG 3.7D, User Manual

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EDM01-06: DAG 3.7D Card User Guide
©2006 2 Version 1: March 2006
Card
Description
The DAG cards are PCI-bus cards designed for cell and packet capture and
generation on IP networks.
The DAG 3.7D card has dual DS3/E3 co-axial interface, both receive and
transmit and is shown below:
Card
Architecture
Description
Because of component close association, packets or cells are time-stamped
accurately. Time stamped packet records are stored in the FPGA, which
interfaces to the PCI bus.
All packet records are written to host PC memory during capture
operations.
Serial PDH data is received by the DAG 3.7D card co-axial interfaces, and
fed into dual DS3/E3 framer.
Network data is then fed to the FPGA which also contains the DUCK
timestamp engine. The close association of these two components means
that packets or cells can be time-stamped very accurately.