EDM01-06: DAG 3.7D Card User Guide
©2006
3
Version 1: March 2006
Card
Architecture
(cont.)
The diagram below shows the DAG 3.7D card major components and
process flow.
Time stamped packet or cell records are stored in a FIFO.
The DAG 3.7D can demap either ADM (ATM Direct Mapped) ATM cells,
PLCP (Payload Layer Convergence Protocol) ATM cells, PPP
encapsulations, HDLC (High-Level Data Link Control) and Frame Relay.
The DAG3.7D also supports subrate DS3 for Kentrox data encapsulation
formats but requires a specific image to do so. Please contact Endace
Customer Support at
for more information.
Records are then transferred from the FIFO into the FPGA, which has
interfaces to the PCI bus.
The current firmware only supports bit synchronisations HDLC
demapping.
Extended
Functions
The functionality of the DAG 3.7D card can be extended in many ways. A
physical transmit path is provided on the card so that packet organisation is
possible, requiring special firmware images.
The framer is normally set up to map DS3 payloads, but other mappings are
possible.
To discuss the use of other extended features contact the Endace customer
support team at
Summary of Contents for DAG 3.7D
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Page 13: ...EDM01 06 DAG 3 7D Card User Guide 2006 7 Version 1 March 2006...
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