EMC-PARTNER CDN2000-06-25, User Manual

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CDN2000-06-25 coupling decoupling network
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Generators to carry out combination wave tests
Figure: 1.0.3-1
Legend:
RL Charging resistor Cs Impulse capacitor S High voltage switch
RE1 Discharge resistor Ls Inductance of the generator Rs Serial resistor
RM Shunt RE2 Discharge resistor TM1 Divider
Lv Inductance of the connection MS Measurement equipment TM2 Divider
A dc source charges the capacitors within the different modules via the charging resistors. Closing the
switch S discharge the capacitors into the parallel branches RE1, RE2 and EUT. When the EUT has a high
impedance the CWG generates a voltage rise defined by the serial inductance Ls and by the parallel
resistor RE2. The half value time is determined by Cs and the both RE1 // RE2. When the EUT has a low
impedance the generated current is determined by the elements Cs, Ls, Rs and the EUT.
The current and voltage waveforms are defined in IEC 61000-4-5 as follows:
Waveshapes and tolerances
Current into short circuit Voltage at no load Figure: 1.0.1-2
The waveforms are verified in open circuit (voc) and short circuit (isc). No load limitation exists, because for
different load impedance (EUT) the waveforms are within the open circuit voltage waveform and the short
circuit current waveform.
Rise time:
Ts=8 µs ± 20%
Half value time:
Tr = 20 µs ± 20%
Under swing :
ü < 30 %
90%
50%
10%
100%
Test generator CWG
I
[A]
EUT, e.g. Motors
U
[V]
100%
50%
20 µs
8 µs
Ü<30%
50 µs
1,2 µs
Rise time:
Ts=1,2 µs ± 30%
Half value time:
Tr = 50 µs ± 20%
Over swing :
ü < 5 %
90%
S