LPT-11 Transceiver-based Device Checklist
LPT-11 Transceiver and Neuron Chip Connections
Item Check
When
Completed
Description
1
Transceiver pins connected as shown in table 2.1 and figure
2.1
2
The recommended number and placement of 0.1µF bypass
capacitors are near the Neuron Chip. See the appropriate
Neuron Chip Databook from Toshiba or Cypress, or the FT
31xx Smart Transceiver Databook from Echelon, as
appropriate.
Note: No more than 1.0µF of total decoupling
capacitance can be connected to Vcc.
3
The Neuron Chip and transceiver input clock frequency is
≥
5MHz and accurate to at least ±200ppm for compatibility
with the L
ON
M
ARK
TP/FT-10 channel. Use of a 2.5MHz
clock frequency is possible with the LPT-11 transceiver, but
it is not compatible with the L
ON
M
ARK
TP/FT-10 channel.
4
If required, a Low Voltage Interrupt (LVI) circuit with open
collector output (such as the Motorola MC33064) is used to
supply a reset signal to the Neuron Chip. See the
appropriate
Neuron Chip Databook
for details on when an
LVI is needed.
LPT-11 PCB Layout
Item Check
When
Completed
Description
5
The network connector, LPT-11 Transceiver SIP, and DC-DC
converter components L1, C1, and C2 are placed close
together, following the general layout guidelines of figure 2.2.
6
The traces that carry moderate DC-DC switching currents are
wide and short (the V+ and INDUCTOR nets).
7
The Neuron Chip and transceiver SIP are placed adjacent to
one another on the same PCB, following the general layout
guidelines of figure 2.2.
8
CLK2 from Neuron Chip is connected to the SIP's CLK pin
via a trace that is
≤
2cm (0.8”) long.
C-2 Appendix C - Checklist