in figure 2.2 are spaced as closely together as possible in order to minimize their loop
area. Circuits that are sensitive to electric field noise should be kept away from L1
and pin 4 of the transceiver, and ground guarding should be employed to shield them
from the electric field noise.
The +5VDC Vcc trace and GROUND trace are shown leading away from the
transceiver into the general board area for the Neuron Chip and application circuit.
The Vcc and GROUND should be routed directly off the C2 capacitor to the device's
circuitry, as shown. The ground guarding around the network connector should not
be used as a source of ground for the digital circuitry. C3 is a small 0.1µF decoupling
capacitor that should be placed near C2 to minimize switching noise.
The CLK input to the LPT-11 transceiver (pin 7) needs to be guarded by ground traces
to minimize clock noise, and to help keep EMI levels low (see Chapter 6). In general,
the
Neuron
3120 or 3150 Chip
should be placed close enough to the LPT-11 transceiver
and oriented correctly so that the CLK trace from the Neuron Chip to the transceiver
is no longer than 2cm. At the same time, the Neuron
Chip and any other fast digital
circuitry should be kept away from the network connector and NET_A/NET_B pins
(pins 1 and 2) on the transceiver. If noisy digital circuitry is located too close to the
network connector or wires, RF noise may couple onto the network cable and cause
EMI problems. With these constraints in mind, it is apparent that the best place to
locate the Neuron Chip is in the lower right corner of figure 2.2, with an orientation
that places the Neuron Chip’s CLK2 line closest to the transceiver's CLK input pin.
This position and orientation work well for both the Neuron
3120 and 3150 Chips,
since the CP lines are oriented near the lower portion of the LPT-11 transceiver for the
rest of the interconnections.
Choosing the Inductor and Capacitors for the LPT-11
Switching Power Supply
Parts that are chosen for L1, C1, and C2 must meet several key specifications to
ensure that the switching power supply conversion performed by the LPT-11
transceiver stays within specified limits. As long as these key specifications are met,
the designer of a link power device is free to choose parts that have other
specifications that best match the application. These specifications allow up to
100mA of sustained peak current to be drawn by the application, including the
Neuron Chip. Component selection for low-current applications is discussed in the
next section.
Suitable parts for inductor L1 are listed in table 2.3. L1 has the following key
specifications that must be met over the device's operating temperature range:
L = 1mH ±10%, DCR
≤
4
Ω
,
Isat
≥
200mA, Fres
≥
800KHz. Isat is defined as the DC
current at which the measured inductance has not fallen below 80% of its low
frequency value, e.g., 800µHenries at 800kHz.
L
ON
W
ORKS
LPT-11 Transceiver User’s Guide
2-7