• a common-mode ferrite choke can be used to help meet EMC requirements for
devices that have noisy application circuitry or special circuit requirements.
Note that it may be possible to design a two-layer 10MHz Neuron 3150 Chip-based
link power device that will pass level “B” in some applications, depending on the
mechanical configuration. Early testing of prototype circuits at an outdoor EMI
range should be used to determine the effectiveness of these EMC techniques in a
particular application.
ESD Design Issues
Electrostatic Discharge (ESD) is encountered frequently in industrial and
commercial use of electronic systems. Reliable system designs must consider the
effects of ESD and take steps to protect sensitive components. Static discharges
occur frequently in low-humidity environments when operators touch electronic
equipment. The static voltages generated by humans can exceed 10kV. Keyboards,
connectors, and enclosures provide paths for static discharges to reach ESD sensitive
components such as the Neuron Chip. This section describes techniques to design
ESD immunity into LPT-11 transceiver-based products. For a discussion of ESD
issues for the LPI-10 module, see the
L
ON
W
ORKS
LPI-10 Link Power Interface
Module User’s Guide
, part number 078-0104-01.
ESD testing is important to ensure that a link powered device and its network
connection can withstand real-world exposure to static discharges. In addition, the
European Community has adopted legal requirements for ESD testing of products.
Designing Systems for ESD Immunity
As with the EMI design issues discussed above, ESD hardening of link power devices
is different than hardening products that have an explicit earth ground connection.
If Cleak,
GND
can be kept small (say,
≤
5pF), and if the link power device is housed
inside a plastic enclosure that offers no access for ESD hits (as in an enclosed IR
motion sensor ), then ESD testing is fairly easy to pass. The current from static
discharges to the device's network connector will travel out the network cable, with
very little energy coupled into the device's circuitry.
In devices that have a larger Cleak,
GND
(up to about 20pF), more energy travels
from network connector ESD hits through the LPT-11 transceiver’s ESD protection
circuitry to logic ground, and from there to earth ground through Cleak,
GND
. In this
type of device, it is important to lay out the ground plane and ground guarding so
that the LPT-11 transceiver’s ground (pin 6) is connected directly to the largest
section of the ground plane without any sensitive circuitry in the path. When the
ESD hit is directed into logic ground by the LPT-11 transceiver, the transient
current can flow out to earth ground via Cleak,
GND
without causing disruptive
voltage bounces in other device circuitry.
ESD hits should not be allowed to reach a link power device's internal circuitry.
Adequate creepage and clearance distances should be built into each device's
enclosure to prevent discharges to anything other than the network wiring
L
ON
W
ORKS
LPT-11 Transceiver User’s Guide
6-5