Dynamic Engineering PMC-BISERIAL-III RL1 User Manual Download Page 29

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Embedded Solutions

Page 29 of 37

Loop-back

The Engineering kit has reference software, which includes external loop-back tests.
The PMC-BISERIAL-III RL1 has a 68 pin SCSI II front panel connector. The tests
require an external cable with the following pins connected.

Full-Duplex Loop-Back

Signal From To Signal

TX0 DATA+

pin 1

pin 2

RX0 DATA+

TX0 DATA-

pin 35

pin 36

RX0 DATA-

TX1 DATA+

pin 3

pin 4

RX1 DATA+

TX1 DATA-

pin 37

pin 38

RX1 DATA-

TX2 DATA+

pin 5

pin 6

RX2 DATA+

TX2 DATA -

pin 39

pin 40

RX2 DATA-

TX3 DATA+

pin 7

pin 8

RX3 DATA+

TX3 DATA-

pin 41

pin 42

RX3 DATA-

TX4 DATA+

pin 9

pin 10

RX4 DATA+

TX4 DATA-

pin 43

pin 44

RX4 DATA-

TX5 DATA+

pin 11

pin 12

RX5 DATA+

TX5 DATA-

pin 45

pin 46

RX5 DATA-

TX6 DATA+

pin 13

pin 14

RX6 DATA+

TX6 DATA -

pin 47

pin 48

RX6 DATA-

TX7 DATA+

pin 15

pin 16

RX7 DATA+

TX7 DATA-

pin 49

pin 50

RX7 DATA-

Half-Duplex Loop-Back

Signal From To Signal

TX/RX 0 DATA+

pin 1

pin 3

TX/RX 1 DATA+

TX/RX 0 DATA-

pin 35

pin 37

TX/RX 1 DATA-

TX/RX 2 DATA+

pin 5

pin 7

TX/RX 3 DATA+

TX/RX 2 DATA -

pin 39

pin 41

TX/RX 3 DATA-

TX/RX 4 DATA+

pin 9

pin 11

TX/RX 5 DATA+

TX/RX 4 DATA-

pin 43

pin 45

TX/RX 5 DATA-

TX/RX 6 DATA+

pin 13

pin 15

TX/RX 7 DATA+

TX/RX 6 DATA -

pin 47

pin 49

TX/RX 7 DATA-

Summary of Contents for PMC-BISERIAL-III RL1

Page 1: ...CA 95060 831 457 8891 Fax 831 457 4793 http www dyneng com sales dyneng com Est 1988 User Manual PMC BISERIAL III RL1 Eight Channel UART Interface PMC Module Revision A Corresponding Hardware Revision...

Page 2: ...escribed in this document at any time and without notice Furthermore Dynamic Engineering assumes no liability arising out of the application or use of the device described herein The electronic equipm...

Page 3: ...COUNT 21 RL1_CHAN_0 7_RD_DMA_PNTR 22 RL1_CHAN_0 7_RX_FIFO_COUNT 22 RL1_CHAN_0 7_FIFO 23 RL1_CHAN_0 7_TX_AMT_LVL 23 RL1_CHAN_0 7_RX_AFL_LVL 23 RL1_CHAN_0 7_TX_CONTROL 24 RL1_CHAN_0 7_RX_CONTROL 25 RL1_...

Page 4: ...mbedded Solutions Page 4 of 37 THERMAL CONSIDERATIONS 34 WARRANTY AND REPAIR 34 Service Policy 35 Out of Warranty Repairs 35 For Service Contact 35 SPECIFICATIONS 36 ORDER INFORMATION 37 SCHEMATICS 37...

Page 5: ...ORT 21 FIGURE 10 PMC BISERIAL III RL1 READ DMA POINTER REGISTER 22 FIGURE 11 PMC BISERIAL III RL1 RX FIFO DATA COUNT PORT 22 FIGURE 12 PMC BISERIAL III RL1 RX TX FIFO PORT 23 FIGURE 13 PMC BISERIAL II...

Page 6: ...for a copy of this specification It is assumed that the reader is at least casually familiar with this document and basic logic design FIGURE 1 PMC BISERIAL III BLOCK DIAGRAM The PMC BiSerial III is...

Page 7: ...nterface can operate at up to 10 Mbits second using a 160 MHz clock Data for all channels is sent and received LSB first using a low start bit and one or two high stop bits to separate data bytes An o...

Page 8: ...re selectively terminated with 100 The termination resistors are in two element packages to allow flexible termination options for custom formats and protocols Optional pull up pull down resistor pack...

Page 9: ...ansfer is from the PMC BiSerial III RL1 board to host memory and a 0 if the transfer is from memory to the board These bits are then replaced with zeros to determine the address of the next descriptor...

Page 10: ...ammable by writing values into the respective FIFO level registers Besides generating FIFO level status and potentially causing an interrupt these values can also be used to give DMA arbitration prior...

Page 11: ...d and the interrupt mask set The interrupt service routine can be configured to respond to the TX RX interrupts After an interrupt is received new TX data can be written or RX data retrieved An effici...

Page 12: ...Control Register RL1_CHAN_1_RX_CONTROL 0x005C Channel 1 RX Control Register RL1_CHAN_1_TX_START 0x0060 Channel 1 TX Start Latch RL1_CHAN_1_RX_START 0x0064 Channel 1 RX Start Latch RL1_CHAN_1_RX_BYTE_C...

Page 13: ...art Latch RL1_CHAN_5_RX_BYTE_COUNT 0x0114 Channel 5 RX Byte Count RL1_CHAN_6_CONTROL 0x0118 Channel 6 Control Register RL1_CHAN_6_STATUS 0x011C Channel 6 Status Register RL1_CHAN_6_WR_DMA_PNTR 0x0120...

Page 14: ...except PLL enable which defaults to enabled high on power up or reset PLL Enable When this bit is set to a one the signals used to program and read the PLL are enabled PLL Sclk Sdata Output These sig...

Page 15: ...this port The bits are read as the lowest byte in the port Access the read only port as a long word and mask off the undefined bits The dip switch positions are defined in the silkscreen For example t...

Page 16: ...reset When these bits are zero normal FIFO operation is enabled FIFO Bypass Enable When this bit is set to a one any data written to the transmit FIFO will be immediately transferred to the receive FI...

Page 17: ...occur at the same time Auto Direction Switch Enable When this bit is set to a one and the channel I O is operating in half duplex mode the I O interface will automatically change directions when the...

Page 18: ...nsmit Data Valid 2 Transmit FIFO Full 1 Transmit FIFO Almost Empty 0 Transmit FIFO Empty FIGURE 7 PMC BISERIAL III RL1 CHANNEL STATUS PORT Transmit FIFO Empty When a one is read the transmit data FIFO...

Page 19: ...ve Done Interrupt Occurred When a one is read it indicates that the receive state machine has received at least one complete message At least one byte must have been received and then the receive data...

Page 20: ...has occurred This bit is latched and can be cleared by writing back to the Status register with a one in this bit position Receive FIFO Overflow Occurred When a one is read it indicates that an attem...

Page 21: ...the data to write to the device the second is the length in bytes of that block and the third is the address of the next chaining descriptor in the list of buffer memory blocks This process is contin...

Page 22: ...e data from the device will be stored the second is the length in bytes of that block and the third is the address of the next chaining descriptor in the list of buffer memory blocks This process is c...

Page 23: ...C BISERIAL III RL1 TX ALMOST EMPTY LEVEL REGISTER This read write port accesses the transmitter almost empty level register When the number of data words in the transmit data FIFO is equal or less tha...

Page 24: ...the FIFO data has been sent otherwise it will occur when the byte count request has been satisfied In either case at least one byte must be sent to constitute a transmitted message TX FIFO Almost Emp...

Page 25: ...X FIFO Overflow Interrupt Enable 2 RX FIFO Almost Full Interrupt Enable 1 Receive Done Interrupt Enable 0 Receiver Enabled read only FIGURE 16 PMC BISERIAL III RL1 RX CONTROL REGISTER Receiver Enabled...

Page 26: ...ould excessively attenuate the signal When this bit is zero the termination is disabled Receive Two Stop Bits Select When this bit is set to a one the Receiver will expect two stop bits to terminate a...

Page 27: ...TX_CONTROL register bit 0 TX Byte Count This 16 bit field determines the number of bytes to send when the transmitter is enabled If TX Byte Count is equal to zero transmit data will be sent until the...

Page 28: ...Bit Description 31 16 Spare 15 0 RX Bytes Received FIGURE 19 PMC BISERIAL III RL1 RX BYTE COUNT PORT RX Bytes Received This field represents the number of bytes received in the last message The value...

Page 29: ...RX2 DATA TX3 DATA pin 7 pin 8 RX3 DATA TX3 DATA pin 41 pin 42 RX3 DATA TX4 DATA pin 9 pin 10 RX4 DATA TX4 DATA pin 43 pin 44 RX4 DATA TX5 DATA pin 11 pin 12 RX5 DATA TX5 DATA pin 45 pin 46 RX5 DATA TX...

Page 30: ...ication but not needed by this design TCK 12V 1 2 GND INTA 3 4 5 6 BUSMODE1 5V 7 8 9 10 GND 11 12 CLK GND 13 14 GND 15 16 5V 17 18 AD31 19 20 AD28 AD27 21 22 AD25 GND 23 24 GND C BE3 25 26 AD22 AD21 2...

Page 31: ...d by the specification but not needed by this design 12V 1 2 TMS TDO 3 4 TDI GND 5 6 GND 7 8 9 10 11 12 RST BUSMODE3 13 14 BUSMODE4 15 16 GND 17 18 AD30 AD29 19 20 GND AD26 21 22 AD24 23 24 IDSEL AD23...

Page 32: ...42 IO_8p TX4 DATA IO_8m TX4 DATA 9 43 IO_9p RX4 DATA IO_9m RX4 DATA 10 44 IO_10p TX5 DATA IO_10m TX5 DATA 11 45 IO_11p RX5 DATA IO_11m RX5 DATA 12 46 IO_12p TX6 DATA IO_12m TX6 DATA 13 47 IO_13p RX6 D...

Page 33: ...cess it Many BIOS will display the PCI devices found at boot up on a splash screen with the VendorID and CardId and an interrupt level Look quickly if the information is not available from the BIOS th...

Page 34: ...ed upon the temperature coefficient of the base FR4 material of 0 31 W m C and taking into account the thickness and area of the PMC The coefficient means that if 2 17 Watts are applied uniformly on t...

Page 35: ...ue to improper packaging of returned items For service on Dynamic Engineering Products not purchased directly from Dynamic Engineering contact your reseller Products returned to Dynamic Engineering fo...

Page 36: ...ces all registers to 0 except as noted Access Modes LW boundary Space see memory map Wait States One for all addresses Interrupt TX message sent RX message received TX FIFO almost empty RX FIFO almost...

Page 37: ...le from the manufacturer s web site ROHS Add for ROHS processing Standard soldering and parts used otherwise ET Industrial Temperature option 40 85C parts used CC Conformal Coating option Note The Eng...

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