Embedded Solutions
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Receive FIFO Overflow Interrupt Enable: When this bit is set to a one, the receive FIFO
overflow interrupt is enabled. An interrupt will be asserted, provided the master
interrupt is enabled when an attempt is made to write to a full receive FIFO. When this
bit is zero, the receive FIFO overflow interrupt is disabled.
Receive Start Clear Enable: When this bit is set to a one, the RX start latch will be
cleared when the current Receive message completes. When this bit is zero, the RX
start latch will remain set until the Receiver is disabled.
Receiver Termination Enable: When this bit is set to a one, the 100
Ω
receiver I/O shunt
termination is enabled when the I/O line is operating in full-duplex mode or in half-
duplex mode with the transmitter disabled. This termination is used to reduce noise on
the I/O line. If more than one receiver is being driven by the same source, be careful
not to enable more than one termination as this could excessively attenuate the signal.
When this bit is zero, the termination is disabled.
Receive Two Stop-Bits Select: When this bit is set to a one, the Receiver will expect two
stop-bits to terminate a data-byte. When this bit is zero, only one stop-bit will be
expected. If the expected stop bits are not received as ones, a framing error will be
latched.
Receive Parity Enable: When this bit is set to a one, a parity bit will be expected after
the eight data-bits and before the stop-bit(s). When this bit is zero, no parity bit will be
expected. If parity is enabled and the parity bit does not match the calculated value, a
parity error will be latched.
Receive Odd Parity Select: When this bit is set to a one, odd parity will be used to
determine the polarity of the expected parity bit, provided the Parity Level Select bit is a
zero. When this bit is zero, even parity will be used.
Receive Parity Level Select: When this bit is set to a one, the expected parity bit will be
equal to the value of the Odd Parity Select bit. When this bit is zero, the polarity of the
expected parity bit will be calculated using odd or even parity as determined by the Odd
Parity Select bit.
