Embedded Solutions
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empty. When this bit is a zero, it indicates that there is no data in this holding register.
Receive FIFO Empty: When a one is read, the receive data FIFO contains no data;
when a zero is read, there is at least one data word in the FIFO.
Receive FIFO Almost Full: When a one is read, the number of data words in the receive
data FIFO is greater or equal to the value written to the RL1_CHAN_RX_AFL_LVL
register; when a zero is read, the FIFO level is less than that value.
Receive FIFO Full: When a one is read, the receive data FIFO is full; when a zero is
read, there is room for at least one more data-word in the FIFO.
Receive Data Valid: When a one is read, there is at least one valid receive data word
left. This bit can be set even if the receive FIFO is empty, because as soon as the first
four words are written into the FIFO, they are read out to fill the receive data pipe-line to
be ready for a PCI read DMA or single word access. When this bit is a zero, it indicates
that there is no valid receive data remaining.
Transmit Done Interrupt Occurred: When a one is read, it indicates that the transmit
state-machine has completed a message. A zero indicates that a transmit message
has not been completed. This bit is latched and can be cleared by writing back to the
Status register with a one in this bit position.
Receive Done Interrupt Occurred: When a one is read, it indicates that the receive
state-machine has received at least one complete message. At least one byte must
have been received and then the receive data line must be idle for at least eight bit-
periods for a message be considered completed. A zero indicates that a complete
message has not been received. This bit is latched and can be cleared by writing back
to the Status register with a one in this bit position.
TX FIFO Almost Empty Interrupt Occurred: When a one is read, it indicates that the TX
FIFO was not almost empty and then the FIFO data count became less than or equal to
the value in the RL1_CHAN_TX_AMT_LVL register. A zero indicates that the FIFO has
not become almost empty. This bit is latched and can be cleared by writing back to the
Status register with a one in this bit position.
RX FIFO Almost Full Interrupt Occurred: When a one is read, it indicates that the RX
FIFO data count has become greater than or equal to the value in the
RL1_CHAN_RX_AFL_LVL register. A zero indicates that the FIFO has not become
almost full. This bit is latched and can be cleared by writing back to the Status register
with a one in this bit position.
Write/Read DMA Error Occurred: When a one is read, a write or read DMA error has
been detected. This will occur if there is a target or master abort or if the direction bit in
the next pointer of one of the chaining descriptors is incorrect. A zero indicates that no
write or read DMA error has occurred. These bits are latched and can be cleared by
