Embedded Solutions
Page 16 of 37
RL1_CHAN_0-7_CONTROL
[0x0010, 3C, 68, 94, C0, EC, 118, 144] Channel Control Register (read/write)
Channel Control Register
Data Bit
Description
31-17
Spare
16
Divided Clock Select
15-12
Clock Divisor
11
PLL Clock A Select
10
Auto Direction Switch Enable
9
Full-Duplex Enable
8
Receive DMA Priority Arbitration Enable
7
Transmit DMA Priority Arbitration Enable
6
Read DMA Interrupt Enable
5
Write DMA Interrupt Enable
4
Force Interrupt
3
Master Interrupt Enable
2
FIFO Bypass Enable
1
Receive FIFO Reset
0
Transmit FIFO Reset
FIGURE 6
PMC-BISERIAL-III RL1 CHANNEL CONTROL REGISTER
Transmit/Receive FIFO Reset: When these bits are set to a one, the transmit and/or
receive FIFOs will be reset. When these bits are zero, normal FIFO operation is
enabled.
FIFO Bypass Enable: When this bit is set to a one, any data written to the transmit FIFO
will be immediately transferred to the receive FIFO. This allows for fully testing the data
FIFOs without using the I/O. When this bit is zero, normal FIFO operation is enabled.
Master Interrupt Enable: When this bit is set to a one, all enabled interrupts (except the
DMA interrupts) will be gated through to the PCI host; when this bit is a zero, the
interrupts can be used for status without interrupting the host.
Force Interrupt: When this bit is set to a one, a system interrupt will occur provided the
master interrupt enable is set. This is useful for interrupt testing.
Write/Read DMA Interrupt Enable: These two bits, when set to one, enable the
interrupts for DMA writes and reads respectively. The DMA interrupts are not affected
by the Master Interrupt Enable.
