Embedded Solutions
Page 25 of 37
added.
Transmit Odd Parity Select: When this bit is set to a one, odd parity will be used to
determine the polarity of the parity bit, provided the Parity Level Select bit is a zero.
When this bit is zero, even parity will be used.
Transmit Parity Level Select: When this bit is set to a one, the parity bit will be equal to
the value of the Odd Parity Select bit. When this bit is zero, the polarity of the parity bit
will be calculated using odd or even parity as determined by the Odd Parity Select bit.
RL1_CHAN_0-7_RX_CONTROL
[0x0030, 5C, 88, B4, E0, 10C, 138, 164] Channel Control Register (read/write)
Channel Control Register
Data Bit
Description
31-10
Spare
9
Receive Parity Level Select
8
Receive Odd Parity Select
7
Receive Parity Enable
6
Receive Two Stop-Bits Select
5
Receiver Termination Enable
4
Receive Start Clear Enable
3
RX FIFO Overflow Interrupt Enable
2
RX FIFO Almost Full Interrupt Enable
1
Receive Done Interrupt Enable
0
Receiver Enabled (read only)
FIGURE 16
PMC-BISERIAL-III RL1 RX CONTROL REGISTER
Receiver Enabled: When a one is read, the Receive state-machine is enabled and
either a message is in progress or it is waiting for a message to begin; when a zero is
read, the state-machine is disabled.
Receiver Done Interrupt Enable: When this bit is a one the Receiver interrupt is
enabled. The interrupt will occur when the Receive state-machine receives a complete
message. This will occur when the at least one byte has been received and then the
receive data line is idle for at least eight bit-periods.
RX FIFO Almost Full Interrupt Enable: When this bit is set to a one, the receive FIFO
almost full interrupt is enabled. An interrupt will be asserted when the FIFO level
becomes greater than or equal to the count in the RL1_CHAN0-7_RX_AFL_LVL
register, provided the master interrupt enable is asserted. When this bit is zero, the RX
FIFO almost full interrupt is disabled.
