Embedded Solutions
Page 17 of 37
Transmit / Receive DMA Priority Arbitration Enable: When this bit is set to a one, the
corresponding DMA channel will get priority if it is near the limit of its FIFO (almost
empty for the TX or almost full for the RX). These limits are derived from the
programmable counts in the RL1_CHAN_0-7_TX_AMT_LVL and RL1_CHAN_0-
7_RX_AFL_LVL registers.
Full-Duplex Enable: When this bit is set to a one, the respective channel I/O will operate
in full-duplex mode. This means the transmit and receive data are transferred on
separate I/O lines and these transfers can occur simultaneously. When this bit is zero,
the I/O will operate in half-duplex mode. This means the transmit and receive data are
transferred on the same I/O line (the full-duplex transmit I/O line) and the transfers
cannot occur at the same time.
Auto Direction Switch Enable: When this bit is set to a one, and the channel I/O is
operating in half-duplex mode, the I/O interface will automatically change directions
when the current message completes provided transmit and receive interfaces are both
enabled. When this bit is zero, the I/O interface will not switch directions unless
explicitly commanded to do so.
PLL Clock A Select: When this bit is set to a one, the PLL clock A is selected for the I/O
reference clock. When this bit is zero, the PLL clock B is selected for the I/O reference
clock.
Clock Divisor: This field determines the reference clock divisor. The formula for
determining the divisor is 2 * (n + 1) where n is the value of this 4-bit field e.g. if n = 0
the divisor equals 2, if n = 1 the divisor equals 4, … if n = 15 the divisor equals 32.
Divided Clock Select: When this bit is set to a one, the divided clock is selected as the
16x reference clock for the channel I/O. When this bit is zero, the undivided PLL clock
is selected.
